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document number: 313070-003 intel ? 5000x chipset memory controller hub (mch) datasheet september 2006
2 intel? 5000x chipset memory controller hub (mch) datasheet information in this document is provided in conne ction with intel? products. no license, express or implied, by estoppel or otherwise, to any intellectual proper ty rights is granted by this document. except as provided in intel's terms and condit ions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, rela ting to sale and/or use of intel products including liability or warranties relating to fitness for a particul ar purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel pr oducts are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? int el reserves these for future definition and shall have no responsib ility whatsoever for conflicts or incompatibilities arising fro m future changes to them. the intel ? 5000 series chipsets, dual core intel ? xeon ? processor 5000 sequence and intel ? 631xesb/632xesb i/o controller hub may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. 64-bit intel ? xeon ? processors with intel ? em64t requires a computer system with a processor, chipset, bios, os, device drivers and applications enab led for intel em64t. processor will no t operate (including 32-bit operati on) without an intel em64t-enable d bios. performance will vary depending on your hardware and so ftware configurations. intel em 64t-enabled os, bios, device drivers and applications may not be available. check with your vendor for more information. contact your local intel sales office or your distributor to obta in the latest specifications an d before placing your product o rder. i 2 c is a two-wire communications bus/protocol developed by philips. smbus is a subset of the i 2 c bus/protocol and was developed by intel. implementations of the i 2 c bus/protocol may require licenses from various entities, including philips electronics n.v. and north american ph ilips corporation. intel, pentium, and xeon are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states and other countries. *other brands and names are the property of their respective owners. copyright ? 2005-2006, intel corporation.
intel? 5000x chipset memory co ntroller hub (mch) datasheet 3 contents 1introduction ............................................................................................................ 13 1.1 terminology ..................................................................................................... 13 1.2 related documents ........................................................................................... 19 1.3 intel? 5000x chipset overview .......................................................................... 19 2 signal description ................................................................................................... 23 2.1 processor front side bus signals ......................................................................... 25 2.1.1 processor front side bus 0 ...................................................................... 25 2.1.2 processor front side bus 1 ...................................................................... 27 2.2 fully buffered dimm memory channels................................................................. 29 2.2.1 fb-dimm branch 0 ................................................................................. 29 2.2.2 fb-dimm branch 1 ................................................................................. 30 2.3 pci express* signal list ..................................................................................... 30 2.3.1 pci express* common signals ................................................................. 30 2.3.2 pci express port 0, enterprise south bridge interface (esi) ......................... 31 2.3.3 pci express port 2.................................................................................. 31 2.3.4 pci express port 3.................................................................................. 31 2.3.5 pci express* graphics port...................................................................... 32 2.4 system management bus interfaces .................................................................... 33 2.5 xd port signal list............................................................................................. 33 2.6 jtag bus signal list .......................................................................................... 33 2.7 clocks, reset and miscellaneous .......................................................................... 34 2.8 power and ground signals .................................................................................. 34 2.9 mch sequencing requirements ........................................................................... 34 2.10 reset requirements........................................................................................... 36 2.10.1 timing diagrams .................................................................................... 36 2.10.2 reset timing requirements ..................................................................... 38 2.10.3 miscellaneous requirements and limitations .............................................. 39 2.11 intel? 5000p chipset platform signal routing topology diagrams ........................... 40 2.11.1 intel? 5000p customer reference platform (srp) reset topology ................ 41 2.12 signals used as straps....................................................................................... 41 2.12.1 functional straps ................................................................................... 41 3 register description ................................................................................................ 43 3.1 register terminology ......................................................................................... 43 3.2 platform configuration structure .................. ....................................................... 44 3.3 routing configuration accesses ........................................................................... 47 3.3.1 standard pci bus configuration mechanism ............................................... 47 3.3.2 pci bus 0 configuration mechanism .......................................................... 47 3.3.3 primary pci and downstream configuration mechanism............................... 48 3.4 device mapping................................................................................................. 48 3.4.1 device identification for intel 5000p chipset, intel 5000z chipset, and intel 5000v chipset components........................................................ 49 3.4.2 special device and function routing ....... .................................................. 50 3.5 i/o mapped registers ........................................................................................ 51 3.5.1 cfgadr: configuration address register................................................... 51 3.5.2 cfgdat: configuration data register ....... ................................................ 52 3.6 mch fixed memory mapped registers .................................................................. 52 3.7 detailed configuration space maps ...................................................................... 53 3.8 register definitions ........................................................................................... 72 3.8.1 pci standard registers ........................................................................... 72 3.8.2 address mapping registers ...................................................................... 81 3.8.3 amb memory mapped registers................................................................ 90
4 intel? 5000x chipset memory controller hub (mch) datasheet 3.8.4 interrupt redirection registers .................................................................93 3.8.5 boot and reset registers .........................................................................94 3.8.6 control and interrupt registers ................................................................98 3.8.7 pci express device configuration registers .............................................. 100 3.8.8 pci express header .............................................................................. 102 3.8.9 pci express power management capability structure........ .......... ........... .... 131 3.8.10 pci express message signaled interrupt s (msi) capability structure............ 134 3.8.11 pci express capability struct ure ................... .......... ........... ........ ............. 138 3.8.12 pci express advanced error reporting capa bility ........... .......... ........... ...... 160 3.8.13 error registers ..................................................................................... 182 3.9 memory control registers ................................................................................. 194 3.9.1 mc - memory control settings ................................................................ 194 3.9.2 gblact - global activation throttle regist er ............................................ 196 3.9.3 thrtsts[1:0] - thermal throttling status register................................... 197 3.9.4 thrtlow - thermal throttling low register ............................................ 198 3.9.5 thrtmid - thermal throttle mid register ................................................ 198 3.9.6 thrthi - thermal throttle high register ................................................. 199 3.9.7 thrtctrl - thermal throttling control regi ster ....................................... 199 3.9.8 mca - memory control settings a ........................................................... 199 3.9.9 ddrfrq - ddr frequency ratio ............................................................. 200 3.9.10 fbdtohostgrcfg0: fb-dimm to host gear ratio configuration 0.............. 200 3.9.11 fbdtohostgrcfg1: fb-dimm to host gear ratio configuration 1.............. 201 3.9.12 hosttofbdgrcfg: host to fb-dimm gear ratio configuration .................. 202 3.9.13 grfbdvldcfg: fb-dimm valid configuration ........................................... 202 3.9.14 grhostfullcfg: host full flow control configuration.............................. 204 3.9.15 grbubblecfg: fb-dimm host bubble configuration ................................. 204 3.9.16 grfbdtohostdblcfg: fb-dimm to host double configuration ................. 205 3.9.17 summary of memory gearing register operating modes ............................ 205 3.9.18 drta - dram timing register a ............................................................. 205 3.9.19 drtb - ddr timing register b ............................................................... 207 3.9.20 errper - error period ........................................................................... 208 3.9.21 memory map registers .......................................................................... 208 3.9.22 fb-dimm error registers........................................................................ 210 3.9.23 fb-dimm branch registers ..................................................................... 225 3.9.24 fb-dimm ras registers......................................................................... 234 3.9.25 fb-dimm intel ibist registers ............................................................... 237 3.9.26 serial presence detect registers ............................................................. 252 3.10 dma engine configuration registers ................................................................... 253 3.10.1 pcicmd: pci command register ............................................................ 253 3.10.2 pcists: pci status register .................................................................. 255 3.10.3 ccr: class code register ...................................................................... 256 3.10.4 cb_bar: dma engine base address register ............................................ 256 3.10.5 capptr: capability pointer re gister ................ ........... ............ ........... ...... 257 3.10.6 intl: interrupt line register.................................................................. 257 3.10.7 intp: interrupt pin register ................................................................... 257 3.10.8 power management capability structure ..... ........................ ........ ............. 257 3.10.9 msicapid - message signalled interrupt capability id register ......... .......... 260 3.10.10msinxptr - message signalled interrupt next pointer register ................... 260 3.10.11msictrl - message signalled interrupt control register ............................ 260 3.10.12msiar: message signalled interrupt address register ............................... 262 3.10.13msidr: message signalled interrupt data register.................................... 262 3.10.14pexcapid: pci express capability id register .......................................... 263 3.10.15pexnptr: pci express next pointer register ............................................ 263 3.10.16pexcaps - pci express capabilities regist er .......... ........... .......... ............. 264 3.10.17pexdevcap - device capabilities register ................................................ 264 3.10.18pexdevctrl - device control register .................................................... 265
intel? 5000x chipset memory co ntroller hub (mch) datasheet 5 3.10.19pexdevsts - pci express device status register ..................................... 266 3.11 pci express intel ibist registers ...................................................................... 267 3.11.1 dioibstr: pci express intel ibist global start/status register................. 267 3.11.2 dio0ibstat: pci express intel ibist completion status register............... 268 3.11.3 dio0iberr: pci express intel ibist error register................................... 268 3.11.4 pex[7:2,0]ibctl: pex intel ibist control register ................................... 269 3.11.5 pex[7:2,0]ibsymbuf: pex intel ibist symbol buffer ............................... 270 3.11.6 pex[7:2,0]ibextctl: pex intel ibist extended control register ................ 271 3.11.7 pex[7:2,0]ibdlysym: pex intel ibist delay symbol ................................ 273 3.11.8 pex[7:2,0]ibloopcnt: pex intel ibist loop counter ............................... 273 3.11.9 pex[7:2,0]iblns[3:0]: pex intel ibist lane status ................................. 274 3.11.10dio[1:0]squelch_cnt: pcie cluster squelch count................................ 275 4 system address map ............................................................................................. 277 4.1 system memory address ranges ....................................................................... 278 4.1.1 32/64-bit addressing ............................................................................ 278 4.2 compatibility area ........ .................. ............ ........... ........... ............ ......... .......... 280 4.2.1 ms-dos area (0 0000h?9 ffffh) ............... .......... ........... ........... ............ 280 4.2.2 legacy vga ranges (a 0000h?b ffffh) .................................................. 281 4.2.3 expansion card bios area (c 0000h?d ffffh).............. .......... ........... ...... 282 4.2.4 lower system bios area (e 0000h?e ffffh) ...... .............. ........... ............ 282 4.2.5 upper system bios area (f 0000h?f ffffh) ........................................... 283 4.3 system memory area....................................................................................... 283 4.3.1 system memory ................................................................................... 283 4.3.2 15 mb - 16 mb window (isa hole).......................................................... 283 4.3.3 extended smram space (tseg) ............................................................. 283 4.3.4 memory mapped configuration (mmcfg) region ....................................... 284 4.3.5 low memory mapped i/o (mmio) ........................................................... 285 4.3.6 chipset specific range .......................................................................... 286 4.3.7 interrupt/smm region........................................................................... 286 4.3.8 high extended memory ......................................................................... 288 4.3.9 main memory region ............................................................................ 289 4.4 memory address disposition ............................................................................. 289 4.4.1 registers used for address routing......................................................... 289 4.4.2 address disposition for processor ........................................................... 290 4.4.3 inbound transactions ........................................................................... 293 4.5 i/o address map ............................................................................................. 295 4.5.1 special i/o addresses ........................................................................... 295 4.5.2 outbound i/o access ............................................................................ 295 4.6 configuration space ........................................................................................ 297 4.7 i/o address map ............................................................................................. 297 4.7.1 special i/o addresses ........................................................................... 297 4.7.2 outbound i/o access ............................................................................ 298 4.8 configuration space ........................................................................................ 298 5 functional description ........................................................................................... 299 5.1 processor front side buses ............................................................................... 299 5.1.1 fsb overview ...................................................................................... 299 5.1.2 fsb dynamic bus inversion ................................................................... 300 5.1.3 fsb interrupt overview......................................................................... 300 5.2 snoop filter.................................................................................................... 301 5.2.1 snoop filter address bit mapping............................................................ 304 5.2.2 operations and interfaces ..................................................................... 304 5.3 system memory controller ............................................................................... 305 5.3.1 memory population rules ...................................................................... 307 5.3.2 fully buffered dimm technology and orga nization .................................... 310 5.3.3 fb-dimm memory operating modes ........................................................ 312
6 intel? 5000x chipset memory controller hub (mch) datasheet 5.3.4 data poisoning in memory...................................................................... 314 5.3.5 patrol scrubbing ................................................................................... 314 5.3.6 demand scrubbing ............................................................................... 315 5.3.7 x8 correction ....................................................................................... 315 5.3.8 single device data correction (sddc) support ......................................... 316 5.3.9 fb-dimm memory configuration mechanism ............................................. 316 5.3.10 fb-dimm memory failure isolation mechanisms ........................................ 318 5.3.11 ddr2 protocol ...................................................................................... 322 5.3.12 memory thermal management................................................................ 322 5.3.13 electrical throttling ............................................................................... 333 5.4 behavior on overtemp state in amb................................................................... 333 5.5 interrupts ....................................................................................................... 334 5.6 xapic interrupt message delivery...................................................................... 334 5.6.1 xapic interrupt message format ............................................................ 334 5.6.2 xapic destination modes ....................................................................... 335 5.6.3 interrupt redirection ............................................................................. 336 5.6.4 eoi..................................................................................................... 338 5.7 i/o interrupts ................................................................................................. 338 5.7.1 ordering.............................................................................................. 338 5.7.2 hardware irq ioxapic interrupts ........................................................... 339 5.7.3 message signalled interrupts ................................................................. 339 5.7.4 non-msi interrupts - ?fake msi? ............................................................ 339 5.8 interprocessor interrupts (ipis) ......................................................................... 340 5.9 chipset generated interrupts ............................................................................ 342 5.9.1 intel 5000x chipset generation of msis .................................................. 344 5.10 legacy/8259 interrupts .................................................................................... 346 5.11 interrupt error handling ................................................................................... 346 5.12 enterprise south bridge interface (esi) .............................................................. 347 5.12.1 power management support................................................................... 348 5.12.2 special interrupt support....................................................................... 348 5.12.3 inbound interrupts ............................................................................... 348 5.12.4 legacy interrupt messages .................................................................... 349 5.12.5 end-of-interrupt (eoi) support .............................................................. 349 5.12.6 error handling...................................................................................... 349 5.13 pci express ports ............................................................................................ 349 5.13.1 intel 5000x chipset mch pci express port overview ................................ 350 5.13.2 enterprise south bridge interface (esi) ................................................... 351 5.13.3 pci express ports 2 and 3 ...................................................................... 351 5.13.4 pci express general purpose ports.......................................................... 352 5.13.5 supported length width port partitioning ................................................. 353 5.13.6 pci express port support summary ........................................................ 354 5.13.7 pci express port physical layer characteri stics ......................................... 355 5.13.8 link layer............................................................................................ 357 5.13.9 flow control......................................................................................... 359 5.13.10transaction layer ................................................................................. 361 5.14 power management.......................................................................................... 361 5.14.1 supported acpi states .......................................................................... 361 5.14.2 fb-dimm thermal management .............................................................. 362 5.14.3 fb-dimm thermal diode overview .......................................................... 362 5.15 system reset.................................................................................................. 362 5.15.1 mch power sequencing ......................................................................... 362 5.15.2 mch reset types.................................................................................. 363 5.15.3 targeted reset mechanism .................................................................... 364 5.15.4 binit# mechanism ............................................................................... 365 5.15.5 reset sequencing ................................................................................. 365 5.16 smbus interfaces description ............................................................................ 366
intel? 5000x chipset memory co ntroller hub (mch) datasheet 7 5.16.1 internal access mechanism .................................................................... 367 5.16.2 smbus transaction field definitions .......... .............................................. 368 5.16.3 smb transaction pictographs ................................................................. 371 5.16.4 slave sm bus, sm bus 0........................................................................ 373 5.16.5 fb-dimm spd interface, sm buses 1, 2, 3 and 4 ...................................... 378 5.16.6 pci express hot-plug support, sm bus 6 ................................................. 379 5.16.7 hot-plug controller ............................................................................... 380 5.16.8 pci express hot-plug usage model.......................................................... 380 5.16.9 virtual pin ports ................................................................................... 381 5.17 clocking......................................................................................................... 384 5.17.1 reference clocks.................................................................................. 384 5.17.2 jtag .................................................................................................. 386 5.17.3 smbus clock........................................................................................ 386 5.17.4 gpio serial bus clock ........................................................................... 386 5.17.5 clock pins ........................................................................................... 386 5.17.6 high frequency clocking support ........................................................... 387 5.18 error list........................................................................................................ 388 6 testability ............................................................................................................. 395 6.1 jtag port ....................................................................................................... 395 6.1.1 jtag access to configuration space........................................................ 395 6.1.2 tap signals ......................................................................................... 395 6.1.3 accessing the tap logic ........................................................................ 396 6.1.4 reset behavior of the tap ..................................................................... 398 6.1.5 clocking the tap .................................................................................. 398 6.1.6 accessing the instruction register .......................................................... 398 6.1.7 accessing the data registers ................................................................. 400 6.1.8 public tap instructions.......................................................................... 400 6.1.9 public data instructions ........................................................................ 401 6.1.10 public data register control................. .................................................. 402 6.1.11 bypass register ................................................................................... 402 6.1.12 device id register................................................................................ 402 6.1.13 boundary scan register ........................................................................ 403 6.2 extended debug port (xdp) .............................................................................. 404 7 electrical characteristics ....................................................................................... 405 7.1 absolute maximum ratings............................................................................... 405 7.1.1 thermal characteristics......................................................................... 405 7.1.2 power characteristics............................................................................ 405 7.2 dc characteristics ........................................................................................... 406 7.2.1 clock dc characteristics........................................................................ 407 7.2.2 fsb interface dc characteristics ............ ................................................ 408 7.2.3 fb-dimm dc characteristics .................. ................................................ 409 7.2.4 pci express/ esi interface dc characterist ics .......................................... 410 7.2.5 miscellaneous dc characteristics ............................................................ 411 8 ballout and package information ........................................................................... 413 8.1 intel 5000x chipset mch ballout ....................................................................... 413 8.2 package information........................................................................................ 455 figures 1-1 intel? 5000x chipset system block diagram ........................................................ 21 2-1 intel 5000x chipset clock and reset requirements.............................................. 35 2-2 power-up ......................................................................................................... 36 2-3 pwrgood ....................................................................................................... 36 2-4 hard reset ....................................................................................................... 37 2-5 reseti# retriggering limitations ................. ....................................................... 37
8 intel? 5000x chipset memory controller hub (mch) datasheet 2-6 simplest power good distribution ........................................................................40 2-7 basic system reset distribution.................... .......................................................40 2-8 basic init# distribution ............................ .........................................................40 3-1 conceptual intel? 5000x chipset mch pci configuration diagram...........................46 3-2 type 1 configuration address to pci address mapping ............................................48 3-3 intel 5000p chipset mch implementation of srid and crid registers ......................77 3-4 pci express configuration space........................................................................ 102 3-5 pci express hot-plug interrupt flow................................................................... 157 3-6 fb-dimm reset timing ..................................................................................... 228 3-7 intel 5000p chipset dma error/channel completion interrupt handling flow............ 261 4-1 system memory address map............................................................................ 278 4-2 detailed memory system address map ............................................................... 279 4-3 interrupt /smm region ..................................................................................... 286 4-4 system i/o address space................................................................................ 296 4-5 system i/o address space................................................................................ 298 5-1 snoop filter .................................................................................................... 302 5-2 minimum two dimm configuration ..................................................................... 308 5-3 next two dimm upgrade positions ..................................................................... 308 5-4 single dimm operation mode............................................................................. 309 5-5 minimum mirrored mode memory configuration.... ................................................ 309 5-6 mirrored mode next upgrade ............................................................................. 310 5-7 fb-dimm channel schematic............................................................................. 311 5-8 connection of dimm serial i/o signals........... ..................................................... 317 5-9 code layout for single-channel branches ........................................................... 320 5-10 code layout for dual-channel branches .......... ................................................... 321 5-11 thermal throttling with thrmhunt=1................................................................ 326 5-12 thermal throttling with thrmhunt=0................................................................ 326 5-13 thermal throttling activation al gorithm .............................................................. 328 5-14 xapic address encoding ................................................................................... 335 5-15 pci express hot-plug interrupt flow................................................................... 343 5-16 mch to intel 631xesb/632xesb i/o controller hub enterprise south bridge interface.... 347 5-17 x4 pci express bit lane.................................................................................... 350 5-18 esi and pci express ports 2 and 3 ..................................................................... 351 5-19 mch to intel 631xesb/632xesb i/o controller hub port configurations .................. 352 5-20 intel 5000x chipset pci express* high performance x16 port ............................... 353 5-21 pci express packet visibility by physical layer. ............ ........... ............ ........... ...... 355 5-22 pci express elastic buffer (x4 example).............................................................. 356 5-23 pci express deskew buffer (4x example) ........................................................... 357 5-24 pci express packet visibility by link layer ..... ........... .......... ........... ........ ............. 358 5-25 pci express packet visibility by transaction laye r............. .............. ........ ............. 361 5-26 intel 5000p chipset power sequencing ............................................................... 362 5-27 power-on reset sequence ................................................................................ 366 5-28 mch sm bus interfaces .................................................................................... 367 5-29 dword configuration read protocol (smbus block write / block read, pec disabled) ................................................................................................. 371 5-30 dword configuration write protocol (smbus block write, pec disabled) ................ 371 5-31 dword memory read protocol (smbus bloc k write / bock read, pec disabled)....... 372 5-32 dword memory write protocol ...................... ................................................... 372 5-33 dword configuration read protocol (smbus word write / word read, pec disabled) ................................................................................................. 372 5-34 dword configuration write protocol (smbus word write, pec disabled)................. 372
intel? 5000x chipset memory co ntroller hub (mch) datasheet 9 5-35 dword memory read protocol (smbus word write / word read, pec disabled)...... 373 5-36 word configuration wrote protocol (smbus byte write, pec disabled) .................. 373 5-37 smbus configuration read (block write / block read, pec enabled) ....................... 375 5-38 smbus configuration read (word writes / word reads, pec enabled) .................... 376 5-39 smbus configuration read (write bytes / read bytes, pec enabled) ...................... 376 5-40 smbus configuration write (block write, pec enabled) ......................................... 376 5-41 smbus configuration write (word writes, pec enabled)........................................ 377 5-42 smbus configuration write (write bytes, pec enabled)......................................... 377 5-43 random byte read timing................................................................................ 378 5-44 byte write register timing ............................................................................... 379 5-1 pci express hot-plug/vpp block diagram............ ................................................ 382 6-1 simplified tap controller block diagram ............................................................. 396 6-2 tap controller state machine ............................................................................ 397 6-3 tap instruction register ................................................................................... 399 6-4 tap instruction register operation ............... ..................................................... 399 6-5 tap instruction register access......................................................................... 400 6-6 tap data register ........................................................................................... 401 6-7 bypass register implementation ....................................................................... 402 8-1 intel 5000x chipset quadrant map .................................................................... 413 8-2 intel 5000x chipset mch ballout left side (top view) .......................................... 414 8-3 intel 5000x chipset mch ballout center (top view) ............................................. 415 8-4 intel 5000x chipset mch ballout right side (top view) ........................................ 416 8-5 bottom view................................................................................................... 455 8-6 top view........................................................................................................ 456 8-7 package stackup ............................................................................................. 457 8-8 notes ............................................................................................................ 458 tables 1-1 general terminology.......................................................................................... 13 2-1 signal naming conventions ................................................................................ 24 2-2 buffer signal types ........................................................................................... 24 2-3 power up and hard reset timings ....................................................................... 38 2-4 critical intel? 5000p initialization timings ....... .................................................... 39 3-1 configuration address bit mapping................... .................................................... 49 3-2 memory control hub esi device identification ..... .................................................. 49 3-3 functions specially handled by the mch............................................................... 50 3-4 access to ?non-existent? register bits.................................................................. 51 3-5 i/o address: cf8h............................................................................................. 51 3-6 i/o address: cfch ............................................................................................ 52 3-7 mapping for fixed memory mapped registers ........................................................ 52 3-8 device 0, function 0: pci express pci space .... .................................................... 53 3-9 device 0, function 0: pci express extended re gisters............................................ 54 3-10 device 0, function 0: pci express intel? interconnect bist (intel? ibist) registers .................................................................................... 55 3-11 device 2-3, function 0: pci express pci space ..................................................... 56 3-12 device 2-3, function 0: pci express extended registers......................................... 57 3-13 device 2-3, function 0: pci express intel ibist registers....................................... 58 3-14 device 4, function 0: pci express pci space ........................................................ 59 3-15 device 4, function 0: pci express extended re gisters............................................ 60 3-16 device 4, function 0: pci express intel ibist registers.......................................... 61 3-17 device 5-7, function 0: pci express pci space ..................................................... 62 3-18 device 5-7, function 0: pci express extended registers......................................... 63
10 intel? 5000x chipset memory controller hub (mch) datasheet 3-19 device 5-7, function 0: pci express intel ib ist registers .......................................64 3-20 device 9, function 0: amb switching window registers ..........................................64 3-21 device 16, function 0: processor bus, boot, and interrupt ......................................65 3-22 device 16, function 1: memory branch map, control, errors ....................................66 3-23 device 16, function 2: ras .................................................................................67 3-24 device 21, 22, function 0: fb-dimm map, control, ras ..........................................68 3-25 device 21, function 0: fb-dimm 0 intel ibist registers .........................................69 3-26 device 21, function 0: fb-dimm 1 ibst regist ers .................................................70 3-27 device 22, function 0: fb-dimm 2 ibst register s ..................................................71 3-28 device 22, function 0: fb-dimm 3 intel ibist registers .........................................72 3-29 address mapping registers .................................................................................81 3-30 register offsets in amb memory mapped regi sters region ......................................92 3-31 xtpr index.......................................................................................................99 3-32 when will an intel 5000x chipset pci express* device be accessible? ............ ........ 100 3-33 intel 5000p chipset mch pc ists and secsts master/data parity error ras handling ................................................................................. 113 3-1 gio port mode selection ................................................................................... 125 3-34 iv handling and processing by mch ................................................................... 137 3-35 maximum link width default value for different pci express ports ......................... 147 3-36 negotiated link width for different pci express ports after training ...................... 150 3-37 global activation throttling as a function of global activation throttling limit (gblactm) and global throttling window mode (gtw_mode) register fields.......... 196 3-38 fb-dimm to host gear ratio mux ....................................................................... 201 3-39 fb-dimm to host gear ratio mux ....................................................................... 201 3-40 host to fb-dimm gear ratio mux select.............................................................. 202 3-41 fb-dimm host data cycle valid mux select ......................................................... 203 3-42 fb-dimm to host flow control mux select ........................................................... 204 3-43 fb-dimm bubble mux select.............................................................................. 204 3-44 fb-dimm to host double config mux select ......................................................... 205 3-45 optimum tref values as a function of core: fbd gear ratios (in fbd super frames) . 207 3-46 timing characteristics of errper.................. ..................................................... 208 3-47 interleaving of an address is governed by mir[ i].................................................. 209 3-48 nrecfbd mapping information....................... ................................................... 220 3-49 ecc locator mapping information ................... ................................................... 222 3-50 iv vector table for dma errors and interrupts .. ................................................... 263 4-1 memory segments and their attributes .............................................................. 280 4-2 pam settings................................................................................................... 282 4-3 low memory mapped i/o1 ................................................................................ 285 4-4 i/o apic address mapping ................................................................................ 287 4-5 intel 5000x chipset mch memory mapping registers ............................................ 289 4-6 address disposition for processor....................................................................... 290 4-7 enabled smm ranges ....................................................................................... 292 4-8 smm memory region access control from processor ............................................. 292 4-9 decoding processor requests to smm and vga sp aces ......................................... 293 4-10 address disposition for inbound transactions ... ................................................... 294 5-1 dbi[3:0]# / data bit correspondence................................................................. 300 5-1 snoop filter physical address partitioning ...... ..................................................... 304 5-2 fsb transaction encoding qualification for sf l ook up............................................ 304 5-3 snoop filter entry ............................................................................................ 304 5-2 minimum system memory configurations & up grade increments............................ 306 5-3 maximum 16 dimm system memory configurations.............................................. 307 5-4 maximum 16 dimm system memory configurations.............................................. 307
intel? 5000x chipset memory co ntroller hub (mch) datasheet 11 5-5 memory poisoning table................................................................................... 314 5-6 x8 double device detection characteristics....... .................................................. 316 5-7 spd addressing............................................................................................... 317 5-8 amb thermal status bit definitions ............... ..................................................... 323 5-9 fb_dimm bandwidth as a function of closed loop thermal throttling .................... 329 5-10 global activation throttling bw allocation as a function of gblactlm for a 16384**1344 window with mc.gtw_mode=0 (normal) ........................................ 332 5-11 electrical throttle window as a function of dimm technology ................................ 333 5-12 xapic data encoding ....................................................................................... 335 5-13 intel 5000x chipset xapic interrupt message routing and delivery ...................... 336 5-14 chipset generated interrupts............................................................................ 344 5-4 pci express link width strapping options fo r port cpci configuration in mch ......... 354 5-15 options and limitations.................................................................................... 354 5-16 pci express credit mapping for inbound transa ctions .......................................... 359 5-17 pci express credit mapping for outbound transactions ........................................ 360 5-18 mch reset classes .......................................................................................... 363 5-19 reset sequences and durations ........................................................................ 366 5-20 smbus transaction field summary .................................................................... 368 5-21 smbus address for product name platform ......................................................... 374 5-22 smbus command encoding............................................................................... 374 5-23 status field encoding for smbus reads .............................................................. 375 5-24 mch supported spd protocols........................................................................... 379 5-25 i/o port registers in i/o extender supported by intel 5000x chipset mch ............. 383 5-26 hot-plug signals on a virtual pin port ............ ..................................................... 384 5-27 intel 5000x chipset mch frequencies for processors and core ............................. 385 5-28 intel 5000x chipset mch frequencies for memory .............................................. 385 5-29 intel 5000x chipset mch frequencies for pci express ......................................... 386 5-30 clock pins ...................................................................................................... 386 5-31 intel 5000x chipset error list.......................................................................... 388 6-1 tap signal definitions ...................................................................................... 395 6-2 tap reset actions ........................................................................................... 398 6-3 public tap instructions..................................................................................... 401 6-4 actions of public tap instructions during va rious tap states................................. 402 6-5 intel? 5000p chipset device id codes ............................................................... 403 7-1 absolute maximum ratings............................................................................... 405 7-2 operating condition power supply rails ............. ................................................ 405 7-3 analog and bandgap voltage and current specific ations ....................................... 406 7-4 clock dc characteristics................................................................................... 407 7-5 fsb interface dc characteristics ....................................................................... 408 7-6 fb-dimm transmitter (tx) output dc characteristics ........................................... 409 7-7 fb-dimm receiver (rx) output dc characterist ics ............................................... 409 7-8 pci express/ esi differential transmitter (t x) output dc characteristics ................ 410 7-9 pci express/ esi differential receiver (rx) input dc characteristics ...................... 410 7-10 smbus dc characteristics................................................................................. 411 7-11 jtag dc characteristics ............................ ....................................................... 411 7-12 1.5 v cmos dc characteristics ......................................................................... 411 7-13 3.3 v cmos dc characteristics ......................................................................... 411 8-1 intel 5000x chipset mch signals (by ball number) .............................................. 417 8-2 intel 5000x chipset mch signals (by signal name) ............................................. 436
12 intel? 5000x chipset memory controller hub (mch) datasheet revision history revision number description date 0.5 initial release january 2004 001 final document release may 2006 002 added support for dual-core intel ? xeon ? 5100 series june 2006 003 dma section updated august 2006
intel ? 5000x chipset memory controller hub (mch) datasheet 13 introduction 1 introduction the intel ? 5000x chipset is designed for systems based on the dual-core intel ? xeon ? 5000 sequence and supports a fsb frequency up to 1333 mts. the intel 5000x chipset contains two main components: memory controller hub (mch) for the host bridge and the i/o controller hub for the i/o subsystem. the intel 5000x chipset uses the intel ? 631xesb/632xesb i/o controller hub for the i/o controller hub. this document is the datasheet for the intel 5000x chipset memory controller hub (mch) components. the intel 5000x chipset is packaged in a 1432 pin fcbga package with pins on 1.092 mm (37 mil) centers. the overall package dimensions are 42.5 mm by 42.5 mm. the intel 5000 series chipset platform supports the dual-core intel ? xeon ? 5000 series (1066 mhz with 2 mb l2 cache on 65nm process in a 771-land, fc-lga4 (flip chip land grid array 4) package and the dual-core intel ? xeon ? 5100 series (1333 mhz with 4 mb shared l2 cache) on 65nm process in a 771-land, fc-lga4 (flip chip land grid array 4) package. this package uses the matching lga771 socket. the surface mount, lga771 socket supports dire ct socket loading (dsl). the dual-core intel xeon 5000 sequence (1066/1333 mhz) returns a processor signature of 0f5xh where x is the stepping number when the cp uid instruction is executed with eax=1. note: unless otherwise specified, the term proc essor in this document refers to the dual-core intel xeon 5000 sequence processo rs at both 1066 mhz with 2 mb l2 cache and 1333 mhz with 4 mb shared l2 cache on 65nm process in the 771-pin fc-lga4 package. 1.1 terminology this section provides the definitions of some of the terms used in this document. table 1-1. general terminology (sheet 1 of 7) terminology description agent a logical device connected to a bus or shared interconnect that can either initiate accesses or be the target of accesses. each thread executing within a processor is a unique agent. aka also known as asserted asserted signal is set to a level that re presents logical true. for signals that end with ?#? this means driving a low voltage. fo r other signals, it is a high voltage. atomic operation a series of operations, any one of which cannot be observed to complete unless all are observed to complete. agp accelerated graphics port. in this document agp refers to the agp/pci interface that is in the mch. the mch agp interface su pports only 0.8 v/1. 5 v agp 2.0/agp 3.0 compliant devices using pci (66 mhz), agp 1x (66 mhz), 4x (266 mhz), and 8x (533 mhz) transfers. mch does not support any 3.3 v devices. for ag p 2.0, pipe# and sba addressing cycles and their associated data phases are generally referred to as agp transactions. frame# cycles are generally referred to as agp/pci transactions bank dram chips are divided into multiple banks internally. commodity parts are all 4 bank, which is the only type the mch supports. each bank acts somewhat like a separate dram, opening and closing pages independently, allowing different pages to be open in each. most commands to a dram target a specific bank, but some commands (that is, precharge all) are targeted at all banks. multiple banks allows higher performance by interleaving the banks and reducing page miss cycles.
introduction 14 intel ? 5000x chipset memory controller hub (mch) datasheet buffer 1. a random access memory structure. 2. the term i/o buffer is also used to desc ribe a low level input receiver and output driver combination. cache line the unit of memory that is copied to an d individually tracked in a cache. specifically, 64 bytes of data or instructions aligned on a 64-byte physical address boundary. cdm central data manager. a custom array wi thin the intel 5000x chipset that acts as a temporary repository for system data in flight between the various ports: fsb?s, fbd?s, esi, and pci express*. cfg, config abbreviation for ?configuration?. channel in the mch a fbd dram channel is the set of signals that connects to one set of fbd dimms. the mch has up to four dram channels. character the raw data byte in an encoded syst em (for example, the 8b value in a 8b/10b encoding scheme). this is the meaningful qu antum of information to be transmitted or that is received across an encoded transmission path. chipset core the mch internal base logic. coherent transactions that ensure that the processor's view of memory through the cache is consistent with that obtain ed through the i/o subsystem. command the distinct phases, cycles, or packets that make up a transaction. requests and completions are referred to generically as commands. completion a packet, phase, or cycle used to term inate a transaction on a interface, or within a component. a completion will always refer to a preceding request and may or may not include data and/or other information. core the internal base logi c in the intel 5000x chipset. crc cyclic redundancy check; a number derived from, and stored or transmitted with, a block of data in order to detect corruption. by recalculating the crc and comparing it to the value originally transmitted, the rece iver can detect some types of transmission errors. critical word first on the dram, processor, and memory interfaces, the requestor may specify a particular word to be delivered first. th is is done using address bits of lower significance than those required to sp ecify the cache line to be accessed. the remaining data is then returned in a standardized specified order. ddr double data rate sdram. ddr describes th e type of drams that transfers two data items per clock on each pin. this is the only type of dram supported by the mch. deasserted signal is set to a leve l that represents logical false. deferred transaction a processor bus split transaction. on the processor bus, the requesting agent receives a deferred response which allows other transactions to occur on the bus. later, the response agent completes the or iginal request with a separate deferred reply transaction or by deferred phase. delayed transaction a transaction where the target retrie s an initial request, but without notification to the initiator, forwards or services the request on behalf of the init iator and stores the completion or the result of the request. th e original initiator subsequently re-issues the request and receives the stored completion dfx (dfd, dfm, dft, dfv) dfd=design for debug dfm=design for manufacturing dft=design for testability dfv=design for validation dimm dual-in-line memory module. a packag ing arrangement of memory devices on a socketable substrate. double-sided dimm terminology often used to describe a dimm that contain two dram rows. generally a double-sided dimm contains two rows, with the exception noted above. this terminology is not used within this document. downstream see terminology entry of ?inbound (i b)/outbound (ob), aka upstream/downstream, northbound/southbound, upbound/downbound? dram page (row) the dram cells selected by the row address. table 1-1. general terminology (sheet 2 of 7) terminology description
intel ? 5000x chipset memory controller hub (mch) datasheet 15 introduction dword a reference to 32 bits of data on a naturally aligned four-byte boundary (that is, the least significant two bits of the address are 00b). ecc error correcting code esb2 intel ? 631xesb/632xesb i/o controller hub fbd fully buffered ddrii fbd channel one electrical interface to one or more fully buffered ddrii dimm. fsb processor front-side bus. this is the bu s that connects the processor to the mch. full duplex a connection or channel that allows da ta or messages to be transmitted in opposite directions simultaneously. gart graphics aperture re-map table. gart is a table in memory containing the page re- map information used during agp aperture address translations. gb/s gigabytes per second (10 9 bytes per second). gb/s gigabits per second (10 9 bits per second). gtlb graphics translation look-aside buffer. a cache used to store frequently used gart entries. hardwired a parameter that has a fixed value. half duplex a connection or channel that allows data or messages to be transmitted in either direction, but not simultaneously. host this term is used synonymously with processor. i/o 1. input/output. 2. when used as a qualifier to a transactio n type, specifies that transaction targets intel architecture-specific i/o space. (for example, i/o read) intel ? 631xesb/ 632xesb i/o controller hub 6th generation i/o controller hub. the io controller hub component that contains the legacy i/o functions. implicit writeback a snoop initiated data transfer from the bus agent wi th the modified cache line to the memory controller due to an access to that line. inband communication that is multiplexed on the st andard lines of an interface, rather than requiring a dedicated signal. inbound see terminology entry of ?inbound (ib)/outbound (ob), aka upstream/downstream, northbound/southbound, upbound/downbound.? incoming a transaction or data th at enters the intel 5000x chipset. inbound (ib)/ outbound (ob), aka upstream/ downstream, northbound/ southbound, upbound/downbound up, north, or inbound is in the direction of the processor, down, south, or outbound is in the direction of io (sdram, smbus). initiator the source of requests. an agent sending a request packet on pci express is referred to as the initiator for that transaction. the initiator may receive a completion for the request. isochronous a classification of transactions or a stream of transactions that require service within a fixed time interval. layer a level of abstraction commonly used in interface specifications as a tool to group elements related to a basic function of the interface within a layer and to identify key interactions between layers. legacy functional requirements handed down from previous chipsets or pc compatibility requirements from the past. line cache line. link the layer of an interface that handles flow control and often error correction by retry. lock a sequence of transactions that must be completed atomically. table 1-1. general terminology (sheet 3 of 7) terminology description
introduction 16 intel ? 5000x chipset memory controller hub (mch) datasheet lsb least significant bit lsb least significant byte master a device or logical entity that is capable of initiating transactions. a master is any potential initiator. master abort a response to an illegal request. reads receive a ll ones. writes have no effect. mb/s megabytes per second (10 6 bytes per second) mch the memory controller hu b component that contains the processor interface, dram controller, pci express interface, and agp interface. it communicates with the i/o controller hub (intel 631xesb/632xesb i/o controller hub) over a proprietary interconnect called the enterpri se south bridge interface (esi). mem used as a qualifier for transactions that target memory space. (for example, a mem read to i/o). memory issue committing a request to ddr or, in the case of a read, returning the read header. mesochronous distributed or common referenced clock. metastability a characteristic of flip flops that describes the state where the output becomes non- deterministic. most commonly caused by a setup or hold time violation. mirroring raid-1. please see raid for detail descriptions. mmio memory mapped io. any memory acce ss to pci express or 3gioc ports. mmcfg memory mapped configuration. a memory transaction that accesses configuration space. msb most significant bit. msb most significant byte. mtbf mean time between failure. non-coherent transactions that may cause the processor's view of memory through the cache to be different with that obtained through the i/o subsystem. outbound see terminology entry of ?inbound (i b)/outbound (ob), aka upstream/downstream, northbound/southbound, upbound/downbound.? outgoing a transaction or completion that exits the intel 5000x chipset. peer-to-peer transactions that occur between two devices below the pci express or esi ports. packet the indivisible unit of data transfer and routing, consisting of a header, data, and crc. page hit. an access to an open page, or dram row. the data can be supplied from the sense amps at low latency. page miss (empty page) an access to a page that is not buffered in sense amps and must be fetched from dram array. address bit permuting address bits are distributed among channel selects, dram selects, bank selects to so that a linear address stream accesses these resources in a certain sequence. page replace aka page miss, row hit/ page miss. an access to a row that has another page open. the page must be transferred back from the sense amps to the array, and the bank must be precharged. pci peripheral component interconnect local bu s. a 32-bit or 64-bit bus with multiplexed address and data lines that is primarily intended for use as an interconnect mechanism within a system between processor/memory and peripheral components or add-in cards. pci 2.3 compliant refers to compliance to the pci local bus specification , revision 2.3. plesiochronous each end of a link uses an independent clock reference. support of this operational mode places restrictions on the absolute frequency difference, as specified by pci express, which can be tolerated betwee n the two independent clock references. posted a transaction that is considered complete by the initiating agent or source before it actually completes at the target of the requ est or destination. all agents or devices handling the request on behalf of the original initiator must then treat the transaction as being system visible from the initiating in terface all the way to the final destination. commonly refers to memory writes. table 1-1. general terminology (sheet 4 of 7) terminology description
intel ? 5000x chipset memory controller hub (mch) datasheet 17 introduction primary pci the physical pci bus that is driv en directly by the intel? 631xesb/632xesb i/o controller hub component. communication between pci and the mch occurs over esi. note that even though the primary pci bus is referred to as pci it is not pci bus 0 from a configuration standpoint. push model method of messaging or data transfer that predominately uses writes instead of reads. queue a storage structure for information. anythi ng that enters a queue will exit eventually. the most common policy to select an entry to read from the queue is fifo (first in first out). raid redundant array of independent disks. raid improves performance by disk striping, which interleaves bytes or groups of bytes ac ross multiple drives, so more than one disk is reading and writing si multaneously. fault tolerance is achieved by mirroring or parity. mirroring is 100% duplication of the data on two drives (raid-1), and parity is used (raid-3 and 5) to calculate the data in two drives and store the results on a third: a bit from drive 1 is xor'd with a bit from drive 2, and the result bit is stored on drive 3 (see or for an explanation of xor) . a failed drive can be hot swapped with a new one, and the raid controller automati cally rebuilds the lost data. raid can be classified into the following categories: raid-0 ? raid-0 is disk striping only, which inte rleaves data across multiple disks for better performance. it does not provide safeguards against failure. raid-1 ? uses disk mirroring, which provides 100% duplication of data. offers highest reliability, but doubles storage cost. raid-2 ? bits (rather than bytes or groups of bytes) are interleaved across multiple disks. the connection machine used this technique, but this is a rare method. raid-3 ? data are striped across three or more drives. used to achieve the highest data transfer, because all drives operate in para llel. parity bits are stored on separate, dedicated drives. raid-4 ? similar to raid-3, but manages disks in dependently rather than in unison. not often used. raid-5 ? most widely used. data are striped across three or more drives for performance, and parity bits are used for fault tolerance. the parity bits from two drives are stored on a third drive. raid-6 ? highest reliability, but not widely used. similar to raid-5, but does two different parity computations or the same computation on overlapping subsets of the data. raid-10 ? actually raid-1,0. a combination of raid-1 and raid-0 (mirroring and striping). above definitions can be extended to dram memory system as well. to avoid confusion, the raid scheme for memory is referred as memory - raid. memory mirroring scheme is actually memory-raid-1. rasum reliability, availability, serviceability, usability, and manageability, which are all important characteristics of servers. receiver, rcvr 1. the agent that receives a packet across an interface regardless of whether it is the ultimate destination of the packet. 2. more narrowly, the circuitry required to convert incoming signals from the physical medium to more perceptible forms. request a packet, phase, or cycle used to initiate a transaction on a interface, or within a component. reserved the contents or undefined states or information are not defined at this time. using any reserved area is not permitted. rmw read-modify-write operation. row a group of dram chips that fill out the da ta bus width of the system and are accessed in parallel by each dram command. row address the row address is presented to the drams during an activate command, and indicates which page to open within the spec ified bank (the bank number is presented also). table 1-1. general terminology (sheet 5 of 7) terminology description
introduction 18 intel ? 5000x chipset memory controller hub (mch) datasheet scalable bus processor-to-mch interface. the compat ible mode of the scalab le bus is the p6 bus. the enhanced mode of the scalable bus is the p6 bus plus enhancements primarily consisting of source synchronous transfers for address and data, and fsb interrupt delivery. the intel ? pentium ? 4 processor implements a subset of the enhanced mode. sddc single device disable code; aka x4 or x8 chip-disable hamming co de to protect single dram device (x4 or x8 data width) failure. sdr single data rate sdram. sdram synchronous dynamic random access memory. sec/ded single-bit error correct / double-symbol error detect secondary pci the physical pci interface that is a su bset of the agp bus driven directly by the mch. it supports a subset of 32-bit, 66 mhz pci 2.0 compliant components, but only at 1.5 v (not 3.3 v or 5 v). serial presence detect (spd) a two-signal serial bus used to read and wr ite control registers in the sdrams via the smbus protocol. single-sided dimm terminology often used to describe a dimm that contains one dram row. usually one row fits on a single side of the dimm allowing the backside to be empty. simplex a connection or channel that allows da ta or messages to be transmitted in one direction only. smbus system management bus. mastered by a system management controller to read and write configuration registers. signaling and protocol are loosely based on i 2 c, limited to 100 khz. snooping a means of ensuring cache coherency by monitoring all coherent accesses on a common multi-drop bus to determine if an ac cess is to information resident within a cache. the intel 5000x chipset mch ensures coherency by initiating snoops on the processor busses with the address of any lin e that might appear in a cache on that bus. split lock sequence a sequence of transactions that oc curs when the target of a lock operation is split across a processor bus data alignment or cache line boundary, resulting in two read transactions and two write transactions to accomplish a read-modify-write operation. split transaction a transact ion that consists of distinct request and completion phases or packets that allow use of bus, or interconnect, by other transactions while the target is servicing the request. sstl stub-series terminated logic sstl_2 stub series terminated logic for 2.6 volts (ddr) symbol an expanded and encoded representation of a data byte in an encoded system (for example, the 10-bit value in a 8-bit/10-bit encoding scheme). this is the value that is transmitted over the physical medium. symbol time the amount of time required to transmit a symbol. system bus processor-to-intel 5000x chipset interface. the system bus in this document refers to operation at 266/533/1066 mhz (bus clock/address/data). the system bus is not compatible with the p6 system bus. target a device that responds to bus transact ions. the agent receiving a request packet is referred to as the target for that transaction. tenured transaction a transaction that holds the bus, or interconnect, until complete, effectively blocking all other transactions while the target is servicing the request. tid transaction identifier: a multi-bit field us ed to uniquely iden tify a transaction. commonly used to relate a completion with its originating request in a split transaction system. table 1-1. general terminology (sheet 6 of 7) terminology description
intel ? 5000x chipset memory controller hub (mch) datasheet 19 introduction 1.2 related documents 1.3 intel ? 5000x chipset overview figure 1-1 shows an example block diagram of an intel 5000x chipset-based platform. the intel 5000x chipset is designed for use in high performance workstations based on the dual-core intel xeon processor 5000 sequence. the intel 5000x chipset supports two processors on dual independent point to point system buses operating at 266 mhz (1066 mts) or two processors on dual independent point to point system buses operating at 333 mhz (1333 mts). the theo retical bandwidth of the two processor busses is 17 gb/s for dual-core intel xeon 5000 series and 21gb/s for dual-core intel xeon 5100 series. intel 5000x chipset features a high performa nce pci express* graphics port capable of through puts of 4 gb/s. this graphics port contains several architectural enhancements designed to optimize graphics performance in demanding video applications. one of the architectural enhancements in intel 5000x chip set is the inclusion of a snoop filter to eliminate snoop traffic to the graphics port. redu ction of this traffic results in significant performance increases in graphics intensive applications. the dual-core intel xeon 5000 series has a 2 mb l2 cache, a 266 mhz (1066 mts) system bus and dual-core intel xeon 5100 series has a 4mb shared l2 cache, a 333mhz (1333 mts) system bus. they are fabricated using a 65nm process in a 771-pin lga package. in a intel 5000x chipset-based platform, th e mch provides the processor interface, fully buffered dimm memory interfaces, pci express bus in terfaces, esi interface, and sm bus interfaces. transaction, txn an overloaded term that represents an operation between two or more agents that can be comprised of multiple phases, cycles, or packets. transmitter 1. the agent that sends a packet acro ss an interface regardless of whether it was the original generator of the packet. 2. more narrowly, the circuitry required to drive signals onto the physical medium. upstream see terminology entry of ?inbound (ib)/outbound (ob), aka upstream/downstream, northbound/southbound, upbound/downbound? document document number/ location dual-core intel ? xeon ? processor-based servers platform design guide http://developer.intel.com/design/ dual-core intel ? xeon ? processor 5000 sequence thermal/mechanical design guideline http://developer.intel.com/design/ intel ? 6402/6400 advanced memory buffe r component external design specification http://developer.intel.com/design/ intel ? 631xesb/632xesb i/o controller hub da tasheet http://developer .intel.com/design/ dual-core intel ? xeon ? processor 5000 sequence electrical, mechanical, and thermal specifications (emts). http://developer.intel.com/design intel ? 5000 series chipsets mch bios specif ication http://developer.intel.com/design jedec fb-dimm memory specification www.jedec.org pci local bus specificatio n, rev 2.3. www.pcisig.org pci express interface specific ation, rev 1.0a www.pcisig.org table 1-1. general terminology (sheet 7 of 7) terminology description
introduction 20 intel ? 5000x chipset memory controller hub (mch) datasheet the mch provides four channels of fully buffered dimm (fb-dimm) memory. each channel can support up to 4 dual ranked fb-dimm ddr2 dimms. fb-dimm memory channels are organized in to two branches for support of raid 1 (mirroring). the mch can support up to 16 dimms or a maximum memo ry size of 64 gb physical memory in non-mirrored mode and 32 gb physical memo ry in mirrored configuration. the read bandwidth for each fb-dimm channel is 4.25 gb/s for ddr2 533 fb-dimm memory which gives a total read bandwidth of 17gb/s for four fb-dimm channels. thus this provides 8.5 gb/s of write memory bandwith for four fb-dimm channels. the read bandwidth for each fb-dimm channel is 5.325 gb/s for ddr2 667fb-dimm memory which gives a total read bandwidth of 21.3 gb/s for four fb-dimm channels. thus this provides 10.7gb/s of write memory bandwith for four fb-dimm channels. the total bandwidth is based on read bandwidth theref ore the total bandwidth is 17 gb/s for 533 and 21.3 gb/s for 667. the intel 631xesb/632xesb i/o controller hub integrates an ultra ata 100 controller, six serial ata host controller ports, one ehci host controller, and four uhci host controllers supporting eight external usb 2.0 ports, lpc interface controller, flash bios interface controller, pci interface controller, azalia / ac?97 digital controller, integrated lan controller, an asf controller and a es i for communication with the mch. the intel 631xesb/632xesb i/o controller hub comp onent provides the data buffering and interface arbitration required to ensure that system interfaces operate efficiently and provide the bandwidth necessary to enable the system to obtain peak performance. the intel 631xesb/632xesb i/o controller hub elevates serial ata storage performance to the next level with intel ? raid. the acpi compliant intel 631xesb/632xesb i/o controller hub platform can support the full-on, stop grant, suspend to ram, suspend to disk, and soft-off power management states. through the use of th e integrated lan functions, the intel 631xesb/632xesb i/o controller hub also supports alert standard format for remote management.
intel ? 5000x chipset memory controller hub (mch) datasheet 21 introduction figure 1-1. intel ? 5000x chipset system block diagram p1 intel? 5000x chipset mch intel? 631xesb/ 632 xesb i/ o controller hub intel? 82563eb network connection ( dual port) phy f b d d r f b d d r f b d d r f b d d r f b d d r f b d d r f b d d r f b d d r f b d d r f b d d r f b d d r f b d d r pci- e x16 graphics port sm buses f b d d r f b d d r f b d d r f b d d r note: all pci- express bandwidth numbers are bi- directional 8 usb ports gpio azalia or ac?97 3 codec support 6 sata ports 1 pata port clock generator pci- e x 4 bus pci- x 133 bus pci 32/ 33 bus power management pci- e x 4 bus rj45 rj45 sio flash bios p2 channel 1 5.3 gb/s channel 2 gb / s channel 3 . 5.3 gb/ s channel 0 5.3gb/s 4 pci-e x4 4gb/s 1066/1333 mts system bus mts system bus pci- e x4 2 gb/s pci- e x4 2 gb/s esi 2 gb/s 5.3 note: fbd bandwidth numbers are for fbd 4.0ghz/667mhz. 1066/1333
introduction 22 intel ? 5000x chipset memory controller hub (mch) datasheet
intel ? 5000x chipset memory controller hub (mch) datasheet 23 signal description 2 signal description this section provides a detailed description of mch signals. the signals are arranged in functional groups according to their associat ed interface. the signals presented in this section may not be present in all intel 5000 series chipsets. to determine if a signal is in a particular version, consult chapter 8 . throughout this section the following conventions are used: the terms assertion and deassertion are to avoid confusion when working with a mix of active-high and active-low signals. the terms assert , or assertion , indicates that the signal is active, independent of whether the ac tive level is represented by a high or low voltage. the terms deassert , or deassertion , indicates that the signal is inactive. signal names may or may not have a ?#? ap pended to them. the ?#? symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. when ?#? is not present after the signal name, the signal is asserted when at the high voltage level. differential signal pairs adopt a ?{p/n}? suffix to indicate the ?positive? (p) or ?negative? (n) signal in the pair. if a ?#? is appended, it is appended to the positive and negative signals in a pair. typical frequencies of operation for the fastest operating modes are indicated. no frequency is specified for asynchronous or analog signals. some signals or groups of signals have multiple versions. these signal groups may represent distinct but similar ports or interfaces, or may represent identical copies of the signal used to reduce loading effects. curly-bracketed non-trailing numerical indices, for example, ?{x/y}?, represent replications of major buses. square-bracket ed numerical indices, for example, ?[n:m]? represent functionally similar but logically distinct bus signals; each signal provides an independent control, and may or may not be asserted at the same time as the other signals in the grouping. in contrast, trailin g curly-bracketed numerical indices, e.g., ?{x/y}? typically represent identical duplicates of a signal; such duplicates are provided for electrical reasons. the following notations are used to describe the signal type: i input pin o output pin i/o bi-directional input/output pin s/t/s sustained tri-state. this pin is driven to its inactive state prior to tri-stating. the signal description also includes the type of buffer used for the particular signal: agtl+ open drain agtl+ interface signal. re fer to the agtl+ i/o specification for complete details. the mch integrates agtl+ termination resistors, and supports vtt from 1.15 v to 1.55 v. lvttl low voltage ttl 3.3 v compatible signals sstl_2 stub series terminated logic 2.6 v compatible signals
signal description 24 intel ? 5000x chipset memory controller hub (mch) datasheet 2.6 vgpio 2.6 v buffers used for miscellaneous gpio signals cmos cmos buffers host interface signals that perform multiple transfers per clock cycle may be marked as either ?4x? (for signals that are ?quad-pump ed?) or 2x (for signals that are ?double- pumped?). note: processor address and data bus signals are logically inverted signals. in other words, the actual values are inverted of what ap pears on the processor bus. this must be taken into account and the addresses and data bus signals must be inverted inside the mch host bridge. all processor control signals follow normal convention. a 0 indicates an active level (low voltage) if the signal is followed by # symbol and a 1 indicates an active level (high voltage) if the signal has no # suffix. ta b l e 2 - 2 lists the reference terminology used for signal types. table 2-1. signal naming conventions convention expands to rr{0/1/2}xx expands to: rr0xx, rr1xx, and rr2xx. this denotes similar signals on replicated buses. rr[2:0] expands to: rr[2], rr[1], and rr[0]. this denotes a bus. rr{0/1/2} expands to: rr2, rr1, and rr0. this denotes electrical duplicates. rr# or rr[2:0]# denotes an active low signal or bus. table 2-2. buffer signal types buffer direction description iinput signal ooutput signal aanalog i/o bidirectional (input/output) signal
intel ? 5000x chipset memory controller hub (mch) datasheet 25 signal description 2.1 processor front side bus signals 2.1.1 processor front side bus 0 signal name type description fsb0a[35:3]# i/o processor 0 address bus: fsb0a[35:3]# connect to the processor address bus. during processor cycles, fsb0a[35:3]# are inputs. the mch drives fsb0a[35:3]# during snoop cycles on behalf of esi and agp/secondary pci initiators. fsb0a[35:3]# are transferred at 2x rate. note that the address is inverted on the processor bus. the mch drives the fsb0a7# signal, which is then sampled by the processor and the mch on the active-to-inactive transition of fsb0reset#. the minimum setup time for this signal is 4 fsb0clks. the minimum hold time is 2 clocks and the maximum hold time is 20 fsb0clks. fsb0ads# i/o processor 0 address strobe: the processor bus owner asserts fsb0ads# to indicate the first of two cycles of a request phase. the mch can assert this signal for snoop cycles and interrupt messages. fsb0adstb[1:0]# i/o processor 0 address strobe: fsb0adstb[1:0]# are source synchronous strobes used to transfer fsb0a[35: 3]# and fsb0req[4:0]# at the 2x transfer rate. strobeaddress bits fsb0adstb0#fsb0a[16:3]#, fsb0req[4:0]# fsb0adstb1#fsb0a[35:17]# fsb0ap[1:0]# i/o processor 0 address parity: fsb0ap[1:0]# provide parity protection on the address bus. fsb0binit# i/o processor 0 bus initialization: this signal causes a reset of the bus state machines. fsb0bnr# i/o processor 0 block next request: this signal is used to block the current request bus owner from issuing a new request. this signal is used to dynamically control the processor bus pipeline depth. fsb0bpm[5:4] i/o breakpoint /debug bus: these signals are breakpoint and performance monitor signals. these are output from the processor to indicate the status of breakpoints and programmable counters used for monitoring processor performance. fsb0bpri# o processor 0 priority agent bus request: the mch is the only priority agent on the processor bus. it asserts th is signal to obtain ownership of the address bus. this signal has priority over symmetric bus requests and cause the current symmetric owner to stop issuing new transactions unless the fsb0lock# signal was asserted. fsb0breq[1:0]# i/o processor 0 bus requests : the mch pulls the fsb0breq0# signal low during reset#. the signal is sampled by the processor on the active-to- inactive transition of fsb0reset#. the minimum setup time for this signal is 4 fsb0clks. the minimum hold time is 2 clocks and the maximum hold time is 20 fsb0clks. fsb0d[63:0]# i/o processor 0 data bus: these signals are connected to the processor data bus. data on fsb0d[63:0]# is transfer red at a 4x rate. note that the data signals may be inverted on the processor bus, depending on the p0dbi [3:0] signals. fsb0dbi[3:0]# i/o processor 0 dynamic bus inversion: these signals are driven along with the fsb0d[63:0]# signals. they indicate if the associated signals are inverted. fsb0dbi[3:0]# are asserted such that the number of data bits driven electrically low (low vofsb0lt age) within the corresponding 16-bit group never exceeds 8. fsb0dbi[x]#data bits fsb0dbi3#fsb0d[63:48]# fsb0dbi2#fsb0d[47:32]# fsb0dbi1#fsb0d[31:16]# fsb0dbi0#fsb0d[15:0]# fsb0dbsy# i/o processor 0 data bus busy: this signal is used by the data bus owner to hold the data bus for transfers requiring more than one cycle. fsb0defer# o processor 0 data bus defer: defer indicates that the mch will terminate the transaction currently being snooped with either a deferred response or with a retry response.
signal description 26 intel ? 5000x chipset memory controller hub (mch) datasheet fsb0dp[3:0]# i/o processor 0 data bus parity: fsb0dp[3:0]# provide parity protection on the data bus. fsb0drdy# i/o processor 0 data ready: this signal is asserted for each cycle that data is transferred. fsb0dstbp[3:0]# fsb0dstbn[3:0]# i/o processor 0 differential host data strobes: the differential source synchronous strobes used to transfer fsb0d[63:0]# and fsb0dbi[3:0]# at the 4x transfer rate. strobedata bits fsb0dstbp3#, fsb0dstbn3#fsb0d[63:48]#, fsb0dbi3# fsb0dstbp2#, fsb0dstbn2#fsb0d[47:32]#, fsb0dbi2# fsb0dstbp1#, fsb0dstbn1#fsb0d[31:16]#, fsb0dbi1# fsb0dstbp0#, fsb0dstbn0#fsb0d[15:0]#, fsb0dbi0# fsb0hit# i/o processor 0 cache hit: this signal indicates that a caching agent holds an unmodified version of the requested lin e. fsb0hit# is also driven in conjunction with fsb0hitm# by the target to extend the snoop window. fsb0hitm# i/o processor 0 cache hit modified: this signal indicates that a caching agent holds a modified version of the requested line and that this agent assumes responsibility for providing the line. fsb0 hitm# is also driven in conjunction with fsb0hit# to extend the snoop window. fsb0lock# i/o processor 0 lock: this signal indicates to the system that a transaction must occur atomically. this signal must connect the appropriate pins of all processor fsb agents. for a locked sequence of transactions, lock# is asserted from the beginning of the first transaction to the end of the last transaction. when the priority agent asserts bpri # to arbitrate for ownership of the processor fsb, it will wait until it ob serves lock# deasserted. this enables symmetric agents to retain ownership of the processor fsb throughout the bus locked operation and ensure the atomicity of lock. fsb0mcerr# i/o processor 0 machine check error: machine check error fsb0req[4:0]# i/o processor bus 0 request command: these signals define the attributes of the request. fsb0req[4:0]# are transf erred at 2x rate. they are asserted by the requesting agent during both halv es of request phase. in the first half the signals define the transaction type to a level of detail that is sufficient to begin a snoop request. in the second half the signals carry additional information to define the complete transaction type. fsb0reset# o processor 0 reset: the fsb0reset# pin is an output from the mch. the mch asserts fsb0reset# while rstin# (pcirst# from intel? 631xesb/ 632xesb i/o controller hub) is asserted and for approximately 1 ms after rstin# is deasserted. the fsb0reset# allows the processors to begin execution in a known state. fsb0rs[2:0]# o processor 0 response status signals: these signals indicate the type of response according to the following: encoding response type 000 idle state 001 retry response 010 deferred response 011 reserved (not driven by mch) 100 hard failure (not driven by mch) 101 no data response 110 implicit writeback 111 normal data response fsb0rsp# o processor 0 response status parity: fsb0trdy# o processor bus 0 target ready: this signal indicates that the target of the processor transaction is able to enter the data transfer phase. fsb0vref analog processor 0 voltage reference: processor 0 voltage reference. signal name type description
intel ? 5000x chipset memory controller hub (mch) datasheet 27 signal description 2.1.2 processor front side bus 1 signal name type description fsb1a[35:3]# i/o processor 1 address bus: fsb1a[35:3]# connect to the processor address bus. during processor cycles, fsb1a[35:3]# are inputs. the mch drives fsb1a[35:3]# during snoop cycles on behalf of esi and agp/secondary pci initiators. fsb1a[35:3]# are transferred at 2x rate. note that the address is inverted on the processor bus. note: the mch drives the fsb1a7# signal , which is then sampled by the processor and the mch on the active-to-inactive transition of fsb1reset#. the minimum setup time for this signal is 4 fsb0clks. the minimum hold time is 2 clocks and the maximum hold time is 20 fsb1clks. fsb1ads# i/o processor 1 address strobe: the processor bus owner asserts fsb1ads# to indicate the first of two cycles of a request phase. the mch can assert this signal for snoop cycles and interrupt messages. fsb1adstb[1:0]# i/o processor 1 address strobe: fsb1adstb[1:0]# are source synchronous strobes used to transfer fsb1a[35: 3]# and fsb1req[4:0]# at the 2x transfer rate. strobeaddress bits fsb1adstb0#fsb1a[16:3]#, fsb1req[4:0]# fsb1adstb1#fsb1a[35:17]# fsb1ap[1:0]# i/o processor 1 address parity: fsb0ap[1:0]# provide parity protection on the address bus fsb1binit# i/o processor 1 bus initialization: this signal causes a reset of the bus state machines. fsb1bnr# i/o processor 1 block next request: this signal is used to block the current request bus owner from issuing a new request. this signal is used to dynamically control the processor bus pipeline depth. fsb1bpm[5:4] i/o breakpoint /debug bus: these signals are breakpoint and performance monitor signals. these are output from the processor to indicate the status of breakpoints and programmable counters used for monitoring processor performance. fsb1bpri# o processor 1 priority agent bus request: the mch is the only priority agent on the processor bus. it asserts th is signal to obtain ownership of the address bus. this signal has priority over symmetric bus requests and cause the current symmetric owner to stop issuing new transactions unless the fsb1lock# signal was asserted. fsb1breq[1:0]# i/o processor 1 bus requests: the mch pulls the fsb1breq1# & fsb1breq0# signals low during reset#. the signal is sampled by the processor on the active-to-inactive transition of fsb1reset#. the minimum setup time for this signal is 4 fsb1cl ks. the minimum hold time is 2 clocks and the maximum hold time is 20 fsb1clks. fsb1d[63:0]# i/o processor 1 data bus: these signals are connected to the processor data bus. data on fsb1d[63:0]# is transfer red at a 4x rate. note that the data signals may be inverted on the processor bus, depending on the fsb1dbi[3:0] signals. fsb1dbi[3:0]# i/o processor 1 dynamic bus inversion: these signals are driven along with the fsb1d[63:0]# signals. they indicate if the associated signals are inverted. fsb1dbi[3:0]# are asserted such that the number of data bits driven electrically low (low voltage) within the corresponding 16-bit group never exceeds 8. fsb1dbi[x]#data bits fsb1dbi3#fsb1d[63:48]# fsb1dbi2#fsb1d[47:32]# fsb1dbi1#fsb1d[31:16]# fsb1dbi0#fsb1d[15:0]# fsb1dbsy# i/o processor 1 data bus busy: this signal is used by the data bus owner to hold the data bus for transfers requiring more than one cycle. fsb1defer# o processor 1 data bus defer: defer indicates that the mch will terminate the transaction currently being snooped with either a deferred response or with a retry response.
signal description 28 intel ? 5000x chipset memory controller hub (mch) datasheet fsb1dp[3:0]# i/o processor 1 data bus parity: fsb1dp[3:0]# provide parity protection on the data bus. fsb1drdy# i/o processor 1 data ready: this signal is asserted for each cycle that data is transferred. fsb1dstbp[3:0]# fsb1dstbn[3:0]# i/o processor 1 differential host data strobes: the differential source synchronous strobes used to transfer fsb1d[63:0]# and fsb1dbi[3:0]# at the 4x transfer rate. strobedata bits fsb1dstbp3#, fsb10dstbn3# fsb1d[63:48]#, fsb1dbi3# fsb1dstbp2#, fsb1dstbn2#fsb1d[47:32]#, fsb1dbi2# fsb1dstbp1#, fsb1dstbn1#fsb1d[31:16]#, fsb1dbi1# fsb1dstbp0#, fsb1dstbn0#fsb1d[15:0]#, fsb1dbi0# fsb1hit# i/o processor 1 cache hit: this signal indicates that a caching agent holds an unmodified version of the requested lin e. fsb1hit# is also driven in conjunction with fsb1hitm# by the target to extend the snoop window. fsb1hitm# i/o processor 1 cache hit modified: this signal indicates that a caching agent holds a modified version of the requested line and that this agent assumes responsibility for providing the line. fsb1 hitm# is also driven in conjunction with fsb1hit# to extend the snoop window. fsb1lock# i/o processor 1 lock: this signal indicates to the system that a transaction must occur atomically. this signal must connect the appropriate pins of all processor fsb agents. for a locked sequence of transactions, lock# is asserted from the beginning of the first transaction to the end of the last transaction. when the priority agent asserts bpri # to arbitrate for ownership of the processor fsb, it will wait until it ob serves lock# deasserted. this enables symmetric agents to retain ownership of the processor fsb throughout the bus locked operation and ensure the atomicity of lock. fsb1mcerr# i/o processor 1 machine check error: machine check error fsb1req[4:0]# i/o processor bus 1 request command: these signals define the attributes of the request. fsb1req[4:0]# are transf erred at 2x rate. they are asserted by the requesting agent during both halv es of request phase. in the first half the signals define the transaction type to a level of detail that is sufficient to begin a snoop request. in the second half the signals carry additional information to define the complete transaction type. fsb1reset# o processor 1 reset: the fsb1reset# pin is an output from the mch. the mch asserts fsb1reset# while rstin# (pcirst# from intel? 631xesb/ 632xesb i/o controller hub) is asserted and for approximately 1 ms after rstin# is deasserted. the fsb1reset# allows the processors to begin execution in a known state. fsb1rs[2:0]# o processor 1 response status signals: these signals indicates type of response according to the following: encodingresponse type 000 idle state 001 retry response 010 deferred response 011 reserved (not driven by mch) 100 hard failure (not driven by mch) 101 no data response 110 implicit writeback 111 normal data response fsb1rsp# o processor 1 response status parity: fsb1trdy# o processor bus 1 target ready: this signal indicates that the target of the processor transaction is able to enter the data transfer phase. fsb1vref analog processor 1 voltage reference: processor 1 voltage reference. signal name type description
intel ? 5000x chipset memory controller hub (mch) datasheet 29 signal description 2.2 fully buffered dimm memory channels the following reference and compensation signals are common to all fully buffered dimm (fb-dimm) channels. 2.2.1 fb-dimm branch 0 fb-dimm branch 0 contains fb-dimm channels 0 and 1. the following signals are common to both fb-dimm channels. 2.2.1.1 fb-dimm channel 0 2.2.1.2 fb-dimm channel 1 signal name type description fbdbgbiasext analog fb-dimm bypass bias input for band gap circuit: fbdicompbias analog fb-dimm transmitter swing bias: fbdresin analog fb-dimm on-die impedance compensation: signal name type description fbd01clkn analog fb-dimm clock negative: core clock negative phase fbd01clkp analog fb-dimm clock positive: core clock positive phase fbd01vcca analog fb-dimm vcc: analog voltage for the pll fbd01vssa analog fb-dimm vss: analog voltage for pll signal name type description fbd0nbin[13:0] i fb-dimm channel 0 northbound input data negative phase: note: fbd0nbin[13] is not an active signal carrying signal but must be connected to properly terminate the fb dimm component. fbd0nbip[13:0] i fb-dimm channel 0 northbound input data positive phase: note: fbd0nbip[13] is not an active signal carrying signal but must be connected to properly terminate the fb dimm component. fbd0sbon[9:0] o fb-dimm channel 0 southbound output negative phase: fbd0sbop[9:0] o fb-dimm channel 0 southbound output positive phase: signal name type description fbd1nbin[13:0] i fb-dimm channel 1 northbound input data negative phase: note: fbd1nbin[13] is not an active signal carrying signal but must be connected to properly terminate the fb dimm component. fbd1nbip[13:0] i fb-dimm channel 1 northbound input data positive phase: note: fbd1nbip[13] is not an active signal carrying signal but must be connected to properly terminate the fb dimm component. fbd1sbon[9:0] o fb-dimm channel 1 southbound output negative phase: fbd1sbop[9:0] o fb-dimm channel 1 southbound output positive phase:
signal description 30 intel ? 5000x chipset memory controller hub (mch) datasheet 2.2.2 fb-dimm branch 1 fb-dimm branch 1 contains fb-dimm channe ls 2 and 3. the following signals are common to both fb-dimm channels. 2.2.2.1 fb-dimm channel 2 2.2.2.2 fb-dimm channel 3 2.3 pci express* signal list 2.3.1 pci express* common signals signal name type description fbd23clkn analog fb-dimm clock negative: core clock negative phase fbd23clkp analog fb-dimm clock positive: core clock positive phase fbd23vcca analog fb-dimm vcc: analog voltage for the pll fbd23vssa analog fb-dimm vss: analog voltage for pll signal name type description fbd2nbin[13:0] i fb-dimm channel 2 northbound input data negative phase: note: fbd2nbin[13] is not an active sign al carrying signal but must be connected to properly terminate the fb dimm component. fbd2nbip[13:0] i fb-dimm channel 2 northbound input data positive phase: note: fbd2nbip[13] is not an active signal carrying signal but must be connected to properly terminate the fb dimm component. fbd2sbon[9:0] o fb-dimm channel 2 southbound output negative phase: fbd2sbop[9:0] o fb-dimm channel 2 southbound output positive phase: signal name type description fbd3nbin[13:0] i fb-dimm channel 3 northbound input data negative phase: note: fbd3nbin[13] is not an active sign al carrying signal but must be connected to properly terminate the fb dimm component. fbd3nbip[13:0] i fb-dimm channel 3 northbound input data positive phase: note: fbd3nbip[13] is not an active signal carrying signal but must be connected to properly terminate the fb dimm component. fbd3sbon[9:0] o fb-dimm channel 3 southbound output negative phase: fbd3sbop[9:0] o fb-dimm channel 3 southbound output positive phase: signal name type description peclkn analog pci express* common clock negative phase: peclkp analog pci express common clock positive phase: peicompi analog pci express impedance compensation: peicompo analog pci express impedance compensation: pevcca analog pci express vcc: analog voltage for the pci express pll: pevccbg analog pci express band gap vcc: band gap voltage pevssa analog pci express vss: analog voltage for pci express pll: pevssbg analog pci express band gap vss: band gap voltage pewidth[3:0] power/other pci express port width strapping pins :
intel ? 5000x chipset memory controller hub (mch) datasheet 31 signal description 2.3.2 pci express port 0, ente rprise south bridge interface (esi) pci express port 0 is a x4 port dedicated to providing the esi link between the intel 5000x chipset mch and the intel 631xesb/632xesb i/o controller hub. 2.3.3 pci express port 2 pci express port 2 is a x4 port. pci express port 2 is combinable with pci express port 3 to form a single pci express x8 port. normally port 2 and port 3 are used to increase the bandwidth between the intel 5000x ch ipset mch and the intel 631xesb/632xesb i/o controller hub. 2.3.4 pci express port 3 pci express port 3 is combinable with pci ex press port 2 to form a single pci express x8 port. normally port 2 and port 3 are used to increase the bandwidth between the intel 5000x chipset mch and the intel 631xesb/632xesb i/o controller hub. signal name type description reference pe0rp[3:0] i pci express port 0 (esi) positive phase inbound: (receive) signals pe0rn[3:0] i pci express port 0 (esi) negative phase inbound: (receive) signals pe0tp[3:0] o pci express port 0 (esi) positive phase outbound: (transmit) signals pe0tn[3:0] o pci express port 0 (esi) negative phase outbound: (transmit) signals signal name type description pe2rp[3:0] i pci express port 2 positive phase inbound: (receive) signals pe2rn[3:0] i pci express port 2 negative phase inbound: (receive) signals pe2tp[3:0] o pci express port 2 positive phase outbound: (transmit) signals pe2tn[3:0] o pci express port 2 negative phase outbound: (transmit) signals signal name type description pe3rp[3:0] i pci express port 3 positive phase: inbound (receive) signals pe3rn[3:0] i pci express port 3 negative phase: inbound (receive) signals pe3tp[3:0] o pci express port 3 positive phase: outbound (transmit) signals pe3tn[3:0] o pci express port 3 negative phase: outbound (transmit) signals
signal description 32 intel ? 5000x chipset memory controller hub (mch) datasheet 2.3.5 pci express* graphics port in the intel 5000x chipset mch pci express ports 4, 5, 6, and 7 are combined to form a single high performance x16 graphics port. signal name type description pe4rp[3:0] i pci express* graphics port first x4, positive phase inbound (receive) signals: pe4rn[3:0] i pci express graphics port first x4, negative phase inbound (receive) signals: pe4tp[3:0] o pci express graphics port first x4, positive phase outbound (transmit) signals: pe4tn[3:0] o pci express graphics port first x4 , negative phase outbound (transmit) signals: pe5rp[3:0] i pci express graphics port second x4, positive phase inbound (receive) signals: pe5rn[3:0] i pci express graphics port second x4, negative phase inbound (receive) signals: pe5tp[3:0] o pci express graphics port second x4, positive phase outbound (transmit) signals: pe5tn[3:0] o pci express graphics port second x4, negative phase outbound (transmit) signals: pe6rp[3:0] i pci express graphics port third x4, positive phase inbound (receive) signals: pe6rn[3:0] i pci express graphics port third x4, negative phase inbound (receive) signals: pe6tp[3:0] o pci express graphics port third x4, positive phase outbound (transmit) signals: pe6tn[3:0] o pci express graphics port third x4, negative phase outbound (transmit) signals: pe7rp[3:0] i pci express graphics port fourth x4, positive phase inbound (receive) signals: pe7rn[3:0] i pci express graphics port fourth x4, negative phase inbound (receive) signals: pe7tp[3:0] o pci express graphics port fourth x4, positive phase outbound (transmit) signals: pe7tn[3:0] o pci express graphics port fourth x4, negative phase outbound (transmit) signals:
intel ? 5000x chipset memory controller hub (mch) datasheet 33 signal description 2.4 system management bus interfaces there are seven sm bus interfaces dedicated to specific functions. these functions are: ? system management ? four buses dedicated to fb-dimm serial presents detect, one for each channel ? pci hot-plug 2.5 xd port signal list 2.6 jtag bus signal list signal name type description cfgsmbclk i/o slave smb clock: system management bus clock cfgsmbdata i/o slave smb data: smb address/data gpiosmbclk i/o pci smb clock: pci hot-plug master vpi, system management bus clock gpiosmbdata i/o pci smb data: pci hot-plug master vpi, smb address/data spd0smbclk i/o fb-dimm channel 0 smb clock: fb-dimm memory serial presents detect 0, system management bus clock spd0smbdata i/o fb-dimm channel 0 smb data: fb-dimm memory serial presents detect 0, smb address/data spd1smbclk i/o fb-dimm channel 1 smb clock: fb-dimm memory serial presents detect 1, system management bus clock spd1smbdata i/o fb-dimm channel 1 smb data: fb-dimm memory serial presents detect 1, smb address/data spd2smbclk i/o fb-dimm channel 2 smb clock: fb-dimm memory serial presents detect 2, system management bus clock spd2smbdata i/o fb-dimm channel 2 smb data: fb-dimm memory serial presents detect 2, smb address/data spd3smbclk i/o fb-dimm channel 3 smb clock: fb-dimm memory serial presents detect 3, system management bus clock spd3smbdata i/o fb-dimm channel 3 smb data: fb-dimm memory serial presents detect 3, smb address/data signal name type description xdpcomcres analog xdp bus compensation: xdpd[15:0]# i/o data bus: . xdpstbn# xdpstbp# i/o data bus strobe negative and positive phases: xdpodtcres analog xdp bus compensation: xdprdy# i/o data bus ready: xdpslwcres analog xdp bus slew rate compensation: . signal name type description tck i clock: clock pin of the jtag. tdi i data input: serial chain input of the jtag. tdo o data output: serial chain output of the jtag. tms i state machine: jtag state machine control trst# i reset: asynchronous reset of the jtag.
signal description 34 intel ? 5000x chipset memory controller hub (mch) datasheet 2.7 clocks, reset and miscellaneous 2.8 power and ground signals 2.9 mch sequencing requirements power plane and sequencing requirements: ? clock valid timing: signal name type description coreclkn analog differential processor core clock negative phase: these pins receive a low-voltage differential host clock from the external clock synthesizer. this clock is used by all of the mch logi c that is in the host clock domain. coreclkp analog differential processor core clock positive phase: these pins receive a low-voltage differential host clock from the external clock synthesizer. this clock is used by all of the mch logi c that is in the host clock domain. corevcca analog core vcc: analog voltage for the pll corevssa analog core vss: analog voltage for pll err[2:0]# o error output: error output signal: err[0] = correctable and recoverable error from the memory subsystem err[1] = uncorrectable error from the intel 5000x chipset mch err[2] = fatal error from the intel 5000x chipset mch fsbcres analog processor bus compensation : odtcres analog processor bus compensation: fsbslwcres analog processor bus slew rate compensation: fsbslwctrl power/other processor bus slew rate control: fsbvcca analog fsb vcc: analog voltage for the fb-dimm channel pll pwrgood i power ok: when asserted, this signal indi cates that all power supplies are in specification. psel[2:0] i processor speed select: reseti# i mch reset: this is the hard reset rsvd no connect reserved pin: tdioanode analog thermal diode anode: this is the anode of the thermal diode tdiocathode analog thermal diode cathode: this is the cathode of the thermal diode testhi power 1.5 volt pullup: testhi_v3ref power/other 3.3 volt pullup: vssquiet analog quiet vss: quiet vss for oddd vsssen analog quiet vss: quiet vss for thermal sensor vccsen analog quiet vcc: quiet vcc for thermal sensor signal name description v3ref smb vcc: common 3.3 for smb buses vcc vcc supply: this is the 1.5 v core voltage. vccsf vcc snoop filter supply: this is the 1.5 v core voltage on a separate plane for the snoop filter. vss ground return: common return for power supplies vtt vtt supply: vtt is a 1.2 v fsb supply vccfbd vcc for system memory: vccfbd is 1.8 v for ddr2 power. vccpe vcc for pci express ports.
intel ? 5000x chipset memory controller hub (mch) datasheet 35 signal description ? busclk must be valid at least 2ms prior to rising edge of pwrgood. figure 2-1. intel 5000x chipse t clock and reset requirements power rails pwrgood reset# busclk 1ms 2ms ~100ms
signal description 36 intel ? 5000x chipset memory controller hub (mch) datasheet 2.10 reset requirements 2.10.1 timing diagrams 2.10.1.1 power-up the power-up sequence is illustrated in figure 2-2 . 2.10.1.2 power good the pwrgood reset sequence is illustrated in figure 2-3 . 2.10.1.3 hard reset the hard reset sequence is illustrated in figure 2-4 . figure 2-2. power-up initialization init full operation pwrgood events busclk reseti# fbd processor reset# pll's straps sampled fuses downloaded synchronized reseti# array init done level t9 t13 poc t12 t7 t14 dmi handshake done t15 pci-express pci-express compatibility reset internal power detect non-fbd analog compensation completed t1 power rails t11 t10 straps inactive t8 t17 figure 2-3. pwrgood initialization init full operation pwrgood events busclk reseti# fbd processor reset# pll's straps sampled fuses downloaded synchronized reseti# array init done level t9 t13 poc t12 t7 t14 dmi handshake done t15 sticky bits pci- express pci-express compatibility reset t11 t3 t10 straps active t2 straps inactive t8 t17
intel ? 5000x chipset memory controller hub (mch) datasheet 37 signal description 2.10.1.4 reseti# retriggering limitations figure 2-5 shows the timing for a reseti# retrigger. figure 2-4. hard reset initialization init full operation events busclk reseti# fbd processor reset# pll's synchronized reseti# array init done level t13 poc t12 t14 dmi handshake done t15 pci- express pci-express compatibility reset t4 sticky bit enable syre.savcfg initin# t11 t10 ichrst# t6 t9 t17 figure 2-5. reseti# retriggering limitations reseti# incomplete initialization complete initialization t 16 t 5 t 9
signal description 38 intel ? 5000x chipset memory controller hub (mch) datasheet 2.10.2 reset timing requirements ta b l e 2 - 3 specifies the timings drawn in figure 2-2 , figure 2-3 , figure 2-4 , and figure 2-5 . nominal clock frequencies are described. specifications still hold for derated clock frequencies. table 2-3. power up and hard reset timings timing description min max comments t1 power and master clocks stable to pwrgood signal assertion 2ms 3gio pll specification t2 pwrgood de-assertion to straps active 40ns t3 pwrgood de-assertion 80ns minimum pwrgood de-assertion time while power and platform clocks are stable. t4 poc after reset# assertion delay 1 busclk t5 platform reset de-assertion to platform reset assertion 50 busclk?s minimum re-trigger time on reseti# de-assertion. t7 pwrgood assertion to poc active 2 busclk?s poc turn-on delay after strap disable t8 pwrgood assertion to straps inactive 12ns 18ns strap hold time t9 reseti# signal assertion during pwrgood / pwrok signal assertion 1ms this delay can be provided by the ich6 or by system logic t10 reset# assertion during processor pwrgood assertion 1ms 10ms processor emts specification. t11 reseti# signal de-assertion to processor reset# signal de-assertion 480us 1 notes: 1. in the intel ? 5000p chipset b0 rtl, the t11 duration is implemented through a counter with max value of 162,000 core clocks. for 333 mhz, this gives a period of 486 us for the po c setup time while @266 mhz, the period is 607.5 us. note : this is a special dual-core intel xeon 5100 series requirement to have a longer poc assertion setup time on the fsb and the intel? 5000p chipset has added a fix in b0 rtl to increase this time period from 160us to 480us. t12 reseti# signal de-assertion to completion of pci-express initialization sequence 1,250,000 peclk?s pci-express clock is 100mhz t13 array initialization duration 200 cycles t14 poc hold time after reset# de-assertion 2 busclk?s 19 busclk?s processor emts specification t15 initiation of dmi reset sequence to processor reset# signal de-assertion 10,000 peclk?s + t17 ich6 specification t16 reseti# re-trigger delay t5 + t9 t17 cpu_reset_done capture timer 2,000 busclk?s
intel ? 5000x chipset memory controller hub (mch) datasheet 39 signal description ta b l e 2 - 4 summarizes the product name initialization timings. 2.10.3 miscellaneous requir ements and limitations ? power rails and stable busclk, fbd{0/1}clk, and peclk master clocks remain within specifications through all but power-up reset. ? frequencies (for example, 266 mhz) descr ibed in this chapter are nominal. the intel ? 5000p chipset mch reset sequences must work for the frequency of operation range specified in the clocking chapter. ? hard reset can be initiated by code running on a processor, jtag, smbus, or pci agents. ? hard reset is not guaranteed to correct all illegal configurations or malfunctions. software can configure sticky bits in the intel 5000p chipset mch to disable interfaces that will not be accessible after hard reset. signaling errors or protocol violations prior to reset (from processor bus, fb-dimm, or pci express) may hang interfaces that are not cleared by hard reset. ? system activity is initiated by a request from a processor bus. no i/o devices will initiate requests until configured by a processor to do so. ? the fb-dimm channels will be enabled for packet levelization (intel 5000p mch.fbdst.state=?ready? or ?recoveryready ? state) upon completion of a hard reset. software should inspect the intel 5000p chipset mch.fbdst.state configuration bits to determine wh ich fb-dimm channels are available. ? the default values of the poc configuration register bits do not require any processor request signals to be asserted when pwrgood is first asserted. software sets these configuration registers to define these values, then initiates a hard reset that causes them to be driven during processor reset# signal assertion. ? cleanly aborting an in-progress spd co mmand during a pwrgood deassertion is problematic. no guarantee can be issued as to the final state of the eeprom in this situation. the intel? 5000p mch cannot meet the spd data t su,sto timing specification. since the intel? 5000p mch fl oats the data output into a pull-up on the platform, a read will not degrade to a write. however, if the pwrgood deassertion occurs after the eeprom has received the write bit, the data will be corrupted. the platform pull-up must be st rong enough to complete a low-to-high transition on the clock signal within t r = 1 microsecond (atmel at24c01 timing specification) after deassertion of pwrgood to prevent clock glitches. within these constraints, an in-progress write address will not be corrupted. table 2-4. critical intel? 50 00p initialization timings sequence started by maximum length covered by timing parameter intel ? 5000p chipset core, fsb, fb-dimm pll lock stable power and master clock 666,667 333 mhz cycles t 1 intel? 5000p mch pci express pll lock stable power and master clock 200,000 100 mhz cycles array initialization synchronized reseti# deassertion 200 cycles t 17 fuse download pwrgood assertion 333,333 333 mhz cycles t 9
signal description 40 intel ? 5000x chipset memory controller hub (mch) datasheet 2.11 intel ? 5000p chipset platform signal routing topology diagrams figure 2-6. simplest power good distribution figure 2-7. basic syst em reset distribution figure 2-8. basic init# distribution processors intel? 631xesb/ 632xesb i/o controller hub power good logic pwrgood pwrgood sys_ reset other resets intel? 5000p chipset ichrst# intel? 5000p chipset reseti# reset#'s processor reset# processor reset# intel pltrst# intel? 631x esb/ 632xesb i/o controller hub processor init# processor init#
intel ? 5000x chipset memory controller hub (mch) datasheet 41 signal description 2.11.1 intel ? 5000p customer reference platfo rm (srp) reset topology typical platform level reset implementation is described in the dual-core intel ? xeon ? processor 5000 series (1066 mhz) and intel ? 5000 sequence chipsets platform design guide (pdg). 2.12 signals used as straps 2.12.1 functional straps the pewidth signals are used to determin e the widths of the 7 pci express ports. signal name type description pewidth[3:0] power/ other pci express port width strapping pins :
signal description 42 intel ? 5000x chipset memory controller hub (mch) datasheet
intel ? 5000x chipset memory controller hub (mch) datasheet 43 register description 3 register description the intel 5000x chipset mch contains three sets of software accessible registers, accessed via the host processor i/o address space: ? control registers i/o mapped into the processor i/o space that controls access to pci and agp configuration spaces. ? internal configuration registers residing within the mch are partitioned into logical device register sets (?logical? since they re side within a single physical device). the first register set is dedicated to mch f unctionality (controls pci bus 0, that is, dram configuration, other chipset operat ing parameters, and optional features). the second register block is dedicated to host-agp bridge functions (controls agp interface configurations and operating parameters). the third register set is dedicated to esi control. the mch supports pci configuration space accesses using the mechanism denoted as configuration mechanism 1 in the pci specification as defined in the pci local bus specification, revision 2.3. all the registers are organized by bus, device, function, and so forth, as defined in the pci express base specification , revision 1.0a. the mch supports registers in pci express extended space. all mch registers in the intel 5000x chipset appear on pci bus #0. in addition, the mch registers can be accessed by a memory mapped register access mechanism (as mmio), a pci configuration access mechanism (only pci space registers), and register access mechanisms through jtag and smbus. the memory mapped access mechanism is further broken down into different ranges. the internal registers of this chip set can be accessed in 8-bit, 16-bit, or 32-bit quantities, with the exception of cfgadr which can only be accessed as a 32-bit. all multi-byte numeric fields use ?little-endian? ordering (that is, lower addresses contain the least significant parts of the field). in addition, the mch can forward accesses to all pci/pci express configuration registers south of the mch through the same mechanisms. 3.1 register terminology registers and register bits are assigned one or more of the following attributes. these attributes define the behavior of register and the bit(s) that are contained with in. all bits are set to default values by hard reset. sticky bits retain their states between hard resets. i term description ro read only . if a register bit is read only, the hardware sets its state. the bit may be read by software. writes to this bit have no effect. wo write only. the register bit is not implemented as a bit. the write causes some hardware event to take place. rw read/write . a register bit with this attribute can be read and written by software. rc read clear: the bit or bits can be read by software, but the act of reading causes the value to be cleared. rcw read clear/write: a register bit with this attribute, will get cleared after the read. the register bit can be written.
register description 44 intel ? 5000x chipset memory controller hub (mch) datasheet 3.2 platform configuration structure in some previous chipsets, the mch and the south bridge were physically connected by pci bus 0. from a configuration standpoint, both components appeared to be on pci bus 0 which was also the system?s primary pci expansion bus. the mch contained two pci devices while the south bridge was considered one pci device with multiple functions. in the intel 5000x chipset-based platform, th e configuration structure is significantly different. the mch and the intel 631xesb/ 632xesb i/o controller hub are physically connected by the esi interface; thus, from a configuration standpoint, the esi interface is logically pci bus 0. as a result, all de vices internal to the mch and intel 631xesb/ 632xesb i/o controller hub appear to be on pci bus 0. the system?s primary pci rwc read/write clear . a register bit with this attribute, can be read or cleared by software. in order to clear this bit, a one must be wr itten to it. writing a zero will have no effect. rws read/write/set: a register bit can be either read or set by software. in order to set this bit, a one must be written to it. writing a zero to this bit has no effect. hardware will clear this bit. rwl read/write/lock . a register bit with this attribute can be read or written by software. hardware or a configuration bit can lock bit and prevent it from updated. rwo read/write once. a register bit with this attribute can be written to only once after power up. after the first write, the bit becomes read only. this attribute is applied on a bit by bit basis. for example, if the rwo attribute is applied to a 2 bit field, and only one bit is written, then the written bit cannot be rewritten (unless reset). the unwritten bit, of the field, may still be written once . this is special case of rwl. rrw read/restricted write. this bit can be read and written by software. however, only supported values will be wri tten. writes of non supporte d values will have no effect. l lock. a register bit with this attribute beco mes read only after a lock bit is set. rv reserved bit. this bit is reserved for future expansion and must not be written. the pci local bus specification, revision 2.2 requires that reserved bits must be preserved. any software that modifies a register that contai ns a reserved bit is responsible for reading the register, modifying the desired bits, and writing back the result. reserved bits some of the mch registers described in this section contain reserved bits. these bits are labeled ?reserved?. software must deal correctly with fields that are reserved. on reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. on writes, software must ensure that the values of reserved bit positions are preserved. that is, the values of reserved bit positions must first be read, merged with the new values fo r other bit positions and then written back. note that software does not need to pe rform a read-merge-write operation for the configuration address (config_address) register. reserved registers in addition to reserved bits within a regist er, the mch contains address locations in the configuration space of the host-esi bridge entity that are marked either ?reserved? or ?intel reserved?. the mch responds to accesses to ?reserved? address locations by completing the host cycle. when a ?reserved? register location is read, a zero value is returned. (?reserved? registers can be 8, 16, or 32 bits in size). writes to ?reserved? registers have no effect on the mch. registers that are marked as ?intel reserved? must not be modified by system software. writes to ?intel reserved? registers may cause system failure. reads to ?intel reserved? registers may return a non-zero value. default value upon a reset upon a reset, the mch sets all of its intern al configuration registers to predetermined default states. some register values at re set are determined by external strapping options. the default state represents the minimum functionality feature set required to successfully bring up the system. hence, it does not represent the optimal system configuration. it is the respon sibility of the system initializa tion software (usually bios) to properly determine the dram configur ations, operating parameters and optional system features that are applicable, and to program the mch registers accordingly. ?st? appended to the end of a bit name the bit is ?sticky? or unchanged by a hard reset. these bits can only be cleared by a pwrgood reset. term description
intel ? 5000x chipset memory controller hub (mch) datasheet 45 register description expansion bus is physically attached to th e intel 631xesb/632xesb i/o controller hub and, from a configuration perspective, appe ars to be a hierarchical pci bus behind a pci-to-pci bridge; therefore, it has a programmable pci bus number. the mch contains 14 pci devices within a single physical component. the configuration registers for these devices are mapped as devices residing on pci bus 0. ? device 0: esi bridge/pci express port 0. logically, this appears as a pci device that resides on pci bus 0. physically devi ce 0, function 0 contains the pci express configuration registers for the esi port, and other mch specific registers. ? device 2: pci express 2. logically this appears as a pci device residing on bus 0. device 2, function 0 is routed to the pci express configuration registers for pci express port 2. when pci express ports 2 and 3 are combined into a single x8 port, controlled by port 2 registers, device 3, function 0 (port 3) configuration registers are inactive. pci express port 2 resides at did of 25e2h(x4) or 25f7h(x8). ? device 3: pci express 3. logically this appears as a pci device that resides on bus 0. device 3, function 0 contains the pc i express configuration registers for pci express port 3. when pci express ports 2 and 3 are combined into a single x8 port, controlled by port 2 registers, these configuration registers are inactive. pci express port 3 resides at did of 25e3h. ? device 4: pci express 4. logically this appears as a pci device that resides on bus 0. device 4, function 0 contains the pc i express configuration registers for pci express port 4. when pci express ports 4, 5, 6, and 7 are combined into a single x16 graphics port, device 4, function 0 contains the configuration registers and device 5, function 0 (port 5), device 6, f unction 0 (port 6), and device 7, function 0 (port 7), configuration registers are inactive. pci express port 4 resides at did of 25e4h(x4) or 25f8h(x8) or 25fah(x16). ? device 5: pci express 5. logically this appears as a pci device that resides on bus 0. device 5, function 0 contains the pc i express configuration registers for pci express port 5. when pci express ports 4, 5, 6 and 7 are combined into a single x16 graphics port device 4, function 0 co ntains the configuration registers, and these configuration registers are inactive. pci express port 5 resides at did of 25e5h. ? device 6: pci express 6. logically this appears as a pci device residing on bus 0. device 6, function 0 contains the pci express configuration registers for pci express port 6. when pci express ports 4, 5, 6 and 7 are combined into a single x16 graphics port device 4, function 0 co ntains the configuration registers, and these configuration registers are inactive. pci express port 6 resides at did of 25e6h(x4) or 25f9(x8). ? device 7: pci express 7. logically this appears as a pci device residing on bus 0. device 7, function 0 contains the pci express configuration registers for pci express port 7. when pci express ports 4, 5, 6 and 7 are combined into a single x16 graphics port device 4, function 0 co ntains the configuration registers, and these configuration registers are inactive. pci express port 2 resides at did of 25e7h. ? device 9: device 9, function 0 is routed to the advanced memory buffer memory map. this interface is supported thro ugh the jtag and smbus interfaces and ambselect register only. ? device 16 : device 16, function 0 is routed to the frontside bus (fsb) controller, interrupt and system address registers. fu nction 1 is routed to the frontside bus address mapping, memory control, and error registers. function 2 is routed to fsb error registers. these devices reside at did 25f0h.
register description 46 intel ? 5000x chipset memory controller hub (mch) datasheet ? device 17 : device 17, function 0 is routed to the coherency engine and data manager registers. these devices reside at did 25f1h. ? device 19: device 19, function 0 is routed to the debug and miscellaneous registers. these devices reside at did 25f3h. ? device 21: device 21, function 0, fbd branch 0 memory map, error flag/mask, and channel control registers. these devices reside at did 25f5h. ? device 22: device 22, function 0, fbd branch 1 memory map, error flag/mask, and channel control registers. these devices reside at did 25f6h. figure 3-1. conceptual intel? 5000x ch ipset mch pci configuration diagram processor 0 intel? 5000x chipset dmi (pci express bridge bus 0, dev 0) pci config window in i/o space intel? 631xesb/632xesb i/o controller hub lpc device bus 0, dev 31, func 0 ide controller bus 0, dev 31, func 1 smbus controller bus 0, dev 31, func 3 ac97 controller bus 0, dev 31, func 5,6 usb controllers bus 0, dev 29, func 0,1,2,7 lan controller bus n , dev 8, func 0 primary pci programmable bus # dmi interface (logical pci bus 0) 4 bit pci express port 2 processor 1 dmi (pci express bridge bus 0, dev x) pci express port 4 bridge bus 0, dev 4 pci express port 5 bridge bus 0, dev 5 pci express port 6 bridge bus 0, dev 6 pci express port 7 bridge bus 0, dev 7 pci express port 2 bridge bus 0, dev 2 pci express port 3 bridge bus 0, dev 3 4 bit pci express port 3 4 bit pci express port 4 4 bit pci express port 5 4 bit pci express port 6 4 bit pci express port 7 4 bit pci express port 0 pci express port 0 bridge bus 0, dev y pci express port 1 bridge bus 0, dev z 4 bit pci express port 0 hi-pci bridge bus 0, dev 30, func 0
intel ? 5000x chipset memory controller hub (mch) datasheet 47 register description 3.3 routing configuration accesses intel? 5000x chipset mch supports both pc i type 0 and type 1 configuration access mechanisms as defined in the pci local bus specification , revision 2.3. pci revision 2.3 defines hierarchical pci busses. type 0 configuration access are used for registers located within a pci device that resides on the local pci bus. that is, the pci bus the transaction is initiated on. type 0 configurat ion transactions are not propagated beyond the local pci bus. type 0 configuration transactions must be claimed by a local device or master aborted. type 1 configuration accesses are used for de vices residing on subordinate pci buses. i.e devices that are connected via pci-to-pci bridges. all targets except pci-to-pci bridges ignore type 1 configuration transactions. pci-to-pci bridges decode the bus number information in type 1 transactions. it the transaction is targeted to a device local to the pci-to-pci bridge it is translated into a type 0 transaction and issued to the device. if the transaction is targeted to a bus subordinate (behind) to pci-to-pci bridge, it passed through unchanged. otherwise the type 1 transaction is dropped. accesses to non operational or non existent devices are master aborted. this means that writes are dropped and reads return all 1?s. 3.3.1 standard pci bus configuration mechanism the pci bus defines a slot based ?configuration space? that supports up to 32 devices. each device is allowed to contain up to eight functions with each function containing up to 256, 8-bit configuration registers. the pci specification defines two bus cycles to access the pci configuration space: config uration read and configuration write. memory and i/o spaces are supported directly by the processor. configuration space is supported by a mapping mechanism implemented within the mch. the pci 2.3 specification defines the configuration mechanism to access configuration space. the configuration access mechanism makes use of the config_address register (at i/o address 0cf8h through 0cfbh) and config_data register (at i/o address 0cfch through 0cffh). to reference a configuration register a dword i/o write cycle is used to place a value into config_address that sp ecifies the pci bus, the device on that bus, the function within the device, and a sp ecific configuration register of the device function being accessed. config_address[31] must be set to 1b, to enable a configuration cycle. config_data then becomes a window into the four bytes of configuration space specified by the conten ts of config_address. any read or write to config_data will result in the mch translating the config_address into the appropriate configuration cycle. the mch is responsible for translating and routing the processor?s i/o accesses to the config_address and config_data regist ers to internal mch configuration registers. 3.3.2 pci bus 0 configuration mechanism the mch decodes the bus number (bits 23:16 ) and the device number fields of the config_address register. if the bus numb er field of config_address is 0, the configuration cycle is targeting a device on pci bus 0. the esi bridge entity within the mch is ha rdwired as device 0 on pci bus 0. the esi bridge passes pci south bridge configuration requests to the south bridge.
register description 48 intel ? 5000x chipset memory controller hub (mch) datasheet 3.3.3 primary pci and downstre am configuration mechanism if the bus number in the config_address is non-zero, the mch will generate a type 1 pci configuration cycle. a[1:0] of the esi request packet for the type 1 configuration cycle will be 01. bits 31:2 of the config_ad dress register will be translated to the a[31:2] field of the esi request packet of the configuration cycle as shown in figure 3-2 . this configuration cycle will be sent over the esi to intel 631xesb/632xesb i/o controller hub. if the cycle is forwarded to the intel 631x esb/632xesb i/o controller hub via esi, the intel 631xesb/632xesb i/o controller hub co mpares the non-zero bus number with the secondary bus number and subordinate bus number registers of its pci-to-pci bridges to determine if the configuration cycl e is meant for primary pci bus, one of the intel 631xesb/632xesb i/o controller hub?s pci express ports, or a downstream pci bus. 3.4 device mapping each component in a intel? 5000x chipset sy stem is uniquely identified by a pci bus address consisting of; bus number, device number and function number. device configuration is based on the pci type 0 configuration conventions. all pci devices within a intel? 5000x chipset platform must support type 0 configuration accesses. all mch registers in the intel? 5000x chipset mch appear on bus #0. all intel? 5000x chipset mch configuration re gisters reside in the configuration space defined by bus, device, function, register ad dress. some registers do not appear in all portions of this space and some mechanisms do not access all portions of this space. in general the configuration space is sparsely populated. the following table defines where the various fields of configuration register addresses appear. each row defines a different access mechanism, register, interf ace, or decoder. each column defines a different field of the configuration address. figure 3-2. type 1 configuratio n address to pci address mapping reg. index reg. index device number function number bus number reserved 1 function number device number bus number 0 config_address 31 16 15 8 7 0 1 2 1 1 1 0 2 3 2 4 16 15 11 7 0 21 8 1 0 2 3 3 1 3 0 2 4 0 1 x x pci address ad[31:0]
intel ? 5000x chipset memory controller hub (mch) datasheet 49 register description . 3.4.1 device identification for intel 5000p chipset, intel 5000z chipset, and intel 5000 v chipset components all devices in the intel? 5000x chipset mch reside on bus 0. the following table describes the root device id for different mch versions. table 3-1. configuration address bit mapping source/ destination bus device function dword offset byte in dword type [11:8] [5:0] pci express config txns (including esi) destination bus[7:0] device[4:0] function[2:0 ] extended register addr[3:0] register [5:0] 1st dw be[3:0] fmt, type pci express mmcfg on fsb source a[27:20] a[19:15] a[14:12] a[11:8] a[7:3] be[7:4] be[7:0] n/a pci express mmcfg from esi or pci express not permitted to access mch or fb-di mm regs and will be master aborted. cpu/inbound cb_bar mmio access source 0 8 1 a[11:8] a[7:3] be[7:4] be[7:0] n/a cfgadr register source bus number [7:0] deviceid [4:0] function number[2:0] not present register address [5:0] not present n/a cfc on fsb source cfgadr register, see row above be[7:4] n/a jtag config access source bus number [7:0] deviceid [4:0] function number[2:0] extended register addr[3:0] register address[7:2 ] register address [1:0] n/a smbus config access source bus number [7:0] dev[4:0] func[2:0] reg number [11:8] reg[7:2] command, register number n/a fixed mch memory mapped on fsb source 0 16 0 cannot access a[15:10] all accesses are 4 byte n/a mch register decoding destination 00000000 see table 14-4 function[2:0 ] dword offset[9:6] dword offset[5:0] byte[3:0] n/a fb-dimm config cmds destination a[23:15] always 0 see note 1 notes: 1. these accesses are used to select channel/dimm based on the ambase register. cannot access a[7:3] be[7:4] be[7:0] n/a table 3-2. memory control hub esi device identification component register group did device functio n intel 5000p chipset enterprise so uth bridge interface 25c8h 0 0 intel 5000z chipset enterprise south bridge interface 25d0h intel 5000v chipset enterprise so uth bridge interface 25d4h 0 0
register description 50 intel ? 5000x chipset memory controller hub (mch) datasheet 3.4.2 special device and function routing all devices in the intel? 5000x chipset mch reside on bus 0. the following table describes the devices and functions that th e mch implements or routes specially. the dimm component designator consists of a three-digit code: the first digit is the branch, the second digit is the channel on the bran ch, and the third digit is the dimm (fb-dimm command ?ds? field) on the channel. to comply with the pci specification, accesse s to non-existent functions, registers, and bits will be master aborted. this beha vior is defined in the following table: table 3-3. functions specially handled by the mch component register group did device functio n comment mch pci express port 2 25e2h 2 0 depending on what is connected to these ports, some may not be accessible. mch pci express port 3 25e3h 3 0 mch pci express port 4 25e4h 4 0 mch pci express port 5 25e5h 5 0 mch pci express port 6 25e6h 6 0 mch pci express port 7 25e7h 7 0 mch dma engine 1a38h 8 0 new device mapping for dma engine mch dma engine mmio space n/a 8 1 mch memory map, error flag/mask, ras, channel control for fb- dimm branch 0 25f5h 21 0 debug and dft in higher address offsets. mch memory map, error flag/mask, ras, channel control for fb- dimm branch 1 25f6h 22 0 debug and dft in higher address offsets. mch processor bus, boot, interrupt, system address 25f0h 16 0 debug and dft in higher address offsets. dimm amb memory mapped registers n/a 9 0 route out to amb per ambselect register only for jtag/smbus. mch address mapping, memory control, error logs 25f0h 16 1 debug and dft in higher address offsets. mch fsb error registers 25f0h 16 2 mch pci express port 2-3 25f7h 2 0 x8 mode. only port 2 is active mch pci express port 4-5 25f8h 4 0 x8 mode. only port 4 is active mch pci express port 6-7 25f9h 6 0 x8 mode. only port 6 is active mch pci express port 4-7 25fah 4 0 x16 mode. only port 4 is active
intel ? 5000x chipset memory controller hub (mch) datasheet 51 register description 3.5 i/o mapped registers there are only two i/o addresses that affect the intel 5000x mch state. the first address is the dword location (cf8h) references a read/write register that is named config_address. the second dword addr ess (cfch) references a read/write register named config_data. these two addresses are used for the pci cfch / cf8h configuration access mechanism. 3.5.1 cfgadr: configuration address register cfgadr is written only when a processor i/o transaction to i/o location cf8h is referenced as a dword; a byte or word reference will not access this register, but will generate an i/o space access. therefor the on ly i/o space taken up by this register is the dword at location cf8h. i/o devices that share the same address but use byte or word registers are not affected because their transactions will pass through the host bridge unchanged. the cfgadr register contains the bus numb er, device number, function number, and register offset for which a subsequent cfgdat access is intended. the mapping between fields in this register and pci express configuration transactions is defined by ta b l e 3 - 1 . table 3-4. access to ?non-e xistent? register bits access to writes reads devices listed in table 3-2, ?memory control hub esi device identification? on page 49 but to functions not listed have no effect mch returns all ones devices listed in table 3-2, ?memory control hub esi device identification? on page 49, but to registers not listed in ssection 3.8, ?register definitions.? have no effect mch returns all zeroes reserved bits in registers software must read- modify-write to preserve the value mch returns all zeroes table 3-5. i/o address: cf8h bit attr default description 31 rw 0h cfge: configuration enable unless this bit is set, accesses to the cfgdat register will not produce a configuration access, but will be treated as other i/o accesses. this bit is strictly an enable for the cfc/cf8 a ccess mechanism and is not forwarded to esi or pci express. 30:24 rv 00h reserved. 23:16 rw 00h bus number if 0, the mch examines device to determine where to route. if non-zero, route as per pbusn and sbusn registers. 15:11 rw 0h device number this field is used to select one of the 32 possible devices per bus. 10:8 rw 0h function number this field is used to select the function of a locally addressed register. 7:2 rw 00h register offset if this register specifies an access to mch registers, this field specifies a group of four bytes to be addressed. the bytes accessed are defined by the byte enables of the cfgdat register access 1:0 rw 0h writes to these bits have no effect, reads return 0
register description 52 intel ? 5000x chipset memory controller hub (mch) datasheet 3.5.2 cfgdat: configuration data register cfgdat provides data for the 4 bytes of configuration space defined by cfgadr. this register is only accessed if there is an acce ss to i/o address, cfch on the processor bus and cfgadr.cfge (configuration enable) bit is set. the byte enables with the i/o access define how many configuration bytes are accessed. 3.6 mch fixed memory mapped registers these registers are mapped into the fixed chipset specific range located from fe60 0000h - fe6f ffffh.these appear at fixed addresses to support the boot process. these registers also appear in the re gular pci express configuration space. the following table defines the memory address of the registers in this region. table 3-6. i/o address: cfch bit attr default description 31:0 rw 0 configuration data window the data written or read to the configuration register (if any) specified by cfgadr table 3-7. mapping for fixed memory mapped registers register memory address bofl0 fe60_c000 bofl1 fe60_c400 bofl2 fe60_c800 bofl3 fe60_cc00 spad0 fe60_d000 spad1 fe60_d400 spad2 fe60_d800 spad3 fe60_dc00 spads0 fe60_e000 spads1 fe60_e400 spads2 fe60_e800 spads3 fe60_ec00 ambase[31:0] fe61_4800 ambase[63:32] fe61_4c00 hecbase fe61_6400
intel ? 5000x chipset memory controller hub (mch) datasheet 53 register description 3.7 detailed configuration space maps table 3-8. device 0, function 0: pci express pci space did vid 00h pexslotcap 80h pcists pcicmd 04h pexslotsts pexslotctrl 84h ccr rid 08h pexrtctrl 88h bist hdr pri_lt cls 0ch pexrtsts 8ch 10h 90h 14h 94h 18h 98h 1ch 9ch 20h a0h 24h a4h 28h a8h sid svid 2ch ach 30h b0h capptr 34h b4h 38h b8h intp intl 3ch bch pexlwstpctrl 40h c0h ssctrl cbpres 44h c4h pexctrl 48h c8h intxswz ctrl pexctrl3 pexctrl2 4ch cch pmcap 50h d0h pmcsr 54h esictrl d4h msictrl msinxptr msicapid 58h d8h msiar 5ch dch msidr 60h e0h 64h e4h 68h e8h pexcap pexcapl 6ch ech pexdevcap 70h f0h pexdevsts pexdevctrl 74h f4h pexlnkcap 78h f8h pexlnksts pexlnkctrl 7ch fch
register description 54 intel ? 5000x chipset memory controller hub (mch) datasheet table 3-9. device 0, function 0: pci express exte nded registers pexenhcap 100h 180h uncerrsts 104h 184h uncerrmsk 108h 188h uncerrsev 10ch 18ch corerrsts 110h 190h corerrmsk 114h 194h aerrcapctrl 118h 198h hdrlog0 11ch 19ch hdrlog1 120h 1a0h hdrlog2 124h 1a4h hdrlog3 128h 1a8h rperrcmd 12ch 1ach rperrsts 130h 1b0h rperrsid 134h 1b4h 138h 1b8h 13ch 1bch intel 5000p sequence chipset mchspcapid 140h 1c0h pex_err_docmd 144h 1c4h emask_uncor_pex 148h 1c8h emask_cor_pex 14ch 1cch emask_rp_pex 150h 1d0h pex_fat_ferr 154h 1d4h pex_nf_cor_ferr 158h 1d8h pex_fat_nerr 15ch 1dch pex_nf_cor_nerr 160h 1e0h 164h 1e4h 168h 1e8h 16ch 1ech pex_sser r 170h 1f0h 174h 1f4h 178h 1f8h 17ch 1fch
intel ? 5000x chipset memory controller hub (mch) datasheet 55 register description table 3-10. device 0, function 0: pci express intel ? interconnect bist (intel ? ibist) registers 300h pex0ibctl 380h 304h pex0ibsymbuf 384h 308h pex0ibextctl 388h 30ch pex0ibloopcnt pex0ibdlysym 38ch 310h pex0ibln s3 pex0ibln s2 pex0ibln s1 pex0ibln s0 390h 314h dio0iber r dio0ibst at 394h 318h dioibstr 398h 31ch 39ch 320h 3a0h 324h 3a4h 328h 3a8h 32ch 3ach 330h 3b0h 334h 3b4h 338h 3b8h 33ch 3bch 340h 3c0h 344h 3c4h 348h 3c8h 34ch 3cch 350h 3d0h 354h 3d4h 358h 3d8h 35ch 3dch 360h 3e0h 364h 3e4h 368h 3e8h 36ch 3ech 370h 3f0h 374h 3f4h 378h 3f8h 37ch 3fch
register description 56 intel ? 5000x chipset memory controller hub (mch) datasheet table 3-11. device 2-3, functi on 0: pci express pci space did vid 00h pexslotcap 80h pcists pcicmd 04h pexslotsts pexslotctrl 84h ccr rid 08h pexrtctrl 88h bist hdr pri_lt cls 0ch pexrtsts 8ch 10h 90h 14h 94h sec_lt subusn sbusn pbusn 18h 98h secsts iolim iobase 1ch 9ch mlim mbase 20h a0h pmlim pmbase 24h a4h pmbu 28h a8h pmlu 2ch ach 30h b0h capptr 34h b4h 38h b8h bctrl intp intl 3ch bch 40h c0h ssctrl 44h c4h pexctrl 48h c8h intxswz ctrl cbctrl pexctrl3 pexctrl2 4ch cch pmcap 50h d0h pmcsr 54h d4h msictrl msinxptr msicapid 58h d8h msiar 5ch dch msidr 60h e0h 64h e4h 68h e8h pexcap pexcapl 6ch ech pexdevcap 70h f0h pexdevsts pexdevctrl 74h f4h pexlnkcap 78h f8h pexlnksts pexlnkctrl 7ch fch
intel ? 5000x chipset memory controller hub (mch) datasheet 57 register description table 3-12. device 2-3, function 0: pci express extended registers pexenhcap 100h 180h uncerrsts 104h 184h uncerrmsk 108h 188h uncerrsev 10ch 18ch corerrsts 110h 190h corerrmsk 114h 194h aerrcapctrl 118h 198h hdrlog0 11ch 19ch hdrlog1 120h 1a0h hdrlog2 124h 1a4h hdrlog3 128h 1a8h rperrcmd 12ch 1ach rperrsts 130h 1b0h rperrsid 134h 1b4h 138h 1b8h 13ch 1bch intel 5000p sequence chipset mchspcapid 140h 1c0h pex_err_docmd 144h 1c4h emask_uncor_pex 148h 1c8h emask_cor_pex 14ch 1cch emask_rp_pex 150h 1d0h pex_fat_ferr 154h 1d4h pex_nf_cor_ferr 158h 1d8h pex_fat_nerr 15ch 1dch pex_nf_cor_nerr 160h 1e0h 164h 1e4h pex_unit_ferr 168h 1e8h pex_unit_nerr 16ch 1ech pex_sser r 170h 1f0h 174h 1f4h 178h 1f8h 17ch 1fch
register description 58 intel ? 5000x chipset memory controller hub (mch) datasheet table 3-13. device 2-3, function 0: pci express intel ibist registers 300h pex[3:2]ibctl 380h 304h pex[3:2]ibsymbuf 384h 308h pex[3:2]ibextctl 388h 30ch pex[3:2]ibloopcnt pex[3:2]ibdlysym 38ch 310h pex[3:2]i blns3 pex[3:2]i blns2 pex[3:2]i blns1 pex[3:2]i blns0 390h 314h 394h 318h 398h 31ch 39ch 320h 3a0h 324h 3a4h 328h 3a8h 32ch 3ach 330h 3b0h 334h 3b4h 338h 3b8h 33ch 3bch 340h 3c0h 344h 3c4h 348h 3c8h 34ch 3cch 350h 3d0h 354h 3d4h 358h 3d8h 35ch 3dch 360h 3e0h 364h 3e4h 368h 3e8h 36ch 3ech 370h 3f0h 374h 3f4h 378h 3f8h 37ch 3fch
intel ? 5000x chipset memory controller hub (mch) datasheet 59 register description table 3-14. device 4, function 0: pci express pci space did vid 00h pexslotcap 80h pcists pcicmd 04h pexslotsts pexslotctrl 84h ccr rid 08h pexrtctrl 88h bist hdr pri_lt cls 0ch pexrtsts 8ch 10h 90h 14h 94h sec_lt subusn sbusn pbusn 18h 98h secsts iolim iobase 1ch 9ch mlim mbase 20h a0h pmlim pmbase 24h a4h pmbu 28h a8h pmlu 2ch ach 30h b0h capptr 34h b4h 38h b8h bctrl intp intl 3ch bch 40h c0h ssctrl 44h c4h pexctrl 48h c8h intxswz ctrl pexctrl3 pexctrl2 4ch cch pmcap 50h d0h pmcsr 54h d4h msictrl msinxptr msicapid 58h d8h msiar 5ch dch msidr 60h e0h 64h e4h 68h e8h pexcap pexcapl 6ch ech pexdevcap 70h f0h pexdevsts pexdevctrl 74h f4h pexlnkcap 78h f8h pexlnksts pexlnkctrl 7ch fch
register description 60 intel ? 5000x chipset memory controller hub (mch) datasheet table 3-15. device 4, function 0: pci express exte nded registers pexenhcap 100h 180h uncerrsts 104h 184h uncerrmsk 108h 188h uncerrsev 10ch 18ch corerrsts 110h 190h corerrmsk 114h 194h aerrcapctrl 118h 198h hdrlog0 11ch 19ch hdrlog1 120h 1a0h hdrlog2 124h 1a4h hdrlog3 128h 1a8h rperrcmd 12ch 1ach rperrsts 130h 1b0h rperrsid 134h 1b4h 138h 1b8h 13ch 1bch intel 5000p chipset mchspcapid 140h 1c0h pex_err_docmd 144h 1c4h emask_uncor_pex 148h 1c8h emask_cor_pex 14ch 1cch emask_rp_pex 150h 1d0h pex_fat_ferr 154h 1d4h pex_nf_cor_ferr 158h 1d8h pex_fat_nerr 15ch 1dch pex_nf_cor_nerr 160h 1e0h 164h 1e4h pex_unit_ferr 168h 1e8h pex_unit_nerr 16ch 1ech pex_sser r 170h 1f0h 174h 1f4h 178h 1f8h 17ch 1fch
intel ? 5000x chipset memory controller hub (mch) datasheet 61 register description table 3-16. device 4, function 0: pci express intel ibist registers 300h pex4ibctl 380h 304h pex4ibsymbuf 384h 308h pex4ibextctl 388h 30ch pex4ibloopcnt pex4ibdlysym 38ch 310h pex4ibln s3 pex4ibln s2 pex4ibln s1 pex4ibln s0 390h 314h 394h 318h 398h 31ch 39ch 320h 3a0h 324h 3a4h 328h 3a8h 32ch 3ach 330h 3b0h 334h 3b4h 338h 3b8h 33ch 3bch 340h 3c0h 344h 3c4h 348h 3c8h 34ch 3cch 350h 3d0h 354h 3d4h 358h 3d8h 35ch 3dch 360h 3e0h 364h 3e4h 368h 3e8h 36ch 3ech 370h 3f0h 374h 3f4h 378h 3f8h 37ch 3fch
register description 62 intel ? 5000x chipset memory controller hub (mch) datasheet table 3-17. device 5-7, functi on 0: pci express pci space did vid 00h pexslotcap 80h pcists pcicmd 04h pexslotsts pexslotctrl 84h ccr rid 08h pexrtctrl 88h bist hdr pri_lt cls 0ch pexrtsts 8ch 10h 90h 14h 94h sec_lt subusn sbusn pbusn 18h 98h secsts iolim iobase 1ch 9ch mlim mbase 20h a0h pmlim pmbase 24h a4h pmbu 28h a8h pmlu 2ch ach 30h b0h capptr 34h b4h 38h b8h bctrl intp intl 3ch bch 40h c0h ssctrl 44h c4h pexctrl 48h c8h intxswz ctrl pexctrl3 pexctrl2 4ch cch pmcap 50h d0h pmcsr 54h d4h msictrl msinxptr msicapid 58h d8h msiar 5ch dch msidr 60h e0h 64h e4h 68h e8h pexcap pexcapl 6ch ech pexdevcap 70h f0h pexdevsts pexdevctrl 74h f4h pexlnkcap 78h f8h pexlnksts pexlnkctrl 7ch fch
intel ? 5000x chipset memory controller hub (mch) datasheet 63 register description table 3-18. device 5-7, function 0: pci express extended registers pexenhcap 100h 180h uncerrsts 104h 184h uncerrmsk 108h 188h uncerrsev 10ch 18ch corerrsts 110h 190h corerrmsk 114h 194h aerrcapctrl 118h 198h hdrlog0 11ch 19ch hdrlog1 120h 1a0h hdrlog2 124h 1a4h hdrlog3 128h 1a8h rperrcmd 12ch 1ach rperrsts 130h 1b0h rperrsid 134h 1b4h 138h 1b8h 13ch 1bch intel 5000p chipset mchspcapid 140h 1c0h pex_err_docmd 144h 1c4h emask_uncor_pex 148h 1c8h emask_cor_pex 14ch 1cch emask_rp_pex 150h 1d0h pex_fat_ferr 154h 1d4h pex_nf_cor_ferr 158h 1d8h pex_fat_nerr 15ch 1dch pex_nf_cor_nerr 160h 1e0h 164h 1e4h pex_unit_ferr 168h 1e8h pex_unit_nerr 16ch 1ech pex_sser r 170h 1f0h 174h 1f4h 178h 1f8h 17ch 1fch
register description 64 intel ? 5000x chipset memory controller hub (mch) datasheet this function is only accessible by smbus or jtag. other accesses will be routed to esi and get master aborted. accessing to this function is routed out to fb-dimm channel as per ambselect register subject to ambpresent register settings. table 3-19. device 5-7, function 0: pci express intel ibist registers 300h pex[7:5]ibctl 380h 304h pex[7:5]ibsymbuf 384h 308h pex[7:5]ibextctl 388h 30ch pex[7:5]ibloopcnt pe[7:5]ibdlysym 38ch 310h pex[7:5]i blns3 pex[7:5]i blns2 pex[7:5]i blns1 pex[7:5]i blns0 390h 314h 394h 318h 398h 31ch 39ch 320h 3a0h 324h 3a4h 328h 3a8h 32ch 3ach 330h 3b0h 334h 3b4h 338h 3b8h 33ch 3bch 340h 3c0h 344h 3c4h 348h 3c8h 34ch 3cch 350h 3d0h 354h 3d4h 358h 3d8h 35ch 3dch 360h 3e0h 364h 3e4h 368h 3e8h 36ch 3ech 370h 3f0h 374h 3f4h 378h 3f8h 37ch 3fch table 3-20. device 9, function 0: amb switching window registers route out amb as per ambselect register 0h - 255h
intel ? 5000x chipset memory controller hub (mch) datasheet 65 register description table 3-21. device 16, function 0: processor bus, boot, and interrupt did vid 00h xtpr0 80h 04h xtpr1 84h ccr rid 08h xtpr2 88h hdr 0ch xtpr3 8ch 10h xtpr4 90h 14h xtpr5 94h 18h xtpr6 98h 1ch xtpr7 9ch 20h xtpr8 a0h 24h xtpr9 a4h 28h xtpr10 a8h sid svid 2ch xtpr11 ach 30h xtpr12 b0h 34h xtpr13 b4h 38h xtpr14 b8h 3ch xtpr15 bch cpurstcaptmr syre 40h bofl0 c0h poc 44h bofl1 c4h ambase 48h bofl2 c8h 4ch bofl3 cch amr 50h spad0 d0h maxamb perch maxch ambselect 54h spad1 d4h pam2 pam1 pam0 58h spad2 d8h pam6 pam5 pam4 pam3 5ch spad3 dch exsmrtop exsmrc smramc exsmramc 60h spads0 e0h hecbase 64h spads1 e4h redirbuckets 68h spads2 e8h redirctl 6ch spads3 ech 70h procenable f0h 74h f4h 78h f8h 7ch fch
register description 66 intel ? 5000x chipset memory controller hub (mch) datasheet table 3-22. device 16, function 1: me mory branch map, control, errors did vid 00h mir0 80h 04h mir1 84h ccr rid 08h mir2 88h hdr 0ch amir0 8ch 10h amir1 90h 14h amir2 94h 18h ferr_fat_fbd 98h 1ch nerr_fat_fbd 9ch 20h ferr_nf_fbd a0h 24h nerr_nf_fbd a4h 28h emask_fbd a8h sid svid 2ch err0_fbd ach 30h err1_fbd b0h 34h err2_fbd b4h 38h mcerr_fbd b8h 3ch nrecmema bch mc 40h nrecmemb c0h 44h nrecfglog c4h drta 48h nrecfbda c8h drtb 4ch nrecfbdb cch errper 50h nrecfbdc d0h ddrfrq 54h nrecfbdd d4h mca 58h nrecfbde d8h 5ch reserved dch gblact 60h recmema e0h thrtctrl thrthi thrtmid thrtlow 64h recmemb e4h thrtsts1 thrtsts0 68h recfglog e8h tolm 6ch recfbda ech 70h recfbdb f0h 74h recfbdc f4h 78h recfbdd f8h redmemb 7ch recfbde fch
intel ? 5000x chipset memory controller hub (mch) datasheet 67 register description table 3-23. device 16, function 2: ras did vid 00h 80h 04h 84h ccr rid 08h 88h hdr 0ch 8ch 10h 90h 14h 94h 18h 98h 1ch 9ch 20h a0h 24h a4h 28h a8h sid svid 2ch ach 30h nrecsf b0h 34h b4h 38h recsf b8h 3ch bch ferr_global 40h nerr_nf_i nt nerr_fat_ int ferr_nf_i nt ferr_fat_i nt c0h nerr_global 44h nrecint c4h 48h recint c8h 4ch emask_int cch 50h mcerr_int err2_int err1_int err0_int d0h 54h d4h 58h d8h 5ch dch 60h e0h 64h e4h 68h e8h 6ch ech 70h f0h 74h f4h 78h f8h 7ch fch
register description 68 intel ? 5000x chipset memory controller hub (mch) datasheet table 3-24. device 21, 22, function 0: fb-dimm map, control, ras did vid 00h mtr0 80h 04h mtr1 84h ccr rid 08h mtr2 88h hdr 0ch mtr3 8ch 10h dmir0 90h 14h dmir1 94h 18h dmir2 98h 1ch dmir3 9ch 20h dmir4 a0h 24h uerrcnt a4h 28h cerrcnt a8h sid svid 2ch badrama ach 30h badramb b0h 34h badcnt b4h 38h b8h 3ch bch spcps spcpc 40h fbdsbtxcf g1 fbdsbtxcf g0 c0h fbdicmd1 fbdicmd0 fbdlvl1 fbdlvl0 44h c4h fbdst hpst0 48h c8h fbdhpc hphpc0 4ch cch hpst1 50h d0h hpctl1 54h d4h fbdists1 fbdists0 58h d8h 5ch dch 60h e0h ambpresent1 ambpresent0 64h e4h 68h e8h 6ch ech 70h f0h spd1 spd0 74h f4h spdcmd0 78h f8h spdcmd1 7ch fch
intel ? 5000x chipset memory controller hub (mch) datasheet 69 register description table 3-25. device 21, function 0: fb-dimm 0 intel ibist registers 100h fbd0ibportctl 180h 104h fbd0ibtxpgctl 184h 108h fbd0ibpatbuf1 188h 10ch fbd0ibtxmsk 18ch 110h fbd0ibrxmsk 190h 114h fbd0ibtxshft 194h 118h fbd0ibrxshft 198h 11ch fbd0rxlnerr 19ch 120h fbd0ibrxpgctl 1a0h 124h fbd0ibpatbuf2 1a4h 128h fbd0ibtxpat2en 1a8h 12ch fbd0ibrxpat2en 1ach 130h 1b0h 134h 1b4h 138h fbd0ts1parm 1b8h 13ch 1bch 140h fbdpllctrl 1c0h 144h 1c4h 148h 1c8h 14ch 1cch 150h 1d0h 154h 1d4h 158h 1d8h 15ch 1dch 160h 1e0h 164h 1e4h 168h 1e8h 16ch 1ech 170h 1f0h 174h 1f4h 178h 1f8h 17ch 1fch
register description 70 intel ? 5000x chipset memory controller hub (mch) datasheet table 3-26. device 21, function 0: fb-dimm 1 ibst registers 200h fbd1ibportctl 280h 204h fbd1ibtxpgctl 284h 208h fbd1ibpatbuf 288h 20ch fbd1ibtxmsk 28ch 210h fbd1ibrxmsk 290h 214h fbd1ibtxshft 294h 218h fbd1ibrxshft 298h 21ch fbd1rxlnerr 29ch 220h fbd1ibrxpgctl 2a0h 224h fbd1ibpatbuf2 2a4h 228h fbd1ibtxpat2en 2a8h 22ch fbd1ibrxpat2en 2ach 230h 2b0h 234h 2b4h 238h fbd1ts1parm 2b8h 23ch 2bch 240h 2c0h 244h 2c4h 248h 2c8h 24ch 2cch 250h 2d0h 254h 2d4h 258h 2d8h 25ch 2dch 260h 2e0h 264h 2e4h 268h 2e8h 26ch 2ech 270h 2f0h 274h 2f4h 278h 2f8h 27ch 2fch
intel ? 5000x chipset memory controller hub (mch) datasheet 71 register description table 3-27. device 22, function 0: fb-dimm 2 ibst registers 100h fbd2ibportctl 180h 104h fbd2ibpgctl 184h 108h fbd2ibpatbuf 188h 10ch fbd2ibtxmsk 18ch 110h fbd2ibrxmsk 190h 114h fbd2ibtxshft 194h 118h fbd2ibrxshft 198h 11ch fbd2rxlnerr 19ch 120h fbd2ibrxpgctl 1a0h 124h fbd2ibpatbuf2 1a4h 128h fbd2ibtxpat2en 1a8h 12ch fbd2ibrxpat2en 1ach 130h 1b0h 134h 1b4h 138h fbd2ts1parm 1b8h 13ch 1bch 140h 1c0h 144h 1c4h 148h 1c8h 14ch 1cch 150h 1d0h 154h 1d4h 158h 1d8h 15ch 1dch 160h 1e0h 164h 1e4h 168h 1e8h 16ch 1ech 170h 1f0h 174h 1f4h 178h 1f8h 17ch 1fch
register description 72 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8 register definitions 3.8.1 pci standard registers these registers appear in every function for every device. 3.8.1.1 vid - vendor identification register the vid register contains the vendor identification number. this 16-bit register, combined with the device identification register uniquely identifies the manufacturer of the function with in the mch. writes to this register have no effect. table 3-28. device 22, function 0: fb-dimm 3 intel ibist registers 200h fbd3ibportctl 280h 204h fbd3ibpgctl 284h 208h fbd3ibpatbuf 288h 20ch fbd3ibtxmsk 28ch 210h fbd3ibrxmsk 290h 214h fbd3ibtxshft 294h 218h fbd3ibrxshft 298h 21ch fbd3rxlnerr 29ch 220h fbd3ibrxpgctl 2a0h 224h fbd3ibpatbuf2 2a4h 228h fbd3ibtxpat2en 2a8h 22ch fbd3ibrxpat2en 2ach 230h 2b0h 234h 2b4h 238h fbd3ts1parm 2b8h 23ch 2bch 240h 2c0h 244h 2c4h 248h 2c8h 24ch 2cch 250h 2d0h 254h 2d4h 258h 2d8h 25ch 2dch 260h 2e0h 264h 2e4h 268h 2e8h 26ch 2ech 270h 2f0h 274h 2f4h 278h 2f8h 27ch 2fch
intel ? 5000x chipset memory controller hub (mch) datasheet 73 register description 3.8.1.2 did - device identification register this 16-bit register combined with the vendor identification register uniquely identifies the function with in the mch. writes to this register have no effect. see ta b l e 3 - 3 for the did of each mch function. device: 0, 2-3, 8, 9 function: 0 offset: 00h version: intel 5000p chipset ,intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 00h version: intel 5000z chipset device: 4-7 function: 0 offset: 00h version: intel 5000p chipset device: 16 function: 0, 2 offset: 00h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 17 function: 0 offset: 00h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 21 function: 0 offset: 00h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 22 function: 0 offset: 00h version: intel 5000p chipset bit attr default description 15:0 ro 8086h vendor identification number the value assigned to intel.
register description 74 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.1.3 rid - revision identification register this register contains the revision number of the mch. the revision id (rid) is a traditional 8-bit read only (ro) register located at offset 08h in the standard pci header of every pci/pci express compatible device and function. previously, a new value for rid was assigned for intel chipsets for every . there is a a need to provide an alternative value for software compatibility when a particular driver or patch unique to that stepping or an earlier stepping is required, for instance, to prevent windows software from flagging differences in rid duri ng device enumeration. the solution is to implement a mechanism to read one of two possible values from the rid register: 1. stepping revision id (srid): this is the default power on value for mask/metal steppings. 2. compatible revision id (crid): the crid functionality gives bios the flexibility to load os drivers optimized for a previous revision of the silicon instead of the current revision of the silicon in order to reduce drivers updates and minimize changes to the os image for minor optimizations to the silicon for yield improvement, or feature enhancement reasons that do not negatively impact the os driver functionality. reading the rid in the intel 5000p chipset mch returns either the srid or crid depending on the state of a register select f lip-flop. following reset, the register select flip flop is reset and the srid is returned when the rid is read at offset 08h. the srid device: 0, 2-3, 8, 9 function: 0 offset: 02h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 00h version: intel 5000z chipset device: 4-7 function: 0 offset: 02h version: intel 5000p chipset device: 16 function: 0, 2 offset: 02h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 17 function: 0 offset: 02h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 21 function: 0 offset: 02h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 22 function: 0 offset: 020h version: intel 5000p chipset bit attr default description 15:0 rwo *see ta b l e 3 - 2 device identification number identifies each function of the mch
intel ? 5000x chipset memory controller hub (mch) datasheet 75 register description value reflects the actual product stepping. to select the crid value, bios/configuration software writes a key value of 79h to bus 0, device 0, function 0 (esi port) of the intel 5000p chipset mch?s rid register at offset 08h. this sets the srid/crid register select flip-flop and causes the crid to be re turned when the rid is read at offset 08h. the rid register in the esi port (bus 0 device 0 function 0) is a ?write-once? sticky register and gets locked after the first write. this causes the crid to be returned on all subsequent rid register reads. software should read and save all device srid values by reading intel 5000p chipset mch device rid registers before setting the srid/crid register select flip flop. the rid values for all devices and functions in intel 5000p chipset mch are controlled by the srid/crid register select flip flop, thus writing the key value (79h) to the rid register in bus 0, device 0, function 0 sets all intel 5000p chipset mch device rid registers to return the crid. writing to the rid register of other devices has no effect on the srid/crid register select flip-flop. only a power good reset can change the rid selection back to srid. device: 0, 2-3, 8, 9 function: 0 offset: 08h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 08h version: intel 5000z chipset device: 4-7 function: 0 offset: 08h version: intel 5000p chipset device: 16 function: 0, 2 offset: 08h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset, device: 17 function: 0 offset: 08h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 21 function: 0 offset: 08h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 22 function: 0 offset: 08h version: intel 5000p chipset bit attr default description 7:4 if (dev 0) {rwost} else {ro} endif 0h major revision steppings which require all masks to be regenerated 1 . 0000: a stepping for intel 5000 series chipset with sf 0001: b stepping for intel 5000 series chipset with sf 0010: c stepping for intel 5000 series chipset with sf 1000: a stepping with intel 5000 series chipset without sf 1001: b stepping with intel 5000 series chipset without sf 1010: c stepping with intel 5000 series chipset without sf others: reserved
register description 76 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.1.3.1 stepping revision id (srid) the srid is a 4-bit hardwired value assigned by intel, based on product?s stepping. the srid is not a directly addressable pci register. the srid value is reflected through the rid register when appropriately addressed. th e 4 bits of the srid are reflected as the two least significant bits of the major an d minor revision field respectively. see figure 3-3 3.8.1.3.2 compatible revision id (crid) the crid is an 4-bit hardwired value assigned by intel during manufacturing process. normally, the value assigned as the crid will be identical to the srid value of a previous stepping of the product with whic h the new product is deemed ?compatible?. 3:0 if (dev 0) {rwost} else {ro} endif 0h minor revision incremented for each stepping which does not modify all masks. reset for each major revision. 0x0: m0 stepping 0x1: m1 stepping 0x2: m2 stepping others: reserved note: the metal steppings indicated are a subset of the major revision. for example, an a stepping with m0 as minor revision typically means a0. notes: 1. even though the contents of the rid have an attribute as ?ro?, it is ultimately dictated by the comparator flop (attribute ?rwost? in device 0, function 0) that se lects between the crid/srid outputs. the comparator is set by bios/sw writing a specific value to offset 08h in dev0, fn 0 based on figure 3-3 . device: 0, 2-3, 8, 9 function: 0 offset: 08h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 08h version: intel 5000z chipset device: 4-7 function: 0 offset: 08h version: intel 5000p chipset device: 16 function: 0, 2 offset: 08h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset, device: 17 function: 0 offset: 08h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 21 function: 0 offset: 08h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 22 function: 0 offset: 08h version: intel 5000p chipset bit attr default description
intel ? 5000x chipset memory controller hub (mch) datasheet 77 register description the crid is not a directly addressable pci register. the crid value is reflected through the rid register when appropriately addressed.the 4 bits of the crid are reflected as the two least significant bits of the major and minor revision field respectively. see figure 3-3 . 3.8.1.4 ccr - class code register this register contains the class code for the device. writes to this register have no effect. figure 3-3. intel 5000p chipset mch implem entation of srid and crid registers 0 1 2 3 4 5 6 7 major rev id minor rev id device 1 :0, 2-3, 9 function: 0 offset: 09h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 09h version: intel 5000z chipset device: 4-7 function: 0 offset: 09h version: intel 5000p chipset device: 16 function: 0, 2 offset: 09h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 17 function: 0 offset: 09h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 21 function: 0 offset: 09h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 22 function: 0 offset: 09h version: intel 5000p chipset bit attr default description 23:16 ro 06h base class . this field indicates the general device category. for the mch, this field is hardwired to 06h, indicating it is a ?bridge device?.
register description 78 intel ? 5000x chipset memory controller hub (mch) datasheet 15:8 ro if (dev2-7) {04h} else {00h} sub-class. this field qualifies the base class, provid ing a more detailed specification of the device function. for pci express devices 2,3,4,5, 6,7 default is 040h, indicating ?pci to pci bridge? for all other devices: 0,9,10,12,14,16,17, 18,19 default is 00h, indicating ?host bridge?. see footnote a, for dma engine device ccr. 7:0 ro 00h register-level programming interface. this field identifies a sp ecific programming interface (if any), that device independent software can use to interact with the device. there are no such interfaces defined for ?host bridge? types, and this field is hardwired to 00h. notes: 1. the dma engine ccr for device 8 is defined separately in section 3.10.3 . device 1 :0, 2-3, 9 function: 0 offset: 09h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 09h version: intel 5000z chipset device: 4-7 function: 0 offset: 09h version: intel 5000p chipset device: 16 function: 0, 2 offset: 09h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 17 function: 0 offset: 09h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 21 function: 0 offset: 09h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 22 function: 0 offset: 09h version: intel 5000p chipset bit attr default description
intel ? 5000x chipset memory controller hub (mch) datasheet 79 register description 3.8.1.5 hdr - header type register this register identifies the header layout of the co nfiguration space. device: 0, 2-3, 8, 9 function: 0 offset: 0eh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 0eh version: intel 5000z chipset device: 4-7 function: 0 offset: 0eh version: intel 5000p chipset device: 16 function: 0, 2 offset: 0eh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 17 function: 0 offset: 0eh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 21 function: 0 offset: 0eh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 22 function: 0 offset: 0eh version: intel 5000p chipset bit attr default description 7ro if (dev16) {1h} else {0h} endif multi-function device. selects whether this is a multi-functi on device, that may have alternative configuration layouts. this bit is hardwired to ?0? for devices for the mch with the exception of device 16 fn 0-2, which it is set to ?1?. 6:0 ro if (dev2-7) {01h} else {00h} endif configuration layout. this field identifies the format of the configuration header layout for a pci-to-pci bridge from bytes 10h through 3fh. for pci express devices 2,3,4,5, 6,7 default is 01h, indicating ?pci to pci bridge? for all other devices: 0,8, 9,16,17,21,22 default is 00h, indicating a conventional type 00h pci header
register description 80 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.1.6 svid - subsystem vend or identification register this register identifies the manufacturer of the system. this 16-bit register combined with the device identification register uniqu ely identify any pci device. they appear in every function except the pci express functions. a write to any of the above registers on the mch will write to all of them. device: 0, 8 function: 0 offset: 2ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 16 function: 0, 2 offset: 2ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 17 function: 0 offset: 2ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 21 function: 0 offset: 2ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 22 function: 0 offset: 2ch version: intel 5000p chipset bit attr default description 15:0 rwo 8086h vendor identification number . the default value specifies intel. each byte of this register will be writable once. second and successive writes to a byte will have no effect.
intel ? 5000x chipset memory controller hub (mch) datasheet 81 register description 3.8.1.7 sid - subsystem identity this register identifies the system. they appear in every function except the pci express functions. 3.8.2 address mapping registers these registers control transaction routing to one of the three interface types (memory, pci express, or esi) based on transaction addresses. the memory mapping registers in this section are made read-only by the lt.lock-memconfig command. routing to particular ports of a given interface type are defined by the following registers: the mch allows programmable memory attrib utes on 13 legacy memory segments of various sizes in the 640 kilobytes to 1 megabytes address range. seven programmable attribute map (pam) registers are used to support these features. device: 0, 8 function: 0 offset: 2eh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 16 function: 0, 2 offset: 2eh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 17 function: 0 offset: 2eh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 21 function: 0 offset: 2eh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 22 function: 0 offset: 2eh version: intel 5000p chipset bit attr default description 15:0 rwo 8086h subsystem identification number: the default value specifies inte l. each byte of this regist er will be writable once. second and successive writes to a byte will have no effect. table 3-29. address mapping registers interface type address routing registers memory mir, amir, pam, smram, exsmrc, exsmramc, tolm, exsmrtop, ambase, amr pci express mbase/mlim (devices 2-7) pmbase/pmlim (devices 2-7) pmbu/pmbl (devices 2-7) iobase/iolim (devices 2-7) sbusn,subusn (devices 2-7) bctrl, hecbase, pcicmd (devices 2-7) esi subtractive decode 1 (device 0) notes: 1. any request not falling in the abov e ranges will be subtractively decode d and sent to intel 631xesb/632xesb i/o controller hub via the esi
register description 82 intel ? 5000x chipset memory controller hub (mch) datasheet each pam register controls one or two regions, typically 16 kilobytes in size 3.8.2.1 pam0 - programmable attribute map register 0 this register controls the read, write, and shadowing attributes of the bios area which extends from 0f 0000h - 0f ffffh. two bits are used to specify memory attributes for each memory segment. these bits apply to both host accesses and pci initiator accesses to the pam areas. these attributes are: re - read enable. when re = 1, the cpu read accesses to the corresponding memory segment are claimed by the mch and directed to main memory. conversely, when re = 0, the host read accesses are directed to esi (intel 631xesb/632xesb i/o controller hub) to be directed to the pci bus. we - write enable. when we = 1, the host write accesses to the corresponding memory segment are claimed by the mch an d directed to main memory. conversely, when we = 0, the host write accesses are di rected to esi (intel 631xesb/632xesb i/o controller hub) to be directed to the pci bus. the re and we attributes permit a memory segment to be read only, write only, read/write, or disabled. for example, if a memory segment has re = 1 and we = 0, the segment is read only. device: 16 function: 0 offset: 59h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7:6 rv 00 reserved 5:4 rw 00 esienable0: 0f0000-0fffff attribute register this field controls the steering of read and write cycles that address the bios area from 0f0000 to 0fffff. bit5 = write enable, bit4 = read enable. encoding description 00: dram disabled - all accesses are directed to esi 01: read only - all reads are serviced by dram. writes are forwarded to esi 10: write only - all writes are sent to dram. reads are serviced by esi 11: normal dram operation - all reads and writes are serviced by dram 3:0 rv 0h reserved
intel ? 5000x chipset memory controller hub (mch) datasheet 83 register description 3.8.2.2 pam1 - programmable attribute map register 1 this register controls the read, write, and shadowing attributes of the bios areas which extend from 0c 0000h-0c 7fffh. 3.8.2.3 pam2 - programmable attribute map register 2 this register controls the read, write, and shadowing attributes of the bios areas which extend from 0c 8000h -0c ffff h. device: 16 function: 0 offset: 5ah version: intel 5000p chipset, intel 5000v chipset bit attr default description 7:6 rv 00 reserved 5:4 rw 00 esienable1: 0c4000-0c7fff attribute register this field controls the steering of read and write cycles that address the bios area from 0c4000 to 0c7fff bit5 = write enable, bit4 = read enable. encoding description 00: dram disabled - all accesses are directed to esi 01: read only - all reads are serviced by dram. writes are forwarded to esi 10: write only - all writes are sent to dram. reads are serviced by esi 11: normal dram operation - all reads and writes are serviced by dram 3:2 rv 00 reserved 1:0 rw 00 loenable1: 0c0000-0c3fff attribute register this field controls the steering of read and write cycles that address the bios area from 0c0000 to 0c3fff. bit1 = write enable, bit0 = read enable encoding description 00: dram disabled - all accesses are directed to esi 01: read only - all reads are serviced by dram. writes are forwarded to esi 10: write only - all writes are sent to dram. reads are serviced by esi 11: normal dram operation - all reads and writes are serviced by dram device: 16 function: 0 offset: 5bh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7:6 rv 00 reserved 5:4 rw 00 esienable2: 0cc000-0cffff attribute register this field controls the steering of read and write cycles that address the bios area from 0cc000-0cffff. bit5 = write enable, bit4 = read enable. encoding description 00: dram disabled - all accesses are directed to esi 01: read only - all reads are serviced by dram. writes are forwarded to esi 10: write only - all writes are sent to dram. reads are serviced by esi 11: normal dram operation - all reads and writes are serviced by dram 3:2 rv 00 reserved
register description 84 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.2.4 pam3 - programmable attribute map register 3 this register controls the read, write, and shadowing attributes of the bios areas which extend from 0d 0000h - 0d 7fffh. 1:0 rw 00 loenable2: 0c8000-0cbfff attribute register this field controls the steering of read and write cycles that address the bios area from 0c8000-0cbfff. bit1 = write enable, bit0 = read enable encoding description 00: dram disabled - all accesses are directed to esi 01: read only - all reads are serviced by dram. writes are forwarded to esi 10: write only - all writes are sent to dram. reads are serviced by esi 11: normal dram operation - all reads and writes are serviced by dram device: 16 function: 0 offset: 5bh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description device: 16 function: 0 offset: 5ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7:6 rv 00 reserved 5:4 rw 00 esienable3: 0d 4000h - 0d 7fffh attribute register this field controls the steering of read and write cycles that address the bios area from 0d 4000h -0d 7fffh. bit5 = write enable, bit4 = read enable. encoding description 00: dram disabled - all accesses are directed to esi 01: read only - all reads are serviced by dram. writes are forwarded to esi 10: write only - all writes are sent to dram. reads are serviced by esi 11: normal dram operation - all reads and writes are serviced by dram 3:2 rv 00 reserved 1:0 rw 00 loenable3: 0d 0000h - 0d 3fffh attribute register this field controls the steering of read and write cycles that address the bios area from 0d 0000h -0d 3fffh. bit1 = write enable, bit0 = read enable encoding description 00: dram disabled - all accesses are directed to esi 01: read only - all reads are serviced by dram. writes are forwarded to esi 10: write only - all writes are sent to dram. reads are serviced by esi 11: normal dram operation - all reads and writes are serviced by dram
intel ? 5000x chipset memory controller hub (mch) datasheet 85 register description 3.8.2.5 pam4 - programmable attribute map registers 4 this register controls the read, write, and shadowing attributes of the bios areas which extend from 0d 8000h - 0d ffffh. 3.8.2.6 pam5 - programmable attribute map register 5 this register controls the read, write, and shadowing attributes of the bios areas which extend from 0e 0000h -0e 7fffh. device: 16 function: 0 offset: 5dh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7:6 rv 00 reserved 5:4 rw 00 esienable4: 0dc000-0dffff attribute register this field controls the steering of read and write cycles that address the bios area from 0dc000-0dffff. bit5 = write enable, bit4 = read enable. encoding description 00: dram disabled - all accesses are directed to esi 01: read only - all reads are serviced by dram. writes are forwarded to esi 10: write only - all writes are sent to dram. reads are serviced by esi 11: normal dram operation - all reads and writes are serviced by dram 3:2 rv 00 reserved 1:0 rw 00 loenable4: 0d8000-0dbfff attribute register this field controls the steering of read and write cycles that address the bios area from 0d8000-0dbfff. bit1 = write enable, bit0 = read enable encoding description 00: dram disabled - all accesses are directed to esi 01: read only - all reads are serviced by dram. writes are forwarded to esi 10: write only - all writes are sent to dram. reads are serviced by esi 11: normal dram operation - all reads and writes are serviced by dram device: 16 function: 0 offset: 5eh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7:6 rv 00 reserved 5:4 rw 00 esienable5: 0e4000-0e7fff attribute register this field controls the steering of read and write cycles that address the bios area from 0e4000-0e7fff. bit5 = write enable, bit4 = read enable. encoding description 00: dram disabled - all accesses are directed to esi 01: read only - all reads are serviced by dram. writes are forwarded to esi 10: write only - all writes are sent to dram. reads are serviced by esi 11: normal dram operation - all reads and writes are serviced by dram 3:2 rv 00 reserved
register description 86 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.2.7 pam6 - programmable attribute map register 6 this register controls the read, write, and shadowing attributes of the bios areas which extend from 0e 8000h -0e ffffh. 1:0 rw 00 loenable5: 0e0000-0e3fff attribute register this field controls the steering of read and write cycles that address the bios area from 0e0000-0e3fff. bit1 = write enable, bit0 = read enable encoding description 00: dram disabled - all accesses are directed to esi 01: read only - all reads are serviced by dram. writes are forwarded to esi 10: write only - all writes are sent to dram. reads are serviced by esi 11: normal dram operation - all reads and writes are serviced by dram device: 16 function: 0 offset: 5eh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description device: 16 function: 0 offset: 5fh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7:6 rv 00 reserved 5:4 rw 00 esienable6: 0ec000-0dffff attribute register this field controls the steering of read and write cycles that address the bios area from 0ec000-0dffff. bit5 = write enable, bit4 = read enable. encoding description 00: dram disabled - all accesses are directed to esi 01: read only - all reads are serviced by dram. writes are forwarded to esi 10: write only - all writes are sent to dram. reads are serviced by esi 11: normal dram operation - all reads and writes are serviced by dram 3:2 rv 00 reserved 1:0 rw 00 loenable6: 0e8000-0ebfff attribute register this field controls the steering of read and write cycles that address the bios area from 0e8000-0ebfff. bit1 = write enable, bit0 = read enable encoding description 00: dram disabled - all accesses are directed to esi 01: read only - all reads are serviced by dram. writes are forwarded to esi 10: write only - all writes are sent to dram. reads are serviced by esi 11: normal dram operation - all reads and writes are serviced by dram
intel ? 5000x chipset memory controller hub (mch) datasheet 87 register description 3.8.2.8 smramc - system mana gement ram control register the smramc register controls how acce sses to compatible and extended smram spaces are treated. the open, close, and lock bits function only when exsmrc.g_smrame bit is set to a 1. also, th e open bit must be reset before the lock bit is set. device: 16 function: 0 offset: 61h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7rv 0 reserved 6rwl 0 d_open: smm space open when d_open=1 and d_lck=0, the smm space dram is made visible even when smm decode is not active. this is intended to help bios initialize smm space. software should ensure that d_open=1 and d_cls=1 are not set at the same time. this register can be locked by d_lck. 5rw 0 d_cls: smm space closed when d_cls = 1 smm space dram is not accessible to data references, even if smm decode is active. code references may still access smm space dram. this will allow smm software to refe rence through smm space to update the display even when smm is mapped over the vga range. software should ensure that d_open=1 and d_cls=1 are not set at the same time. note that the d_cls bit only applies to compatible smm space. 4rwl 0 d_lck: smm space locked when d_lck is set to 1 then d_open is reset to 0 and d_lck, d_open, c_base_seg, h_smrame, g_smrame, al l lt.mseg.base, all lt.mseg.size, esmmtop, tseg_sz and t_en become read only. d_lck can be set to 1 via a normal configuration space write but can only be cleared by a full reset. the combination of d_lck and d_open provide convenience with security. the bios can use the d_open function to initialize smm space and then use d_lck to ?lock down? smm space in the fu ture so that no application software (or bios itself) can violate the integrit y of smm space, even if the program has knowledge of the d_open function. 3rv 0 reserved 2:0 ro 010 c_base_seg: compatible smm space base segment this field indicates the location of legacy smm space. smm dram is not remapped. it is simply made visible if the conditions are right to access smm space, otherwise the access is forwarded to esi/vga. since the mch supports only the smm space between a 0000h and b ffffh, this field is hardwired to 010.
register description 88 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.2.9 exsmrc - extended system management ram control register the extended smram register controls the configuration of extended smram space. the extended smram (e_smram) memory provides a write-back cacheable smram memory space that is above 1 mbyte. 3.8.2.10 exsmrtop - extended system management ram top register this register defines the location of the extended (tseg) smm range by defining the top of the tseg smm range (esmmtop). device: 16 function: 0 offset: 62h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7rwl 0 h_smrame: enable high smram controls the smm memory space location (that is, above 1 mbyte or below 1 mbyte) when g_smrame is 1 and h_sm rame is set to 1, the high smram memory space is enabled. smram a ccesses within the range feda_0000h to fedb ffffh are remapped to dram addresses within the range 000a_0000h to 000b_ffffh. once d_lck has been set, this bit becomes read only. 6ro 0 mdap: mda present since the mch does not support mda, this bit has no meaning. 5rv 0 reserved 4rv 0 reserved 3rwl 0 g_smrame: global smram enable if set to a 1, then compatible smram functions are enabled, providing 128 kb of dram accessible at the a0000h ad dress while in s mm (ads# with smm decode). to enable extended smram functi on this bit has be set to 1. refer to the section on smm for more details. once d_lck is set, this bit becomes read only. (moved from smram bit3) 2:1 rwl 00 tseg_sz: tseg size selects the size of the tseg memory block if enabled. memory from (esmmtop - tseg_sz) to esmmtop - 1 is partitioned away so that it may only be accessed by the processor interf ace and only then when the smm bit (smmem#) is set in the request packet . non-smm accesses to this memory region are sent to esi when the tseg memory block is enabled. note that once d_lck is set, these bits become read only. 00: 512kb 01: 1mb 10: 2mb 11: 4mb 0rwl 0 t_en: tseg enable enabling of smram memory for ex tended smram space only. when g_smrame =1 and tseg_en = 1, the ts eg is enabled to appear in the appropriate physical address space. note that once d_lck is set, this bit becomes read only. device: 16 function: 0 offset: 63h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7:4 rv 0h reserved
intel ? 5000x chipset memory controller hub (mch) datasheet 89 register description 3.8.2.11 exsmramc - expansion system management ram control register other address mapping registers such as bctrl (vgaen), mb ase/limit, pmbase/ limit, and so forth, are included with th e pci express registers described in this chapter. 3.8.2.12 hecbase - pci express extended configuration base address register this register defines the base address of the enhanced pci express configuration memory. 3:0 rwl 1h esmmtop: top of extended smm space (tseg) this field contains the address that corresponds to address bits 31 to 28. this field points to the top (+1) of extended smm space below 4 gb. addresses below 4 gb (a[39:32] must be 0) that fall in this range are decoded to be in the extended smm space and should be routed according to section 4.3.3 : esmmtop-tseg_sz <= address < esmmtop tseg_sz can be 512 kb, 1 mb, 2 mb, or 4 mb, depending on the value of exsmrc.tseg_sz. esmmtop is relocatable to accommodate software that wishes to configure the tseg smm space before mmio space is known. this field defaults to point to the sa me address as tolm. note that esmmtop cannot be greater than tolm otherwise the ch ipset will not function deterministically. note that once d_lck is set, this field becomes read only. device: 16 function: 2 offset: 60h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7rwc 0 e_smerr: invalid smram access this bit is set when cpu has accessed the defined memory ranges in high smm memory and extended smram (t-segment ) while not in smm space and with the d-open bit = 0. the mch will set this bit if any in-bound access from i/o device targeting smm range that gets ro uted to the esi port (master abort). refer to section 4.4.3 for details. the mch will not set this bit when processor does a cache line eviction (ewb or iwb) to smm ranges regardless of smmem# on fsb. it is software's responsibility to clear this bit. the software must write a 1 to this bit to clear it. 6:0 rv 0h reserved device: 16 function: 0 offset: 63h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description device: 16 function: 0 offset: 64h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:24 rv 0h reserved
register description 90 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.3 amb memory mapped registers the mch supports four fb-dimm channels. the mch supports up to 16 fb-dimm (each with its advanced memory buffer [amb]) on four channels. software needs to program ambpresent for each amb on the platform. there are up to eight functions per amb component with 256 b of register space per function. the mch supports memory mapped register regions for software to access individual amb configuration registers. memory mapped access to amb register regions are converted by the mch to fb-dimm ch annel command encodings subject to ambpresent register settings (see section 3.9.23.11 ). this region is relocatable by programming the ambase register. software is required to program the amr for the size of amb register regions. the size of this region is 128kb. it is mapped to each amb addressing slot in 2 kb blocks. if the corre sponding ambpresent bi t is not set, then mch will not send configuration transa ction to that amb addressing slot. to support smbus and jtag access using tr aditional pci configuration mechanism, mch provides a ?switching window? using a de dicated pci device/function and ambselect register. ambselect register can be programm ed to select an amb. bus 0, device 9, function 0 is mapped to the selected amb?s configuration registers. access to bus 0, device 9, function 0 is limited to smbus and jtag only, fsb access to this function will be mastered aborted by mch as non-existent pci function. amb register spaces are accessible through the smbus by the programming of the ambselect function_select field. this field is used select one of the amb 8 register spaces. 3.8.3.1 ambase: amb memory mapped register region base register 23:12 rw 001h hecbase: pci express exte nded configuration base this register contains the address that corresponds to bits 39 to 28 of the base address for pci express extended configuration space. configuration software will read this register to determine where the 256mb range of addresses resides for this particular host bridge . this register defaults to the same address as the default value for tolm. 11:0 rv 0h reserved device: 16 function: 0 offset: 64h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description device: 16 function: 0 offset: 48h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 63:40 rv 0h reserved 39:17 rw 007f00h ambase: this marks the 128kb memory-mapped registers region used for accessing amb registers. it can be placed as mmio region within the physical limits of the system. since the mch uses only 40-bit addressable space, hence only bits 39:17 are valid. the default base address is at: 0xfe00_0000. this field could be relocated by software. 16:0 rv 0h reserved
intel ? 5000x chipset memory controller hub (mch) datasheet 91 register description 3.8.3.2 amr - amb memory mapped registers region range register 3.8.3.3 ambselect - amb switching window select register 3.8.3.4 maxch - maximum channel number register 3.8.3.5 maxdimmperch - maximum di mm per channel number register this register controls the maximum numbe r of amb dimms per fb-dimm channel that mch supports for amb configuration register access. this register applies only to dimm modules in the fb-dimm channel, that is, those amb with ds[3:0] encoding from 0h to 7h. device: 16 function: 0 offset: 50h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:0 rw 0002_0000h ambase_region_size: the size of amb memory mapped register region in bytes. for mch, the value is 128 kb: 2 kb per amb for a total of 16 amb per channel, 32 kb per fb-dimm channel for a total of four channels. device: 16 function: 0 offset: 54h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 15:9 rv 0h reserved 8:7 rw 0h channel_select: specify the fb-dimm channel being accessed via bus 0, device 9, function 0 for sm bus and jtag only. 6:3 rw 0h amb_select: specify the amb slot being accessed via bu s 0, device 9, function 0 for sm bus and jtag only. 2:0 rw 0h function_select: specify the function being accessed via bus 0, device 9, function 0 for sm bus and jtag only. device: 16 function: 0 offset: 56h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset, bit attr default description 7:0 ro 04h maximum_number_channels: set by hardware to indicate the maximum number of fb-dimm channels that mch supports.
register description 92 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.3.6 map to amb registers in ta b l e 3 - 3 0 , each 2 kb range is mapped to individual amb registers by address translation of mch. the address of this relo catable register area is specified in the ambase register. configuration transactions targeting these ranges are converted to fb-dimm commands by the mch and sent to the fb-dimm channel subject to ambpresent register settings. the amb register?s pci function (3 bits) and offset (8 bits) are used as the offset (11 bits) from the base of each 2 kb range for the specific amb register space. device: 16 function: 0 offset: 57h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7:0 ro 04h maximum_number_dimm_per_channel: set by hardware to indicate the maximum number of fb-dimm ambs per channel that the mch supports. table 3-30. register offsets in amb memo ry mapped registers region (sheet 1 of 2) 7ffh-0h map to channel_0, amb_0 registers fffh-800h map to channel_0, amb_1 registers 17ffh-1000h map to channel_0, amb_2 registers 1fffh-1800h map to channel_0, amb_3 registers 27ffh-2000h map to channel_0, amb_4 registers 2fffh-2800h map to channel_0, amb_5 registers 37ffh-3000h map to channel_0, amb_6 registers 3fffh-3800h map to channel_0, amb_7 registers 47ffh-4000h map to channel_0, amb_8 registers 4fffh-4800h map to channel_0, amb_9 registers 57ffh-5000h map to channel_0, amb_a registers 5fffh-5800h map to channel_0, amb_b registers 67ffh-6000h map to channel_0, amb_c registers 6fffh-6800h map to channel_0, amb_d registers 77ffh-7000h map to channel_0, amb_e registers 7fffh-7800h map to channel_0, amb_f registers 87ffh-8000h map to channel_1, amb_0 registers 8fffh-8800h map to channel_1, amb_1 registers 97ffh-9000h map to channel_1, amb_2 registers 9fffh-9800h map to channel_1, amb_3 registers a7ffh-a000h map to channel_1, amb_4 registers afffh-a800h map to channel_1, amb_5 registers b7ffh-b000h map to channel_1, amb_6 registers bfffh-b800h map to channel_1, amb_7 registers c7ffh-c000h map to channel_1, amb_8 registers cfffh-c800h map to channel_1, amb_9 registers d7ffh-d000h map to channel_1, amb_a registers dfffh-d800h map to channel_1, amb_b registers e7ffh-e000h map to channel_1, amb_c registers efffh-e800h map to channel_1, amb_d registers
intel ? 5000x chipset memory controller hub (mch) datasheet 93 register description 3.8.4 interrupt redirection registers 3.8.4.1 redirctl - redirection control register this register controls the priority algo rithm of the xtpr interrupt redirection mechanism. . f7ffh-f000h map to channel_1, amb_e registers ffffh-f800h map to channel_1, amb_f registers 107ffh-10000h map to channel_2, amb_0 registers 10fffh-10800h map to channel_2, amb_1 registers 117ffh-11000h map to channel_2, amb_2 registers 11fffh-11800h map to channel_2, amb_3 registers 127ffh-12000h map to channel_2, amb_4 registers 12fffh-12800h map to channel_2, amb_5 registers 137ffh-13000h map to channel_2, amb_6 registers 13fffh-13800h map to channel_2, amb_7 registers 147ffh-14000h map to channel_2, amb_8 registers 14fffh-14800h map to channel_2, amb_9 registers 157ffh-15000h map to channel_2, amb_a registers 15fffh-15800h map to channel_2, amb_b registers 167ffh-16000h map to channel_2, amb_c registers 16fffh-16800h map to channel_2, amb_d registers 177ffh-17000h map to channel_2, amb_e registers 17fffh-17800h map to channel_2, amb_f registers 187ffh-18000h map to channel_3, amb_0 registers 18fffh-18800h map to channel_3, amb_1 registers 197ffh-19000h map to channel_3, amb_2 registers 19fffh-19800h map to channel_3, amb_3 registers 1a7ffh-1a000h map to channel_3, amb_4 registers 1afffh-1a800h map to channel_3, amb_5 registers 1b7ffh-1b000h map to channel_3, amb_6 registers 1bfffh-1b800h map to channel_3, amb_7 registers 1c7ffh-1c000h map to channel_3, amb_8 registers 1cfffh-1c800h map to channel_3, amb_9 registers 1d7ffh-1d000h map to channel_3, amb_a registers 1dfffh-1d800h map to channel_3, amb_b registers 1e7ffh-1e000h map to channel_3, amb_c registers 1efffh-1e800h map to channel_3, amb_d registers 1f7ffh-1f000h map to channel_3, amb_e registers 1ffffh-1f800h map to channel_3, amb_f registers table 3-30. register offsets in amb memory mapped registers region (sheet 2 of 2) device: 16 function: 0 offset: 6eh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 15:14 rv 0 reserved 13 rv 0 reserved 12 rv 0 reserved
register description 94 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.4.2 redirbuckets - redirection bucket number register this register allows software to read the current hardware bucket number assigned to each xtpr register. . 3.8.5 boot and reset registers 3.8.5.1 syre - system reset register this register controls mch reset behavior. any resets produced by a write to this register must be delayed until the configur ation write is completed on the initiating interface (pci express, esi, processor bus, smbus, jtag). 11:8 rw 0h bucket2: first priority number not in bucket0, bucket1, or bucket2. must be programmed with a larger va lue than bucket1. a suggested value is ch. 7:4 rw 0h bucket1: first priority numbe r not in bucket0 or bucket1. must be programmed with a larger value than bucket0. a suggested value is 8h. 3:0 rw 0h bucket0: first priority number not in bucket0 . a suggested value is 0h. device: 16 function: 0 offset: 6eh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description device: 16 function: 0 offset: 68h version: intel 5000p chipset, intel 5000v chipset bit attr default description 31:30 ro 0 bucket15: redirection bucket number for xtpr[15]. 29:28 ro 0 bucket14: redirection bucket number for xtpr[14]. 27:26 ro 0 bucket13: redirection bucket number for xtpr[13]. 25:24 ro 0 bucket12: redirection bucket number for xtpr[12]. 23:22 ro 0 bucket11: redirection bucket number for xtpr[11]. 21:20 ro 0 bucket10: redirection bucket number for xtpr[10]. 19:18 ro 0 bucket9: redirection bucket number for xtpr[9]. 17:16 ro 0 bucket8: redirection bucket number for xtpr[8]. 15:14 ro 0 bucket7: redirection bucket number for xtpr[7]. 13:12 ro 0 bucket6: redirection bucket number for xtpr[6]. 11:10 ro 0 bucket5: redirection bucket number for xtpr[5]. 9:8 ro 0 bucket4: redirection bucket number for xtpr[4]. 7:6 ro 0 bucket3: redirection bucket number for xtpr[3]. 5:4 ro 0 bucket2: redirection bucket number for xtpr[2]. 3:2 ro 0 bucket1: redirection bucket number for xtpr[1]. 1:0 ro 0 bucket0: redirection bucket number for xtpr[0].
intel ? 5000x chipset memory controller hub (mch) datasheet 95 register description there is no ?soft reset? bit in this register . that function is invoked through the esi. there are no core:fbd gear ratio definitions in this register. those are located in the ddrfrq register. 3.8.5.2 cpurstcaptmr: cpu reset done cap latency timer this register implements the cap latency method for the cpu_rst_done/ cpu_rst_done_ack using a 12-bit variable timer. device: 16 function: 0 offset: 40h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 15 rw 0 savcfg: preserve configuration when this bit is set, mch configuration register contents (except for this bit) are not cleared by hard reset. as this bit is cleared by reset, software must set it after each reset if this behavior is desired for the next reset. if this bit is set, bofl will not be cleared by re set. software should use the boot flag reset bit to re-enable the bofl mechanism. 14 rw 0 cpurst: processor reset if set, the mch will assert processor reset# on both buses as soon as the mch has no pending transactions. the chipset will then deassert reset# following the timing rules described in the reset chapter. the mch does not have any mechanism to drain transactions before effecting the cpu reset#. it is the responsibilit y of software to ensure that the system is quiet before sending the configuration write (last command) to set this field in the mch in order to drive the cpu reset# signal. any violation of this usage pattern would render the system unstable and potentially catastrophic. 13 rv 0 cpubist: processor built-in-self-test if set, a[3]# is asserted during power-on-configuration (poc), and the processor will run bist before en gaging processor bus protocol. 12:11 rv 0 reserved1 10 rost 0 s3: s3 sleep state the mch sets this bit when it sends an ack-s3 message to the esi port. the mch clears this bit after it has pl aced appropriate fb-dimm channels into the fb-dimm.calibrate state in response to deassertion of the reseti# signal. 9rw 0 ror: processor reset on refresh if set, the mch will assert processor reset# on both busses when a refresh cycle completes. 8rwst 0 bnr_indp_binit_mode: bnr independent of binit mode 0: the chipset associates bnr with bi nit and for cpus that do not follow the ?bnr independent of binit? feature set. 1: enables the chipset to use the ?bnr independent of binit? feature set. i.e no dependency is required between bnr and binit. refer to the bnr#, binit# sampling ru les in the intel? pentium? 4 and intel? xeon? processor external hardware specification, rev 2.5, ref#14035 7:0 rv 0h reserved
register description 96 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.5.3 poc - power-on configuration register contrary to its name, this register defines configuration values driven at reset. at power-on, no bits in this register are active as pwrgood clears them all. this register only activates configuration on subsequent resets. the mch drives the contents of this register on a[35:4]# whenever it asserts processor reset#. these values are driven during processor reset# assertion, and for two host clocks past the trailing edge of processor reset#. this register is sticky through reset; that is, the contents of the register remain unchanged during and following a hard reset. this allows system configuration software to modify the default values and reset the system to pass those values to all host bus devices. the poc bits do not affect mch oper ation except for driving a[35:4]#. read after write to poc register will read updated value but the architectural behavior will not be affected until hard-reset deassertion. a warm reset (cpu reset) will not cause the contents of the poc register to be altered. there are other power-on configuration bits in the syre register. device: 16 function: 0 offset: 42h bit attr default description 15:12 rv 0h reserved 11:0 rwst 7ffh dcrt: esi cpu reset done ack determinism timer this field provides the determinism timer threshold for the intel 5000p chipset mch for handling the cpu_ reset_done/cpu_reset_done_ack message before deasserting the cpu_reset#. it uses this 12-bit counter to schedule the cpu_reset_done message on the dmi and then waits for the cpu_reset_done_ack message to co me back and waits for the timer expiry before deasserting cpu_reset#. cap_latency = max(cpu_rst_done_ack_round trip_latency, dcrt). it is expected that the dcrt field is set larger than the expected round trip latency. this provides the nece ssary leeway for absorbing clock synchronization, jitter, deskew and other variations that will affect the determinism on the dmi port. hence the data is always sent back only after the expiry of the dcrt field at the heartbeat boundary. it is sticky through reset to permit to allow different types of bios flows that may require a hard reset of the intel 5000p chipset mch. maximum value is 4095 core clocks a default of 2047 clocks (7ffh) is used. device: 16 function: 0 offset: 44h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:28 rv 0h reserved 27 rwst 0 mtdis: disable multi-threading if set, a[31]# is asserted, and the processor will disable multi-threading. 26:12 rv 0h reserved
intel ? 5000x chipset memory controller hub (mch) datasheet 97 register description 3.8.5.4 spad[3:0] - scratch pad registers these scratch pad registers each provide 32 read/writable bits that can be used by software. they are also aliased to fixed memory addresses. 3.8.5.5 spads[3:0] - sticky scratch pad these sticky scratch pad registers each provide 32 read/writable bits that can be used by software. they are also aliased to fixed memory addresses. 11 rwst 1 buspark: request bus parking disable if set, a[15]# is asserted and the processor may not park on the system bus. default is to disable busparking 10:0 rv 0h reserved device: 16 function: 0 offset: 44h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description device: 16 function: 0 offset: dch, d8h, d4h, d0h version: intel 5000p chipset, intel 5000v chipset bit attr default description 31:0 rw 00000000h scratch pad value. these bits have no effect on the hardware. device: 16 function: 0 offset: ech, e8h, e4h, e0h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:0 rwst 00000000h scratch pad value. these sticky bits have no effect on the hardware.
register description 98 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.5.6 bofl[3:0] - boot flag register these registers can be used to select the system boot strap processor or for other cross processor communication purposes. when this register is read, the contents of the register is cleared. therefore, a processor that reads a non-zero value owns the semaphore. any value can be written to this register at any time. an example of usage would be for all processors to read the register. the first one that gets a non-zero value owns the semaphore. since the read clears the value of the register, all other processors will see a zero value and will spin until they receive further notification. after the winning processor is done, it writes a non-zero value of its choice into the register, arming it for subsequent uses. these registers are also aliased to fixed memory i/o addresses. 3.8.6 control and in terrupt registers 3.8.6.1 procenable: processor enable global control the two fsben bits are used to enable or disable frontside bus arbitration. when frontside bus arbitration is disabled the processor is effectively disabled. 3.8.6.2 fsbs[1:0] - processor bus status register this register holds status from the processor busses. device: 16 function: 0 offset: c0h, c4h, c8h, cch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:0 rcw a5a5a5a5h semaval: semaphore value can be written to any value. value is cleared when there is a read. device: 16 function: 0 offset: f0h bit attr default description 31:5 rv 3fah reserved. 4:3 rwst 11 fsben: fsb1 and fsb0 enable the field is defined as the following: 00: reserved 01: fsb1 is disabled. fsb0 is enabled. 10: fsb1 is enabled. fsb0 is disabled. 11: fsb1 is enabled. fsb0 is enabled. (default) hard-reset is needed after changing value in this register. 2rwst 0 sfbypass: snoop filter bypass 0: sf is enabled 1: sf is disabled note: the output of the fuse ?sf chop ? is gated appropriately with this register field viz. sfbypass for further internal decoding by intel 5000x chipset mch. the fuse has overriding effect. 1:0 rv 0h reserved.
intel ? 5000x chipset memory controller hub (mch) datasheet 99 register description 3.8.6.3 xtpr[7:0] - external task priority register these registers control redirectable interrupt priority for xapic agents connected to the mch. up to four agents on each bus are su pported. these agents may be two dual core processors each with two threads or four single core processors. the xapic architecture provides for lowest priority delivery through interrupt redirection by the mch. if the redirectable ?hint bit? is set in the xapic message, the chipset may redirect the interrupt to another agent. redirection of interrupts can be applied to both i/o interrupts and ipis. each register contains the following fields: 1. agent priority (task priority) 2. apic enable bit (tpr enable) 3. logical apic id (logid) 4. processor physical apic id (physid) the xtpr registers are modified by a front side bus xtpr_update transaction. in addition, the xtpr registers can be modified by software. these registers are used for lowest priority delivery through interrupt redirection by the chipset. device: 16 function: 0 offset: 7ch, 74h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:2 rv 0h reserved. 1ro 0 2socket: 2 sockets present on this fsb set when intel 5000p chipset mch has seen ab[22] asserted, indicating there are more than 1 processors present on this fsb. 0ro 0 2core: 2 cores present set when intel 5000p chipset mch has seen ab[30] asserted, indicating there is more than 1 core in a processor. note: mixing single core wi th dual-core processors w ill be recognized as dual- core processor on this fsb. table 3-31. xtpr index index value 3 0 for fsb0, 1 for fsb1 2ab[29] 1 ab[30] or ab[22] 0ab[21]
register description 100 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.7 pci express device configuration registers this section describes the registers associated with the pci express interface. the pci express register structure is expose d to the operating system and requires a separate device per port. ports 2-7 will be assigned devices 2 through 7 while port 0 is the esi interconnect to the intel 631xesb/632xesb i/o controller hub. the pci express ports determine at reset the maximum width of the devices to which they are connected through link training. all ports will be made visible to os even if unconnected. if ports are combined to form la rger widths (for example, x8 or x16 from a x4 link), then the unused ports will master abort (reads return all ones, writes dropped) any accesses to it. note that configuration accesses to the unconnected port will still be allowed to permit device remapping, hot-plug and so forth. device: 16 function: 0 offset: bch, b8h, b4h, b0h, ach, a8h, a4h, a0h, 9ch, 98h, 94h, 90h, 8ch, 88h, 84h, 80h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31 if (xtpr0) {rw} else {rv} endif 0 cluster: global cluster mode (xtpr[0] only) used in interrupt redirection for lowest priority delivery. updated by every xtpr_update transaction on either bus (aa[3]). 0: flat note: cluster mode not supported 30:24 rv 00h reserved. 23 rw 0 tpren: tpr enable this bit reflects the value of ab[31]#. when ab[31]# is asserted, the value of this bit will be 0. 22:20 rv 0h reserved. 19:16 rw 0h priority: task priority the processor with the lowest enabled value will be assigned the redirectable interrupt. this field is updated with ab[27:24] of the xtpr_update transaction. 15:8 rw 0h physid: physical apic id the physical id of the apic agent associated with the xtpr entry. this field is updated with aa[19:12] of the xtpr_update transaction. 7:0 rw 0h logid: logical apic id the logical id of the apic agent associated with th e xtpr entry. this field is updated with aa[11:4] of the xtpr_update transaction. table 3-32. when will an inte l 5000x chipset pci expre ss* device be accessible? pci express port device x16 registers may be accessed if: 77high performance graphics port 66 55 4 4 port 4 is connected to x16 device 33possible combination port3 is connected to a 4x device 2 2 port2 is connected to a x4 or x8 device 00 esi - not combinable port0 is connected to a x4 esb2 port through esi and cannot be combined with any other port
intel ? 5000x chipset memory controller hub (mch) datasheet 101 register description figure 3-4 illustrates how each pci express port?s configuration space appears to software. each pci express port?s configuration space has four regions: ? standard pci header - this region closely resembles a standard pci-to-pci bridge header. ? pci device dependent region - the region is also part of standard pci configuration space and contains the pci capability structures. for the intel 5000p chipset mch, the supported capabilities are: ? message signalled interrupts ?hot-plug ? pci express capability ? pci express extended configuration space - this space is an enhancement beyond standard pci and only accessible with pci express aware software. the mch supports the enhanced error signalling capability. ? capability working register sets - these ranges are indirectly accessed through data and select registers in the capability structures. for the mch, working register sets exist for the standard hot-plug controller and power management capabilities.
register description 102 intel ? 5000x chipset memory controller hub (mch) datasheet figure 3-3 shows the configuration register of fset addresses for each of the pci express ports as defined in the pci express base specification , revision 1.0a. it is also compatible with the standard pci 2.3 capabi lity structure and comprises of a linked list where each capability has a pointer to the next capability in the list. for pci express extended capabilities, the first structure is required to start at 0x100 offset. 3.8.8 pci express header the following registers define the standa rd pci 2.3 compatible and extended pci express configuration space for each of th e pci express x4 links in the mch. unless otherwise specified, the registers are enumerat ed as a vector [2:7] mapping to each of the six pci express ports uniquely while the esi port is referred by index 0. figure 3-4. pci express configuration space 0x00 0x40 0x100 0xfff pci-express advanced error reporting msi capability pci-express capability p2p cap_ptr extended configuration space pci device dependent pci header intel? 5000p chipset advanced error reporting 0x140 pm capability r e m a i n d e r o f e x t e n d e d p c i - e x p r e s s c o n f i g u r a t i o n s p a c e
intel ? 5000x chipset memory controller hub (mch) datasheet 103 register description 3.8.8.1 pcicmd[7:2, 0]- command register this register defines the pci 2.3 compatible command register values applicable to pci express space. device: 0, 2-3 function: 0 offset: 04h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 04h version: intel 5000z chipset device: 4-7 function: 0 offset: 04h version: intel 5000p chipset bit attr default description 15:11 rv 0h reserved. (by pci sig) 10 rw 0 intxdisable: interrupt disable controls the ability of the pci express port to generate intx messages. this bit does not affect the ability of the gnb to route interrupt messages received at the pci express port. howeve r, this bit controls the generation of legacy interrupts to the dmi for pci express errors detected internally in this port (for example, malformed tl p, crc error, completion time out, and so forth) or when receiving root port error messages or interrupts due to hp/pm events generated in legacy mo de within the intel 5000p chipset mch. refer to the intp register in section 3.8.8.27, ?intp[7:2,0] - interrupt pin register? on page 119 for interrupt routing to dmi. 1: legacy interrupt mode is disabled 0: legacy interrupt mode is enabled 9ro 0 fb2b: fast back-to-back enable not applicable to pci express and is hardwired to 0 8rw 0 serre: serr message enable his field handles the reporting of fata l and non-fatal errors by enabling the error pins err[2:0]. 1: th e gnb is enabled to send fatal/non-fatal errors. 0: the gnb is disabled from generating fatal/non-fatal errors. the errors are also enabled by the pexde vctrl register in section 3.8.11.4 . in addition, for type 1 configuration space header devices, for example, virtual p2p bridge), this bit, wh en set, enables transmission of err_nonfatal and err_fatal error messages 1 forwarded from the pci express interface. this bit does not affect the transmission of forwarded err_cor messages. refer to the intel 5000p chipset mch ras error model. 7ro 0 idselwcc: idsel stepping/wait cycle control not applicable to pci express. hardwired to 0. 6rw 0 perre: parity error response enable when set, this field enables parity checking. 5ro 0 vgapse: vga palette snoop enable not applicable to pci express. hardwired to 0. 4ro 0 mwien: memory write and invalidate enable not applicable to pci express. hardwired to 0. 3ro 0 sce: special cycle enable not applicable to pci express. hardwired to 0.
register description 104 intel ? 5000x chipset memory controller hub (mch) datasheet 2rw 0 bme: bus master enable controls the ability of the pci express port to forward memory or i/o transactions. 1: enables the pci express port to successfully complete the memory or i/ o read/write requests. 0: the bus master is disabled. the mch will treat upstream memory writes/ reads, i/o writes/reads, and msis as illegal cycles and re turn unsupported request status (equivalent to master abort) in pci express when the bme is disabled, the mch will treat upstream memory writes/ reads, i/o writes/reads, and msis as illegal cycles and re turn unsupported request status (equivalent to master abort) in pci express requests other than inbound memory or i/o (for example, configuration, outbound) are not controlled by this bit. the bme is typically used by the system software for operations such as hot-plug, device configuration. when the cpureset# signal is asserted during a power good or hard reset and after the dmi completes its trai ning, the lpc device in the intel 631xesb/632xesb i/o controller hub (o r other nic/sio4 cards could potentially send inboun d requests even before the cpureset# is deassserted. this corner case is handled by the bme filtration in the intel 5000p chipset mch?s pci express port using the above rules since bme is reset. however, in general, it is illegal for a an i/o device to issue inbound requests until the cpureset# has been deasserted to prevent any possible malfunction in the intel 5000p chipset mch logic. 1if (port 7-2) {rw} elseif (port 0) {ro} endif 0 mse: memory space enable controls the bridge?s response as a target to memory accesses on the primary interface that address a device that resides behind the bridge in both the non-prefetchable and prefetchable memory ranges (high/low) or targets a memory-mapped location within the bridge itself 1: enables the memory and prefet chable memory address ranges (mmio) defined in the mbase/mlim, pmbase/pmlim, pmbu/pmlu registers. 0: disables the entire memory space seen by the pci express port on the primary side ( mch ). requests will then be subtractively claimed by intel 631xesb/632xesb i/o controller hub. for port 0, this bit is hardwired to 0 since the esi is not a p2p bridge. 0if (port 7-2) {rw} elseif (port 0) {ro} endif 0 ioae: access enable 1: enables the i/o address range defined in the iobase and iolim registers. 0: disables the entire i/o space seen by the pci express port on the primary. requests will be then be s ubtractively claimed by intel 631xesb/ 632xesb i/o controller hub. for port 0, this bit is hardwired to 0 since the esi is not a p2p bridge. notes: 1. in addition, bcctrl.bcserre also gates the transm ission of err_fatal, non_fatal and err_cor messages received from the pci express interface. see section 3.8.8.28 . device: 0, 2-3 function: 0 offset: 04h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 04h version: intel 5000z chipset device: 4-7 function: 0 offset: 04h version: intel 5000p chipset bit attr default description
intel ? 5000x chipset memory controller hub (mch) datasheet 105 register description 3.8.8.2 pcists[7:2, 0] - status register the pcists is a 16-bit status register that reports the occurrence of error conditions associated with the primary side of the ?virtual? pci-pci bridge embedded in the selected pci express cluster of the mch. device: 0, 2-3 function: 0 offset: 06h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 06h version: intel 5000z chipset device: 4-7 function: 0 offset: 06h version: intel 5000p chipset bit attr default description 15 rwc 0 dpe: detected parity error this bit is set when the pci express port receives an u ncorrectable data error or address/control parity errors regardless of the parity error re sponse enable bit (perre). this applies only to parity errors that target the pci express port interface (inbound/outbound direction). the detected parity error maps to b1, f6, m2 and m4 (uncorrectab le data error from fsb, memory or internal sources) of the intel 5000p chipset mch. 14 rwc 0 sse: signaled system error 1: the pci express port generated internal fatal/non fatal errors (io0- io17) through the err[2:0] pins with se rre bit enabled. software clears this bit by writing a ?1? to it. 0: no internal pci express port errors are signaled. 13 rwc 0 rma: received master abort t his bit is set when a requestor (primary side for type 1 header configuration space header device) receives a completion with unsupported request completion status. 1: assert this rma bit when the prim ary side performs operations for an unsupported transaction. these apply to inbound configs, i/o accesses, locks, bogus memory reads and any other request that is master aborted internally. these are terminated on the pci express link with a ur completion status, but only if a completion is required. software clears this bit by writing a 1 to it. pexdevsts.urd is set and uncerrsts [20].io2err is set in addition. 0: no master abort is generated 12 rwc 0 rta: received target abort this bit is set when a requestor (primary side for type 1 header configuration space header device) receives a completion with completer abort completion status. for example, for supported requests that cannot be completed because of address decoding problems or other errors. these are terminated on the pci express link with a ca completion status, but only if a completion is required. software clears this bit by writing a 1 to it. 11 ro 0 sta: signaled target abort target abort does not exist on the primary side of the pci express port. hardwired to 0. 10:9 ro 0h devselt: devsel# timing not applicable to pci express. hardwired to 0 .
register description 106 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.8.3 cls[7:2, 0] - cache line size this register contains the cache line size and is set by bios/operating system. it does not affect the pci express port functionality in the mch. 8rwc 0 mdperr: master data parity error this bit is set by the pci express port if the parity error response enable bit (perre) is set and it receives error b1, f2, f6, m2 and m4 (u ncorrectable data error or address/control parity errors or an internal failure). if the parity error enable bit (perre) is cl eared, this bit is never set. 7ro 0 fb2b: fast back-to-back not applicable to pci express. hardwired to 0 . 6rv 0 reserved. (by pci sig) 5ro 0 66mhzcap: 66 mhz capable. not applicable to pci express. hardwired to 0 . 4ro 1 capl: capabilities list this bit indicates the presence of pci expr ess capabilities list structure in the pci express port. hardwired to 1. (mandatory) 3ro 0 intxstat: intx status indicates that an intx interrupt message is pending internally in the pci express port. the intx status bit should be rescinded when all the relevant events via ras errors/hp/pm internal to the port that requires legacy interrupts are cleared by software. 2:0 rv 0h reserved. (by pci sig) device: 0, 2-3 function: 0 offset: 06h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 06h version: intel 5000z chipset device: 4-7 function: 0 offset: 06h version: intel 5000p chipset bit attr default description
intel ? 5000x chipset memory controller hub (mch) datasheet 107 register description 3.8.8.4 pri_lt[7:2, 0] - primary latency timer this register denotes the maximum time slice for a burst transaction in legacy pci 2.3 on the primary interface. it does not affect/influence pci express functionality. 3.8.8.5 bist[7:2,0] - built-in self test this register is used for reporting control and status information of bist checks within a pci express port. it is not suppor ted in the intel 5000p chipset mch. device: 0, 2-3, 0 function: 0 offset: 0ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 0ch version: intel 5000z chipset device: 4-7 function: 0 offset: 0ch version: intel 5000p chipset bit attr default description 7:0 rw 00h cls: cache line size this is an 8-bit value that indicates the size of the cache line and is specified in dwords. it does not affect the mch . device: 0, 2-3 function: 0 offset: 0dh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 0dh version: intel 5000z chipset device: 4-7 function: 0 offset: 0dh version: intel 5000p chipset bit attr default description 7:0 ro 00h prim_lat_timer: primary latency timer not applicable to pci express. hardwired to 00h.
register description 108 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.8.6 bar0[7:2,0] - base address register 0 base address registers are used for mapping internal registers to an mmio or i/o space. it does not affect the mch. the base address register 0 is not supported/defined in the pci express port of the mch. 3.8.8.7 bar1[7:2,0] - base address register 1 the base address register 1 is not supported/defined in the mch. 3.8.8.8 exp_rom[0]: expansion rom registers the esi port (device 0, function 0) does not implement any base address registers in the intel 5000p chipset mch from offset 10h to 24h. similarly no expansion rom base address register is defined in offset 30h. also no cardbus cis pointer is defined in offset 28h. the min_gnt (offset 3eh) and max_lat (3fh) registers are also not implemented as they are not app licable to the esi interface. 3.8.8.9 pbusn[7:2] - primary bus number this register identifies the bus number on the on the primary side (mch) of the pci express port. device: 0, 3-2 function: 0 offset: 0fh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 0fh version: intel 5000z chipset device: 7-4 function: 0 offset: 0fh version: intel 5000p chipset bit attr default description 7:0 ro 00h bist_tst: bist tests not supported. hardwired to 00h
intel ? 5000x chipset memory controller hub (mch) datasheet 109 register description 3.8.8.10 sbusn[7:2] - secondary bus number this register identifies the bus number assigned to the secondary side (pci express) of the ?virtual? pci-pci bridge. this number is programmed by the pci configuration software to allow mapping of configuration cycles to devices connected to pci express. device: 2-3 function: 0 offset: 18h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 18h version: intel 5000z chipset device: 4-7 function: 0 offset: 18h version: intel 5000p chipset bit attr default description 7:0 ro 00h pbubsnum: primary bus number configuration software typically programs this field with the number of the bus on the primary side of the bridge. since the pci express virtual pci-pci bridge is an internal device and its primary bus is consistently 0, these bits are read only and are hardwired to 0. device:2-3 function: 0 offset: 19h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 19h version: intel 5000z chipset device: 4-7 function: 0 offset: 19h version: intel 5000p chipset bit attr default description 7:0 rw 00h secbusnum: secondary bus number this field is programmed by configuration software with the lowest bus number of the busses connected to pci express. since both bus 0, device 1 and the pci to pci bridge on the other end are considered by configuration software to be pci-pci bridges, this bus number will consistently correspond to the bus number assigned to the pci express port.
register description 110 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.8.11 subusn[7:2] - subordinate bus number this register identifies the subordinate bus (if any) that resides at the level below the secondary pci express interface. this number is programmed by the pci configuration software to allow mapping of configuration cycles to devices subordinate to the secondary pci express port. 3.8.8.12 sec_lt[7:2] - secondary latency timer this register denotes the maximum time slic e for a burst transaction in legacy pci 2.3 on the secondary interface. it does not affect/influence pci express functionality. 3.8.8.13 iobase[7:2] - i/o base register the i/o base and i/o limit registers (see section 3.8.8.14 ) define an address range that is used by the pci express port to determine when to forward i/o transactions from one interface to the other using the following formula: io_base <= a[15:12]<=io_limit device: 2-3 function: 0 offset: 1ah version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 1ah version: intel 5000z chipset device: 4-7 function: 0 offset: 1ah version: intel 5000p chipset bit attr default description 7:0 rw 00h subbusnum: subordinate bus number this register is programmed by configur ation software with the number of the highest subordinate bus that is behind the pci express port. device: 2-3 function: 0 offset: 1bh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 1bh version: intel 5000z chipset device: 4-7 function: 0 offset: 1bh version: intel 5000p chipset bit attr default description 7:0 ro 00h slat_tmr: secondary latency timer not applicable to pci express. hardwired to 00h.
intel ? 5000x chipset memory controller hub (mch) datasheet 111 register description only the upper 4 bits are programmable. for the purpose of address decode, address bits a[11:0] are treated as 0. the bottom of the defined i/o address range will be aligned to a 4 kb boundary while the top of th e region specified by io_limit will be one less than a 4 kb multiple. refer to section 4.5.1 and section 4.5.3 in the intel 5000p chipset platform specification. 3.8.8.14 iolim[7:2] - i/o limit register the i/o base and i/o limit registers define an address range that is used by the pci express bridge to determine when to forward i/o transactions from one interface to the other using the following formula: io_base <= a[15:12] <=io_limit only the upper 4 bits of this register ar e programmable. for the purpose of address decode, address bits a[11:0] of the i/o limit register is treated as fffh. device: 2-3 function: 0 offset: 1ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 1ch version: intel 5000z chipset device: 4-7 function: 0 offset: 1ch version: intel 5000p chipset bit attr default description 7:4 rw 0h iobase: i/o base address corresponds to a[15:12] of the i/o addresses at the pci express port. 3:0 ro 0h iocap: i/o address capability 0h ? 16 bit i/o addressing, (supported) 1h ? 32 bit i/o addressing, others - reserved. the mch does not support 32 bit addressing, so these bits are hardwired to 0. device: 2-3 function: 0 offset: 1dh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 1dh version: intel 5000z chipset device: 4-7 function: 0 offset: 1dh version: intel 5000p chipset bit attr default description 7:4 rw 0h iolimit: i/o address limit corresponds to a[15:12] of the i/o addresses at the pci express port.
register description 112 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.8.15 secsts[7:2] - secondary status secsts is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (that is, pci express side) of the ?virtual? pci-pci bridge embedded within mch. k 3:0 ro 0h iolcap: i/o address limit capability 0h ? 16 bit i/o addressing, (supported) 1h ? 32 bit i/o addressing, others - reserved. the mch does not support 32 bit i/o addressing, so these bits are hardwired to 0. device: 2-3 function: 0 offset: 1dh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 1dh version: intel 5000z chipset device: 4-7 function: 0 offset: 1dh version: intel 5000p chipset bit attr default description device: 2-3 function: 0 offset: 1eh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 1eh version: intel 5000z chipset device: 4-7 function: 0 offset: 1eh version: intel 5000p chipset bit attr default description 15 rwc 0 sdpe: detected parity error this bit is set by the intel 5000p chipset mch whenever it receives a poisoned tlp in the pci express port regardless of the state the parity error response bit ( in the bctrl.prspen register) . bctrl.prspen register) . this corresponds to io4 as defined in table 5-31, ?intel 5000x chipset error list? on page 388 . 14 rwc 0 srse: received system error this bit is set by the mch when it receives a err_fatal or err_nonfatal message. section 3.8.8.28 . (note that bctrl.bcserre is not a gating item for the recording of this error on the secondary side). 13 rwc 0 s rmas: received master abort status this bit is set when the pci express port receives a completion with ?unsupported request completion? status.
intel ? 5000x chipset memory controller hub (mch) datasheet 113 register description 12 rwc 0 srtas: received target abort status this bit is set when the pci expre ss port receives a completion with ?completer abort? status. 11 rwc 0 sstas: signaled target abort this bit is set when the pci express por t completes a request with ?completer abort? status when the pexsts.rta is set since the mch acts as a virtual pci bridge and passes the completion abort from the primary to the secondary side. note however that the mch will not set the sstas field directly on the secondary side since all r equests are passed upstream through the primary side to the internal core logic for decoding. 10:9 ro 00 sdevt: devsel# timing not applicable to pci express. hardwired to 0 8rwc 0 smdperr: master data parity error this bit is set by the pci express port on the secondary side (pci express link) if the parity error response enable bit (prspen) in the section 3.8.8.28 is set and either of the following two conditions occurs: ?the pci express port receives a completion marked poisoned ?the pci express port poisons a write request if the parity error response enable bit is cleared, this bit is never set. refer to ta b l e 3 - 3 3 for details on the data parity error handling matrix in the intel 5000p chipset mch. 7ro 0 sfb2btc: fast back-to-back transactions capable not applicable to pci express. hardwired to 0. 6rv 0 reserved. (by pci sig) 5ro 0 s66mhcap: 66 mhz capability not applicable to pci express. hardwired to 0. 4:0 rv 0h reserved. (by pci sig) table 3-33. intel 5000p chipset mch pcists and secsts master/data parity error ras handling register name ob post ob compl in post ib compl pcists[15].dpe 1 yes yes no no pcists[8].mdperr no yes no no secsts[15].sdpe no no yes yes secsts[8].smdperr no no no yes device: 2-3 function: 0 offset: 1eh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 1eh version: intel 5000z chipset device: 4-7 function: 0 offset: 1eh version: intel 5000p chipset bit attr default description
register description 114 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.8.16 mbase[7:2] - memory base the memory base and memory limit registers define a memory mapped i/o non- prefetchable address range (32-bit addresses) and the mch directs accesses in this range to the pci express port based on the following formula: memory_base <= a[31:20] <= memory_limit the upper 12 bits of both the memory base and memory limit registers are read/write and corresponds to the upper 12 address bits, ad[31:20], of 32-bit addresses. for the purpose of address decoding, the bridge assumes that the lower 20 address bits, ad[19:0], of the memory base address are zero. similarly, the bridge assumes that the lower 20 address bits, ad[19:0], of the memo ry limit address (not implemented in the memory limit register) are fffffh. thus, the bottom of the defined memory address range will be aligned to a 1 mb boundary an d the top of the defined memory address range will be one less than a 1 mb boundary. refer to section 4.3.9 , section 4.4.2 and section 4.4.3 in the intel 5000p chipset programmer?s guide for further details on address mapping. 3.8.8.17 mlim[7:2]: memory limit this register controls the processor to pci express non-prefetchable memory access routing based on the following formula as described above: memory_base <= a[31:20] <= memory_limit the upper 12 bits of the register are re ad/write and correspond to the upper 12 address bits a[31:20] of the 32 bit address. the bottom 4 bits of this register are read- only and return zeroes when read. this regist er must be initialized by the configuration software. for the purpose of address decode address bits a[19:0] are assumed to be fffffh. notes: 1. in general, the dpe field is the superset of th e mdperr from a virtual pci-pci bridge perspective but there may be cases where a pcists[8].mdperr may not be logged in the pcists[15].dpe field in the intel 5000p chipset mch on the primary side. device: 2-3 function: 0 offset: 20h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 20h version: intel 5000z chipset device: 4-7 function: 0 offset: 20h version: intel 5000p chipset bit attr default description 15:4 rw 0h mbase: memory base address corresponds to a[31:20] of the memory address on the pci express port. 3:0 ro 0h reserved. (by pci sig)
intel ? 5000x chipset memory controller hub (mch) datasheet 115 register description memory range covered by mbase and mlim registers, are used to map non- prefetchable pci express address ranges (typically where control/status memory- mapped i/o data structures reside) and pmbase and pmlim are used to map prefetchable address ranges. this segreg ation allows application of uswc space attribute to be performed in a true plug-a nd-play manner to the prefetchable address range for improved pci express memory access performance. note also that configuration software is responsible for programming all address range registers such as mir, mlim, mbase, io lim, iobase, pmbase, pmlim, pmbu, pmlu (coherent, mmio, prefetchable, non-prefetch able, i/o) with the values that provide exclusive address ranges, that is, prevent overlap with each other and/or with the ranges covered with the main memory. there is no provision in the mch hardware to enforce prevention of overlap and operations of the system in the case of overlap are not guaranteed. 3.8.8.18 pmbase[7:2] - prefetchable memory base the prefetchable memory base and memory limit registers define a memory mapped i/o prefetchable address range (32-bit addr esses) which is used by the pci express bridge to determine when to forwar d memory transactions based on the following formula: prefetch_memory_base <= a[31:20 ] <= prefetch_memory_limit the upper 12 bits of both the prefetchable memory base and memory limit registers are read/write and corresponds to the upper 12 address bits, a[31:20], of 32-bit addresses. for the purpose of address decodi ng, the bridge assumes that the lower 20 address bits, a[19:0], of the memory base address are zero. similarly, the bridge assumes that the lower 20 address bits, a[ 19:0], of the memory limit address (not implemented in the memory limit register) are f ffffh. thus, the bottom of the defined memory address range will be aligne d to a 1 mb boundary and the top of the defined memory address range will be one less than a 1 mb boundary . device: 2-3 function: 0 offset: 22h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 22h version: intel 5000z chipset device: 4-7 function: 0 offset: 22h version: intel 5000p chipset bit attr default description 15:4 rw 0h mlimit: memory limit address corresponds to a[31:20] of the memory address that corresponds to the upper limit of the range of memory accesses that will be passed by the pci express bridge 3:0 ro 0h reserved. (by pci sig)
register description 116 intel ? 5000x chipset memory controller hub (mch) datasheet the bottom 4 bits of both the prefetchable memory base and prefetchable memory limit registers are read-only, contain the same value, and encode whether or not the bridge supports 64-bit addresses. if these fo ur bits have the value 0h, then the bridge supports only 32 bit addresses. if these four bits have the value 01h, then the bridge supports 64-bit addresses and the prefetch able base upper 32 bits and prefetchable limit upper 32 bits registers hold the rest of the 64-bit prefetchable base and limit addresses respectively. 3.8.8.19 pmlim[7:2] - pref etchable memory limit this register controls the processor to pci express prefetchable memory access routing based on the following formula as described above: prefetch_memory_base <= a[31:20] <= preftch_memory_limit the upper 12 bits of the register are re ad/write and correspond to the upper 12 address bits a[31:20] of the 32 bit address. this register must be initialized by the configuration software. for the purpose of address decode address bits a[19:0] are assumed to be f ffffh. device: 2-3 function: 0 offset: 24h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 24h version: intel 5000z chipset device: 4-7 function: 0 offset: 24h version: intel 5000p chipset bit attr default description 15:4 rw 0h pmbase: prefetchable memory base address corresponds to a[31:20] of the prefetchable memory address on the pci express port. 3:0 ro 1h pmbase_cap: prefetchable memory base address capability 0h ? 32 bit prefetchable memory addressing 1h ? 64bit prefetchable memory addressing, others - reserved. device: 2-3 function: 0 offset: 26h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-7 function: 0 offset: 26h version: intel 5000p chipset bit attr default description 15:4 rw 0h pmlimit: prefetchable memory limit address corresponds to a[31:20] of the memory address on the pci express bridge
intel ? 5000x chipset memory controller hub (mch) datasheet 117 register description 3.8.8.20 pmbu[7:2] - prefetchable memory base (upper 32 bits) the prefetchable base upper 32 bits and pref etchable limit upper 32 bits registers are extensions to the prefetchable memory base and prefetchable memory limit registers. if the prefetchable memory base and prefetchable memory limit registers indicate support for 32-bit addressing, then the prefetchable base upper 32 bits and prefetchable limit upper 32 bits registers should return zero when read. if the prefetchable memory base and prefetchable memory limit registers indicate support for 64-bit addressing, then the prefetchable base upper 32 bits and prefetchable limit upper 32 bits registers are implemented as read/write registers. if a 64-bit prefetchable memory address ra nge is supported, the prefetchable base upper 32 bits and prefetchable limit upper 32 bits registers specify the upper 32 bits, corresponding to a[63:32], of the 64-bit base and limit addresses which specify the prefetchable memory address range. 3:0 ro 1h pmlimit_cap: prefetchable memory limit address capability 0h ? 32 bit prefetchable memory addressing 1h ? 64 bit prefetchable memory addressing, others - reserved. device: 2-3 function: 0 offset: 26h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-7 function: 0 offset: 26h version: intel 5000p chipset bit attr default description device: 2-3 function: 0 offset: 28h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 28h version: intel 5000z chipset device: 4-7 function: 0 offset: 28h version: intel 5000p chipset bit attr default description 31:0 rw 0h pumbase: prefetchable upper 32-bit memory base address corresponds to a[63:32] of the memory address that maps to the upper base of the prefetchable range of memory acce sses that will be passed by the pci express bridge. os should program thes e bits based on the available physical limits of the system.
register description 118 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.8.21 pmlu[7:2] - prefetchable memory limit (upper 32 bits) 3.8.8.22 iob[7:2] - i/o base register (upper 16 bits) not used since mch does not support upper 16-bit i/o addressing. 3.8.8.23 iol[7:2] - i/o limit register (upper 16 bits) not used since mch does not support upper 16-bit i/o addressing. 3.8.8.24 capptr[7:2, 0]- capability pointer the capptr is used to point to a linked list of additional capabilities implemented by this device. it provides the offset to the first set of capabilities registers located in the pci compatible space from 40h. currently the firs t structure is located 50h to provide room for other registers. device: 2-3 function: 0 offset: 2ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 2ch version: intel 5000z chipset device: 4-7 function: 0 offset: 2ch version: intel 5000p chipset bit attr default description 31:0 rw 0h pumlim: prefetchable upper 32-bit memory limit address corresponds to a[63:32] of the memory address that maps to the upper limit of the prefetchable range of memory acce sses that will be passed by the pci express bridge. os should program thes e bits based on the available physical limits of the system. device: 0, 2-3 function: 0 offset: 34h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 34h version: intel 5000z chipset device: 4-7 function: 0 offset: 34h version: intel 5000p chipset bit attr default description 7:0 ro 50h capptr: capability pointer points to the first capability structure (pm) in pci 2.3 compatible space at 50h
intel ? 5000x chipset memory controller hub (mch) datasheet 119 register description 3.8.8.25 rbar[7:2] - rom base address register not implemented in mch, since the mch is a virtual pci-pci bridge. 3.8.8.26 intl[7:2,0] - interrupt line register the interrupt line register is used to co mmunicate interrupt lin e routing information between the initialization code and the device driver . the mch does not have a dedicated interrupt line. this register ro and is provided for backwards compatibility . 3.8.8.27 intp[7:2,0] - interrupt pin register the intp register identifies legacy inte rrupts for inta, intb, intc and intd as determined by bios/firmware. these are emulated over the esi port using the appropriate assert_intx commands. device: 0, 2-3 function: 0 offset: 3ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 3ch version: intel 5000z chipset device: 4-7 function: 0 offset: 3ch version: intel 5000p chipset bit attr default description 7:0 ro 00h intl: interrupt line bios writes the interrupt routing informat ion to this register to indicate which input of the interrupt controller this pci express port is connected to. not used in mch since the pci express port does not have interrupt lines.
register description 120 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.8.28 bctrl[7:2] - bridge control register this register provides extensions to the pc icmd register that are specific to pci-pci bridges. the bctrl provides additional cont rol for the secondary interface (that is, pci express) as well as some bits that affe ct the overall behavior of the ?virtual? pci-pci bridge embedded within the mch, for example, vga compatible address range mapping. device: 0, 2-3 function: 0 offset: 3dh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 3dh version: intel 5000z chipset device: 4-7 function: 0 offset: 3dh version: intel 5000p chipset bit attr default description 7:0 rwo 01h intp: interrupt pin this field defines the type of interrup t to generate for the pci express port. 001: generate inta 010: generate intb 011: generate intc 100: generate intd others: reserved bios/configuration software has the ab ility to program this register once during boot to set up the co rrect interrupt for the port. device: 2-3 function: 0 offset: 3eh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 3eh version: intel 5000z chipset device: 4-7 function: 0 offset: 3eh version: intel 5000p chipset bit attr default description 15:12 rv 0h reserved. (by pci sig) 11 ro 0 dtss: discard timer serr status not applicable to pci express. th is bit is hardwired to 0. 10 ro 0 dts: discard timer status not applicable to pci express. th is bit is hardwired to 0. 9ro 0 sdt: secondary discard timer not applicable to pci express. th is bit is hardwired to 0.
intel ? 5000x chipset memory controller hub (mch) datasheet 121 register description 8ro 0 pdt: primary discard timer not applicable to pci express. this bit is hardwired to 0. 7ro 0 fb2ben: fast back-to-back enable not applicable to pci express. this bit is hardwired to 0. 6rw 0 sbusreset: secondary bus reset 1: setting this bit causes a hot re set on the link for the corresponding pci express port and the pci express hierarchy domain subo rdinate to the port. this sends the ltssm into the hot-reset state, which necessarily implies a reset to the downstream device and all subordinate devices. the mechanism to reset the downstream device is utilizing the ts1/ts2 ?link reset? bit (bit number 0 of symbol 5). it is recommended for software/bios that the sbusreset field be held asse rted for a minimum of 2 ms to ensure that the link enters the hot-reset state from l0 or l1/l2. software can also poll the pexlnksts.ln ktrg bit for a deasserted condition to determine if the hot-reset state has been entered at which point it can clear the sbusreset field to train the link. when this sbusreset bit is cleared after the mch enters the ?hot-reset? state, the intel 5000p chipset mch will init iate operations to move to ?detect? state and then train the link (polling, configuration, l0 (link-up)) after sending at least 2 ts1 and receiving 1 ts1 with the hotreset bit set in the training control field of ts1 and waiting for 2ms in the hot-reset state. the 2ms stay in the hot-reset state is enforced by the chipset ltssm for the pci express hierarchy to reset. if the sbusreset is held asserted even after the 2ms time-out has expired, the intel 5000p chipset mch will continue to maintain the hot-reset state. hence it is necessary for software to cl ear this register appropriately to bring the link back in training. note also that a secondary bus reset w ill not in general reset the primary side configuration registers of the targeted pci express port. this is necessary to allow software to specify special training configuration, such as entry into loopback mode. 0: no reset happens on the pci express port. 5ro 0 mamode: master abort mode not applicable to pci express. this bit is hardwired to 0. 4rw 0 vga16bdecode: vga 16-bit decode this bit enables the virtual pci-to-pci bridge to provide 16-bit decoding of vga i/o address precluding the decoding of alias addresses every 1 kb. the i/o addresses decoded is in the range of 03b0h to 03bbh or 03c0h to 03dfh within the first 1kb i/o space. 0: execute 10-bit address dec odes on vga i/o accesses. 1: execute 16-bit address dec odes on vga i/o accesses. this bit only has meaning if bit 3 (vgaen) of this register is also set to 1, enabling vga i/o decoding and forwarding by the bridge. this read/write bit enables system configuration software to select between 10- and 16-bit i/o address decoding for a ll vga i/o register accesses that are forwarded from the primary to secondary whenever the vgaen is set to 1. device: 2-3 function: 0 offset: 3eh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 3eh version: intel 5000z chipset device: 4-7 function: 0 offset: 3eh version: intel 5000p chipset bit attr default description
register description 122 intel ? 5000x chipset memory controller hub (mch) datasheet 3rw 0 vgaen: vga enable controls the routing of cpu initiated transactions targeting vga compatible i/ o and memory address ranges. this bit may only be set for one pci express port. 2rw 0 i saen: isa enable modifies the response by the intel 5000p chipset mch to an i/o access issued by the cpu that target isa i/o addresse s. this applies only to i/o addresses that are enabled by the iobase and iolim registers. 1: the intel 5000p chipset mch will not forward to pci express any i/o transactions addressing the last 768 bytes in each 1kb block even if the addresses are within the range defined by the iobase and iolim registers. see section 4.5.2 . instead of going to pci express these cycles will be forwarded to esi where they can be subt ractively or positively claimed by the isa bridge. 0: all addresses defined by the iobase and iolim for cpu i/o transactions will be mapped to pci express. 1rw 0 bcserre: serr enable this bit controls forwarding of err_cor, err_nonfatal and err_fatal messages from the pci express port to the primary side. 1: enables forwarding of err_cor, err_nonfatal and err_fatal messages. 0: disables forwarding of err_cor, err_nonfatal and err_fatal. note that bcserre is no longer a ga ting item for the recording of the sescsts.srse error. 0rw 0 prspen: parity error response enable this bit controls the response to poisoned tlps in the pci express port 1: enables reporting of poisoned tlp errors. 0: disables reporting of poisoned tlp errors device: 2-3 function: 0 offset: 3eh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 3eh version: intel 5000z chipset device: 4-7 function: 0 offset: 3eh version: intel 5000p chipset bit attr default description
intel ? 5000x chipset memory controller hub (mch) datasheet 123 register description 3.8.8.29 pexlwstpctrl: pci express link width strap control register this register provides the ability to change the pci express link width through software control. normally, the intel 5000p chipset mch will use the pewidth[3:0] pins to train the links. however, if bios needs the ability to circumvent the pin strappings and enforce a specific setting for a given platform, it must perform a soft initialization sequence through the following actions in this register: 1. set pexlwstpctrl.lwoen to ?1?. 2. write the desired link width to pexlwstpctrl.gpmnxt0(1) fields for iou0 and iou1 clusters. 3. perform a hard reset to the intel 5000p chipset mch. the chipset will then use the values in itialized in the pexlwstpctrl.gpmnxt0(1) fields and train the links appropriately followi ng the hard reset. the intel 5000p chipset mch will also provide status information to the software as to what link width it is currently using to train the link via pexlwstpctrl.gpmcur0(1) fields and the appropriate training mode, pexlwstpctrl.lwtm. (pins strap vs. software enabled mode). device: 0 function: 0 offset: 40h bit attr default description 15:14 rv 0h reserved 13:11 ro 000 gpmcur1: iou1 max width current configuration now (ports 4-7) this field is updated by the hardware to indicate the current link width of iou1 ports that is used for training. this fi eld is set before training gets underway. 000: x4,x4,x4,x4 001: x8,--,x4,x4 010: x4,x4, x8,-- 011: x8,--,x8,-- 100: x16,--,--,--,-- others: reserved 10:8 ro 000 gpmcur0: iou0 max width current conf iguration (ports 2-3 only, port 0, esi, is always x4) this field is updated by the hardware to indicate the current link width of iou1 ports that is used for training. this fi eld is set before training gets underway. 000: x4,x4 001: reserved 010: x8,-- others: reserved 7ro0 lwtm: link width training mode this field is updated by the hardware to provide feedback to software on the training mode it is using fo llowing reset. that is, link st rap or soft initialization of link widths. 0: iou clusters trained the links using the pewidth[3:0] pins (external strapping) [default] 1: iou clusters trained the links using th e soft initialization mechanism in this register viz. gpmnxt1 and gpmnxt0 following a hard reset. 6:4 rwst 000 gpmnxt1: iou1 max width conf iguration next (ports 4-7) the iou1 cluster will use this field to train the link after a hard reset provided lwoen is set. refer to table 3.8.8.30, ?pexctrl[7,2:0]: pci express control register? on page 126 .
register description 124 intel ? 5000x chipset memory controller hub (mch) datasheet 3:1 rwst 000 gpmnxt0: iou0 max width configuration next (ports 2-3) the iou0 cluster will use this field to tr ain the links after a hard reset provided lwoen is set. refer to table 3.8.8.30, ?pexctrl[7,2:0]: pci express control register? on page 126 0rwst0 lwoen: link width override enable 0: disables software from setting the pci express link width through this register and the link width is controlled by the external pins pewidth[3:0]. (default). 1. enables bios/software to set the required link width through this register. when this bit is set, the iou cluster will ignor e the external pin strap (pewidth[3:0] and use the described table for co nfiguring the link width. th e values will take effect after a hard reset. device: 0 function: 0 offset: 40h bit attr default description
intel ? 5000x chipset memory controller hub (mch) datasheet 125 register description table 3-1. gio port mode selection gio port (iou0) gio port (iou1) gpmnxt1 [2:0] (iou0) port0 (esi) port1 (rsvd) port2 port3 gpmnxt0 [2:0] (iou1) port4 port5 port6 port7 3'b000 x4 rsvd x4 x4 3'b000 x4 x4 x4 x4 3'b001 invalid 3'b001 x8 n/a x4 x4 3'b010 x4 rsvd x8 n/a 3'b010 x4 x4 x8 n/a 3'b011 invalid 3'b011 x8 n/a x8 n/a 3'b100 invalid 3'b100 x16 n/a n/a n/a 3'b101 invalid 3'b101 invalid 3'b110 invalid 3'b110 invalid 3'b111 x4 rsvd rsvd 3'b111 rsvd
register description 126 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.8.30 pexctrl[7,2:0]: pci express control register device: 7-2,0 function: 0 offset: 48h bit attr default description 31:26 rw 0h reserved 25:24 rw 00 coalesce_mode : used to increase the amount of combining for completions. 00: no restriction on coalescing_hin t. the iou will try to maximize completion combining. since intel 5000p chipset mch issues requests in order, it does not make sense to restrict the coalesce hint because there are few resources available at the time of fetch. by the time the hint is used, resources could be fre ed up and reused for the following requests. note: this mode of ?00? is the preferred setting for intel 5000p chipset mch if coalesce_en=1 for software/bios 01: #cpl_entries_free will restrict coalesce_hint 10: if set then #pf_pend wi ll restrict coalesce hint 11: minimum of coalesce_hint obt ained from settings ?01? and ?10? 23 rw 0 timeout_enable_cfg: timeout enable for configuration transactions 1: config transactions can time out. 0: config transactions cannot time out. suggested value: 0 note: in general, configuration timeouts on the pci-express port should not be enabled. this is necessary to permit slow devices nested deep in the pci hierarchy that may take longer to complete requests than the maximum timeout specified in the intel 5000p. software/bios should set this field based on the context and usage/platform configuration. for e.g. compliance testing with a known broken card should have this field set. note: for the configuration timeout to take effect, (due to intel 5000p rtl implementation) the pexctrl.timeout_enable (bit 22) has to be set. note: due to recently discovered rtl bug in b3 and later stepping, the iou will log a completion erro r (io6) for any outstanding configuration transaction that crosses the counter limit even if this register field is cleared or bit 22 of this register is cleared (example, either timeout is disabled. however, it does not affect the functionality and the config transaction will be outstanding indefinitely until the completion is returned except for the unnecessary error log. software should be aware of this limitation when the field is cleared.) 22 rw 0 timeout_enable: timeout en able for non-configuration transactions 1: non config transactions can time out. 0: non config transactions cannot time out. suggested value: 1 note: when both timeout_enable_cfg and timeout_enable fields are set to 0, the intel 5000p will assume an infinite completion time for the respective transactions. hence the system is dependent on the end device re turning the completion response at some point in time, else it will result in a hang. note: due to recently discovered rtl bug in b3 and later stepping, the iou will log a completion erro r (io6) for any outstanding configuration transaction that crosses the counter limit even if this register field is cleared or bit 22 of this register is cleared (example, either timeout is disabled. however, it does not affect the functionality and the config transaction will be outstanding indefinitely until the completion is returned except for the unnecessary error log. software should be aware of this limitation when the field is cleared.)
intel ? 5000x chipset memory controller hub (mch) datasheet 127 register description 21 rw 0 maltlp_en: 1: check for certain malformed tlp types. 0: do not check for certain malformed tlp types. suggested value: 1 when this bit is set, it enables the following conditions to mark a packet as malformed: ? 4dw header mem_rd or mem_wr and the address is less than 32 bits (address[39:32] = 0) ? byte enable check for mem/io/cfg requests. length > 1 dw and (first dword byte enables = 0 or last dword byte enables = 0) length = 1 dw and last dword byte enables != 0 ? io{rd,wr}/cfg{rd,wr}{0,1} and (traffic class != 0 or attributes != 0 or length != 1) ? a configuration retry completion response (crs) received for a non- cfg outbound request 20:13 rv 0h reserved 12 rw 0 max_rdcmp_lmt_en: maximum re ad completion combining limit enable 1: up to 256 b return and coalesce_en = 1. 0: up to 128 b return if coalesce_en = 1 note : it is strongly recommended that this field should not be set to 1 (256 b completion combining) due an mch b2 silicon issue, especially when mps is configured to 256 b. 11 rw 0 coalesce_force : force coalescing of accesses. when 1, forces intel 5000p chipset mc h to wait for all coalescable data before sending the transaction as op posed to forwarding as much as possible. 0: normal operation 1: wait to coalesce data note: it is strongly recommended that coalesce_force should not be set to ?1? due to an mch b2 silicon erratum. 10 rw 0 coalesce_en : read completion coalescing enable when 1, enables read return of >64 b. 1: returns of >64 b enabled. (see max_rdcmp_lmt_en above) . 0: returns are 64 b or less. note: for optimal read completion combin ing, this field should be set to ?1? along with max_rdcmp_lmt_en as ?0? for 128b completion combining. 9rw 0 pmegpeen : pme gpe enable 1: enables ?assert_pmegpe? (deassert_pmegpe) messages to be sent over the dmi from the root complex for pm interrupts. 0: disables ?assert_pmegpe? (deassert_pmegpe) messages for pm events to the root complex. this has an overriding effect to generate acpi pm interrupts over traditional interrupts (msi/intx). 8rw 0 hpgpeen: hotp lug gpe enable 1: enables ?assert_hpgpe? (deassert_hpgpe) messages to be sent from the root complex for hot-plug events. 0: disables ?assert_hpgpe? (deasse rt_hpgpe) messages for hot-plug events from the root complex. this has an overriding effect to gener ate acpi hp events over traditional interrupts. 7rv 1 reserved device: 7-2,0 function: 0 offset: 48h bit attr default description
register description 128 intel ? 5000x chipset memory controller hub (mch) datasheet this 32-bit register implements chipset specific operations for general control/ accessibility such as device hiding, selective configuration cycles and interrupt signaling 6:3 rw 0000 vpp: virtual pin port [6:4] = smbus address, [3] =io port defines the 8-bit io port that is used for routing power, attention, hotplug, presence, mrl and other events defined in section 3.8.11.10 . 2rw 1 dis_vpp: disable vpp the intel 5000p chipset mch will use this bit to decide whether the vpp is valid or not for the given pci ex press port as set by configuration software. for example, to distinguish hp events for a legacy card or pci express port module, this bit can be used. 1: vpp is disabled for this pci express port. 0: vpp is enabled for this pci express port. default value is to disable vpp for the pci express port 1rw 0 dis_apic_eoi; disable apic eoi the intel 5000x mch will use this bit to decide whether end of interrupts (eoi) need to be sent to an apic controller/bridge (for example, intel 6700pxh 64 bit pci hub) through this pci express device. 1: no eois are sent (disabled). 0: eois are dispatched to the apic controller. note: in the case of slave (secondary) ports, the bios has to disable eoi for that port by setting this register field. for example, x8 device connected on port 2-3 should have the pexctrl.dis_apic_eoi of the slave port (viz. #3) set to prevent eois from causing deadlocks. this is a micro- architectural requirement due to the internal handshake between iou-ce for eoi slave handling. 0if (port 7- 2) {rwo} elsif (port 0) {rv} endif 0 devhide: device_hide the device hide bit is used to enable the intel 5000x mch to hide the pci express device from the operating sy stem and is applicable only to ports 7-2. typically, an external i/o processo r acts as its proxy by configuring it and claiming resources on behalf of it and then unhides. the hiding is done by changing the class code (ccr register) for this port to 0x0600. this will prevent the os from attempting to probe or modify anything related to this device. 1: the pci express port ccr register has a value of 0600. 0: the pci express port ccr register has a value of 0604 (bridge) the default value is ?0? (to make the device a bridge). the device hide bit does not apply to the dmi interface (port 0) and has no effect on its operation. device: 7-2,0 function: 0 offset: 48h bit attr default description
intel ? 5000x chipset memory controller hub (mch) datasheet 129 register description 3.8.8.31 pexctrl2[7:2,0]: pci express control register 2 this is an auxiliary control register for pci express port specific debug/defeature operations. 3.8.8.32 pexctrl3[7:2,0] - pci express control register 3 this is an additional control register fo r pci express port specific debug/defeature operations for ras. device: 0, 2-3 function: 0 offset: 4ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 4ch version: intel 5000z chipset device: 4-7 function: 0 offset: 4ch version: intel 5000p chipset bit attr default description 7:1 rv 0 reserved. 0rw 0 no_compliance: set by software to enable link operation in the presence of single wire failures on the link. if clear, then specified link b ehavior in the presence of a wire failure will be polling.compliance. device: 0, 2-3 function: 0 offset: 4dh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 4dh version: intel 5000z chipset device: 4-7 function: 0 offset: 4dh version: intel 5000p chipset bit attr default description 7:5 rv 0 reserved. 4rwo 1 portenable: pci express port enable control 1: the pci express port can be enabled by software and is available for use. 0: the pci express port is disabled and not available. this setting disables the underlying port logic and associated pci express x4 lanes, completely removing the port from register configuration space. 3:0 rv 0 reserved
register description 130 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.8.33 pexgctrl - pci express global control register this 32-bit global register in the mch implements chipset specific operations for generalized control of all pci express events and activity such as power management, hot-plug. there is only one register for a ll pci express ports and dma engine device that controls related i/o operations. device:19 function:0 offset:17ch version:intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:18 rv 3fffh timeout: completion time out internal timer for handling outbound np completion timeouts. this varies based on the core clock frequency and the time at which the completion structure is loaded relative to the timeout timer which is free-running. the bounds of this roll over can be approximated as a minimum of 6 or max of 7 few cycles) since there is a 3 bit counter whose roll over is tied to the timeout timer for 333 mhz, the granularity of this time r viz. each increment is in the range (9216 ns, 10,752 ns) giving a min/max value for a full face value of this register field as (150.99 ms, 176.15 ms) for 266 mhz, the granularity of this time r viz. each increment is in the range (11520 ns, 13440 ns) giving a min/max value for a full face value of this register field as (188.73 ms, 220.19 ms) bios/software needs to set this field as appropriate for handling various timeout conditions requ ired by the system. note: for example with bnb running at 333 mhz, for smbus protocols, the maximum value recommended for this field is 0x744 (or 1860 decimal) to achieve a 20 ms timeout threshold (that is, 20 ms =~ 10,752 * 1860) such that it provides headroom to the chipset for the global smbus timeout of 25ms. example: with 0x744 as default and 333 mhz core clock, 1. max timeout value: if bits 31:28 were set to 0x744 (1860d), the timeout delay is calculated as follows: 1860*7 (for the rollovers)*512(lower 9 bits)*3.0ns (for 333 mhz) = 1860*107542=19.998ms=~20 ms 2. min timeout value: if bits 31:28 were set to 0x744 (1860d), the delay calculation would be like this: 1860*6 (too close to the limit, so missed full count for one rollover)*512 (lower 9 bits)*3.0 ns (for 333 mhz)= 17.141 ms=~17 ms 17:2 rv 1385 reserved. 1 rwst 0 pme_turn_off: send pme turn off message when set, the intel 5000 chipset mch will issue a pme turn off message to all enabled pci express ports excluding the esi port. the intel 5000 chipset mch will clear this bit once the message is sent. ?note: in the intel 5000 chipset mch implementation, an end device that is d3 pm state and the link being in l2 will not respond to any transaction to the device until it is woken up by the wake# signal in the platform. under these conditions, if software sets the pme_turn_off (bit 1) of this register, the intel 5000 chipset mch will not send the message until the link is brought back into l0. i.e. pme_turn_off bit will remain set until the message is dispatched. furthermore, a surprise link down error is logged. ? expected usage: software should not set this bit if the link is already in l2 prior. 0 rwc 0 pme_to_ack: received pme time out acknowledge message the intel 5000p chipset mch sets this bit when it receives a pme_to_ack message from all enabled pci express po rts excluding the esi port. software will clear this bit when it handles the acknowledge. note that the esi2 will not generate a pme_to_ack based on the flow described in the esi spec. however, if a pme_to_ack is received at the intel 5000p chipset mch esi port, it will be master aborted.
intel ? 5000x chipset memory controller hub (mch) datasheet 131 register description 3.8.8.34 intxswzctrl[7:2,0]: pci express interrupt swizzle control register this register provides software the ability to swizzle the legacy interrupts (intx) from each port and remap them to a different inte rrupt type (inta,b,c,d) for the purposes of interrupt rebalancing to optimize system pe rformance. this swizz ling only applies to inbound intx messages that arrive at the various ports (including esi). the default setting is to have one-to-one map of the same interrupt types, that is (inta => inta, and so forth). bios can program this regi ster during boot time (before enabling interrupts) to swizzle the intx types for the various ports within the combinations described in this register. mch will use the transformed intx messages from the various ports and track them using the bit vector as a wired-or logic for sending assert/ deassert intx messages on the esi. please refer to the interrupt swizzling solution for intel 5000 chipset series-based platforms - application note , document #314337 available on developer.intel.com for more detailed information on this feature. 3.8.9 pci express power management capability structure the intel 5000p chipset mch pci express po rt provides basic power management capabilities to handle pm events for compat ibility. the pci express ports can be placed in a pseudo d3 hot state but it does have re al power savings and works as if it were in the d0 mode. 3.8.9.1 pmcap[7:2,0] - power ma nagement capabilities register the pm capabilities register defines the capability id, next pointer and other power management related support. the followin g pm registers /capabilities are added for software compliance. device: 7-2,0 function: 0 offset: 4fh bit attr default description 7:2 ro 0h reserved 1:0 rwo 00 intxswz: intx swizzle the encoding below defines the target in tx type to which the incoming intx message is mapped to for that port. (4 combinations using the barber-pole slide mechanism) 00: inta=>inta, intb=>intb, intc=>intc, intd=>intd (default 1:1) 01: inta=>intb, intb=>intc, intc=>intd, intd=>inta 10: inta=>intc, intb=>intd, intc=>inta, intd=>intb 11: inta=>intd, intb=>inta, intc=>intb, intd=>intc
register description 132 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.9.2 pmcsr[7:2, 0] - power manage ment control and status register this register provides status and control in formation for pm events in the pci express port of the mch. device: 0, 2-3 function: 0 offset: 50h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 50h version: intel 5000z chipset device: 4-7 function: 0 offset: 50h version: intel 5000p chipset bit attr default description 31:27 ro 11001 pmes: pme support identifies power states in the inte l 5000p chipset mch which can send an ?assert_pmegpe/deassert pmegpe? message. bits 31, 30 and 27 must be set to '1' for pci-pci bridge structures representing ports on root complexes. the definition of these bits is taken from the pci bus power management interface specification revision 1.1. xxxx1b - assert_ pmegpe / deassert pmegpe can be sent from d0 xxx1xb - assert_ pmegpe/deassert pmegpe can be sent from d1 (not supported by intel 5000p chipset mch) xx1xxb - assert_ pmegpe/deassert pmegpe can be sent from d2 (not supported by intel 5000p chipset mch) x1xxxb - assert_ pmegpe/deassert pmegpe can be sent from d3 hot (supported by inte l 5000p chipset mch) 1xxxxb - assert_ pmegpe/deassert pmegpe can be sent from d3 cold (not supported by intel 5000p chipset mch) 26 ro 0 d2s: d2 support intel 5000p chipset mch does not support power management state d2. 25 ro 0 d1s: d1 support intel 5000p chipset mch does not support power management state d1. 24:22 ro 0h auxcur: aux current 21 ro 0 dsi: device specific initialization 20 rv 0 reserved. 19 ro 0 pmeclk: pme clock this field is hardwired to 0h as it does not apply to pci express. 18:16 ro 010 ver: version this field is set to 2h as version number from the pci express base specification , revision 1.0a specification. 15:8 ro 58h nxtcapptr: next capability pointer this field is set to offset 58h for the next capability structure (msi) in the pci 2.3 compatible space. 7:0 ro 01h capid: capability id provides the pm capabili ty id assigned by pci-sig.
intel ? 5000x chipset memory controller hub (mch) datasheet 133 register description device: 0, 2-3 function: 0 offset: 54h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 54h version: intel 5000z chipset device: 4-7 function: 0 offset: 54h version: intel 5000p chipset bit attr default description 31:24 ro 00h data: data data read out based on data select (dsel). refer to section 3.2.6 of pci pm specification for details. this is not implemented in the power management capability for intel 5000p chipset mch and is hardwired to 0h. 23 ro 0h bpccen: bus power/clock control enable this field is hardwired to 0h as it does not apply to pci express. 22 ro 0h b2b3s: b2/b3 support this field is hardwired to 0h as it does not apply to pci express. 21:16 rv 0h reserved. 15 rwcst 0h pmests: pme status this pme status is a sticky bit. when set, the pci express port generates a pme internally independent of the pmeen bit defined below. software clears this bit by writing a ?1? when it has been completed. as a root port, the intel 5000p chipset mch will never set this bit, because it never generates a pme interna lly independent of the pmeen bit. 14:13 ro 0h dscl: data scale this 2-bit field indicates the scaling fa ctor to be used while interpreting the ?data_scale? field. 12:9 ro 0h dsel: data select this 4-bit field is used to select which data is to reported through the ?data? and the ?data scale? fields. 8rwst 0h pmeen: pme enable this field is a sticky bit and when set enables pmes generated internally to appear at the intel 631xesb/632xes b i/o controller hub through the ?assert(deassert)_pmegpe?message. this has no effect on the intel 5000p chipset mch since it does not generate pme events internally. 7:2 rv 0h reserved. 1:0 rw 0h ps: power state this 2-bit field is used to determine the current power state of the function and to set a new power state as well. 00: d0 01: d1 (reserved) 10: d2 (reserved) 11: d3_hot if software sets this to d1 or d2, then the power state will default to d0.
register description 134 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.10 pci express mess age signaled interrup ts (msi) capability structure message signaled interrupts (msi) is an op tional feature that enables a device to request service by writing a system-specified message to a system-specified address in the form of an interrupt message. the tran saction address (for example, feex_xxxxh) specifies the message destination and the transaction data specifies the message. the msi mechanism is supported by the followi ng registers: the msicapid, msinxptr, msictrl, msiar and msidr register described below. 3.8.10.1 msicapid[7:2, 0] - msi capability id 3.8.10.2 msinxptr[7:2, 0]- msi next pointer device: 0, 2-3 function: 0 offset: 58h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 58h version: intel 5000z chipset device: 4-7 function: 0 offset: 58h version: intel 5000p chipset bit attr default description 7:0 ro 05h capid: capability id assigned by pci-sig for message signaling capability. device: 0, 2-3 function: 0 offset: 59h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 59h version: intel 5000z chipset device: 4-7 function: 0 offset: 59h version: intel 5000p chipset bit attr default description 7:0 ro 6ch nxtptr: next pointer this field is set to 6ch for the next ca pability list (pci express capability structure - pexcap) in the chain.
intel ? 5000x chipset memory controller hub (mch) datasheet 135 register description 3.8.10.3 msictrl[7:2, 0] - message control register device: 0, 2-3 function: 0 offset: 5ah version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 5ah version: intel 5000z chipset device: 4-7 function: 0 offset: 5ah version: intel 5000p chipset bit attr default description 15:8 rv 00h reserved. 7ro 0 ad64cap: 64-bit address capable this field is hardwired to 0h since the message writes addresses are only 32- bit addresses (for ex ample, feex_xxxxh). 6:4 rw 000 mmen: multiple message enable software writes to this field to indicate the number of allocated messages which is aligned to a power of two. when msi is enabled, the software will allocate at least one message to the de vice. see below for discussion on how the interrupts are handled if n is the number of messages by software. if software writes a value greater than the limit specified by the mmcap field in the mmen field, it is considered as a programming error. the intel 5000p chipset mch gnb will only use the lsb of the mmen (as a power of 2) to decode up to 2 messages. 3:1 ro 001 mmcap: multiple message capable software reads this field to determine the number of requested messages. which is aligned to a power of two. it is set to 2 messages (encoding of 001). th e intel 5000p chipset mch is designe d to handle msis for different events ? hp/pm events ? ras error events 0rw 0 msien: msi enable the software sets this bit to select legacy interrupts or transmit msi messages. 0: disables msi from being generated. 1: enables the intel 5000p chipset mc h to use msi messages to request context specific service through register bits defined in the section 3.8.8.32 for events such as hot-plug, pm, ras. refer to the intel 5000p chipset programming guide for details on the legacy, acpi and interrupt generation events.
register description 136 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.10.4 msiar[7:2, 0] - msi address register the msi address register (msiar) contains th e system specific address information to route msi interrupts and is broken into its constituent fields. 3.8.10.5 msidr[7:2, 0] - msi data register the msi data register (msidr) contains all the data (interrupt vector) related information to route msi interrupts. device: 0, 2-3 function: 0 offset: 5ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 5ch version: intel 5000z chipset device: 4-7 function: 0 offset: 5ch version: intel 5000p chipset bit attr default description 31:20 ro feeh amsb: address msb this field specifies the 12 most signi ficant bits of the 32-bit msi address. 19:12 rw 00h adstid: address destination id this field is initialized by software fo r routing the interrupts to the appropriate destination. 11:4 rw 00h aexdstid: address extended destination id this field is not used by ia32 processor. 3rw 0h ardhint: address redirection hint 0: directed 1: redirectable 2rw 0h adm: address destination mode 0: physical 1: logical 1:0 rv 0h reserved. not used since the memory write is d-word aligned
intel ? 5000x chipset memory controller hub (mch) datasheet 137 register description device: 0, 2-3 function: 0 offset: 60h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 60h version: intel 5000z chipset device: 4-7 function: 0 offset: 60h version: intel 5000p chipset bit attr default description 31:16 rv 0000h reserved. 15 rw 0h tm: trigger mode this field specifies the ty pe of trigger operation 0: edge 1: level 14 rw 0h lvl: level if tm is 0h, then this field is a don?t care. edge triggered messages are consistently treated as assert messages. for level triggered interrupts, th is bit reflects the state of the interrupt input if tm is 1h, then 0: deassert messages 1: assert messages 13:11 rw 0h these bits are don?t care in ioxapic interrupt message data field specification. 10:8 rw 0h dm: delivery mode 000: fixed 001: lowest priority 010: smi/hmi 011: reserved 100: nmi 101: init 110: reserved 111: extint 7:0 rw 0h iv: interrupt vector the interrupt vector (lsb) will be modified by the intel 5000p chipset mch to provide context sensitive interrupt inform ation for different events that require attention from the processor. for example, hot-plug, power management and ras error events. depending on the number of messages enabled by the processor in section 3.8.10.3 , and ta b l e 3 - 3 4 illustrates the breakdown. table 3-34. iv handling and processing by mch number of messages enabled by software (msictrl.mmen) events iv[7:0] 1all xxxxxxxx 1 notes: 1. the term ?xxxxxx? in the interrupt vector denotes that software/bios initializes them and the mch will not modify any of the ?x? bits except the lsb as indicated in the table as a function of mmen 2hp, pm xxxxxxx0 ras errors xxxxxxx1
register description 138 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.11 pci express capability structure the pci express capability structure describes pci express related functionality, identification and other information such as control/status associated with the port. it is located in the pci 2.3 compatible space and supports legacy operating system by enabling pci software transparent features. 3.8.11.1 pexcapl[7:2, 0]- pci ex press capability list register the pci express capability list register enumerates the pci express capability structure in the pci 2.3 configuration space. 3.8.11.2 pexcap[7:2, 0] - pci express capabilities register the pci express capabilities register iden tifies the pci express device type and associated capabilities. device: 0, 2-3 function: 0 offset: 6ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 6ch version: intel 5000z chipset device: 4-7 function: 0 offset: 6ch version: intel 5000p chipset bit attr default description 15:8 ro 00h nxtptr: next ptr this field is set to null pointer to terminate the pci capability list. 7:0 ro 10h capid: capability id provides the pci express capabi lity id assigned by pci-sig. device: 0, 2-3 function: 0 offset: 6eh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 6eh version: intel 5000z chipset device: 4-7 function: 0 offset: 6eh version: intel 5000p chipset bit attr default description 15:14 rv 0h reserved.
intel ? 5000x chipset memory controller hub (mch) datasheet 139 register description 3.8.11.3 pexdevcap[7:2, 0] - pci express device capabilities register the pci express device capabilities register identifies device specific information for the port. 13:9 ro 00h imn: interrupt message number this field indicates the interrupt message number that is generated from the pci express port. when there are more than one msi interrupt number, this register field is required to contain the offset between the base message data and the msi message that is generated when the status bits in the slot status register or root port status registers are set. the chipset is required to update the field if the number of msi messages changes. 8if (port 7-2) {rw o} elsif (port 0) {ro} endif 0 slot_impl: slot implemented 1: indicates that the pci express link as sociated with the port is connected to a slot. 0: indicates no slot is connected to this port. this register bit is of type ?write once? and is controlled by bios/special initialization firmware. for the dmi port, this value should always be 0b since it is not hot-pluggable and it is required for boot. rest of the pci_express ports which are slotted/hot-pluggable, bios or software can set this field to enable the slots. 7:4 ro 0100 dpt: device/port type this field identifies the type of device. it is set to 0100 as defined in the spec since the pci express port is a ?root port? in the intel 5000p chipset mch. 3:0 ro 0001 vers: capability version this field identifies the version of the pci express capability structure. set to 0001 by pci sig. device: 0, 2-3 function: 0 offset: 6eh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 6eh version: intel 5000z chipset device: 4-7 function: 0 offset: 6eh version: intel 5000p chipset bit attr default description
register description 140 intel ? 5000x chipset memory controller hub (mch) datasheet device: 0, 2-3 function: 0 offset: 70h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 70h version: intel 5000z chipset device: 4-7 function: 0 offset: 70h version: intel 5000p chipset bit attr default description 31:28 rv 0h reserved. 27:26 ro 0h cspls: captured slot power limit scale specifies the scale used for the c aptured slot power limit value. it does not apply to intel 5000p chipset mch as it is a root complex. hardwired to 0h . 25:18 ro 00h csplv: captured slot power limit value this field specifies upper limit on power su pplied by a slot in an upstream port. it does not apply to intel 5000p chipset mch as it is a root complex. hardwired to 00h . 17:15 rv 0h reserved 14 ro 0 pipd: power indicator present on device this bit when set indicates that a power indicator is implemented. 0: pipd is disabled in intel 5000p chipset mch 1: reserved 13 ro 0 aipd: attention indicator present this bit when set indicates that an attention indicator is implemented. 0: aipd is disabled in intel 5000p chipset mch 1: reserved 12 ro 0 abpd: attention button present this bit when set indicates that an attention button is implemented. 0: abpd is disabled in intel 5000p chipset mch 1: reserved 11:9 ro 111 epl1al: endpoint l1 acceptable latency this field indicates the acceptable la tency that an endpoint can withstand due to the transition from l1 state to the l0 state. 000: less than 1s 001: 1 s to less than 2 s 010: 2 s to less than 4 s 011: 4 s to less than 8 s 100: 8 s to less than 16 s 101: 16 s to less than 32 s 110: 32 s to 64 s 111: more than 64 s the intel 5000p chipset mch does not su pport endpointl1 acceptable latency and is set to the maximum value for safety.
intel ? 5000x chipset memory controller hub (mch) datasheet 141 register description 8:6 ro 111 epl0al: endpoints l0s acceptable latency this field indicates the ac ceptable latency that an endpoint can withstand due to the transition from l0s state to the l0 state. 000: less than 64 ns 001: 64 ns to less than 128 ns 010: 128 ns to less than 256 ns 011: 256 ns to less than 512 ns 100: 512 ns to less than 1 s 101: 1 s to less than 2 s 110: 2 s to 4 s 111: more than 4 s note that intel 5000p chipset mch does not support l0s implementation and for backup, this field is set to the maximum value. 5ro 0 etfs: extended tag field supported this field indicates the maximum supported size of the tag field. 0: in the intel 5000p chipset mch, only 5-bit tag field is supported 4:3 ro 0h pfs: phantom functions supported this field indicates the number of most significant bits of the function number portion of requester id in a tlp that are logically combined with the tag identifier. 0: for root ports, no function number bits for phantom functions are supported 2:0 ro 001 mplss: max payload size supported this field indicates the maximum payload size that the pci express port can support for tlps. 001: 256 b max payload size others - reserved note that the intel 5000p chipset mch on ly supports up to a maximum of 256 b payload (for example, writes, read completions) for each tlp and violations will be flagged as pci express errors device: 0, 2-3 function: 0 offset: 70h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 70h version: intel 5000z chipset device: 4-7 function: 0 offset: 70h version: intel 5000p chipset bit attr default description
register description 142 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.11.4 pexdevctrl[7:2, 0] - pci express device control register the pci express device control register co ntrols pci express specific capabilities parameters associated with this port. device: 0, 2-3 function: 0 offset: 74h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 74h version: intel 5000z chipset device: 4-7 function: 0 offset: 74h version: intel 5000p chipset bit attr default description 15 rv 0h reserved. 14:12 rw 101 mrrs: ma x_ read_reques t_ size this field sets maximum read request size generated by the intel 5000p chipset mch . the pci express port must not generate read requests with size exceeding the set value. 000: 128b max read request size 001: 256b max read request size 010: 512b max read request size 011: 1024b max read request size 100: 2048b max read request size 101: 4096b max read request size 110: reserved 111: reserved the mch will not generate read requests larger than 64b in general on the outbound side due to the internal micro- architecture (cpu initiated, dma or peer to peer). hence the field is set to 000b encoding. 11 rw 1 ennosnp: enable no snoop when set, the pci express port is permitted to set the ?no snoop bit? in the requester attributes of tr ansactions it initiates that do not require hardware enforced cache coherency. typically the ?no snoop bit? is set by an originating pci express device down in the hierarchy. the intel 5000p chipset mch never sets or modifies the ?no snoop bit? in the received tlp even if ennosnp is enabled. for outbound traffic, the intel 5000p chipset mch does not need to snoop. 10 rwst 0 appme: auxiliary power management enable 1: enables the pci express port to draw aux power independent of pme aux power. 0: disables the pci express port to draw aux power independent of pme aux power. devices that require aux power on legacy operating systems should continue to indicate pme aux power requirements. aux power is allocated as requested in the aux_current field on the power management capabilities register (pmc), independent of the pmeen bit in the power management. control & status register (pmcsr) defined in section 3.8.9.2 .
intel ? 5000x chipset memory controller hub (mch) datasheet 143 register description 9ro 0 pfen: phantom functions enable this bit enables the pci express port to use unclaimed functions as phantom functions for extending the number of outstanding transaction identifiers. intel 5000p chipset mch does not implement this bit (root complex) and is hardwired to 0. 8ro 0h etfen: extended tag field enable this bit enables the pci express port to use an 8-bit tag field as a requester. the intel 5000p chipset mch does not use this field (root complex) and is hardwired to 0. 7:5 rw 000 mps: max payload size this field is set by configuration soft ware for the maximum tlp payload size for the pci express port. as a receiv er, the intel 5000p chipset mch must handle tlps as large as the set value. as a transmitter, it must not generate tlps exceeding the set value. permissible values that can be programmed are indicated by the max_payload_size_s upported in the device capabilities register: 000: 128b max payload size 001: 256b max payload size 010: 512b max payload size 011: 1024b max payload size 100: 2048b max payload size 101: 4096b max payload size others: reserved note: the mch supports max payload sizes only up to 256b. if software programs a value that exceeds 256b for the mps field, then it will be considered as an error. for receive tlps, it will be flagged as ?unsupported request? and for transmit tlps, it will be recorded as a malformed tlp. note: due to erratum 501664, read completi on coalescing cannot be used if mps=256 b is set by software. read co mpletion combining up to 128 b would work only if the mps is set by software. read completion combining up to 128 b would work only if the mps is set to 128 b. see pexctrl.coalesce_en field. 4ro 0 enrord: enable relaxed ordering intel 5000p chipset mch enforces only strict ordering only and hence this bit is initialized to ?0? 3rw 0 urren: unsupported request reporting enable this bit controls the reporting of unsupported requests to the mch in the pci express port. 0: unsupported request reporting is disabled 1: unsupported request reporting is enabled note that the reporting of error messages (such as err_corr, err_nonfatal, err_fatal) received by pci express port is controlled exclusively by the pci express root control register (pexrtctrl) described in section 3.8.11.12 . device: 0, 2-3 function: 0 offset: 74h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 74h version: intel 5000z chipset device: 4-7 function: 0 offset: 74h version: intel 5000p chipset bit attr default description
register description 144 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.11.5 pexdevsts[7:2, 0] - pci express device status register the pci express device status register prov ides information about pci express device specific parameters associated with this port. 2rw 0 fere: fatal error reporting enable this bit controls the reporting of fatal errors internal to the mch in the pci express port. 0: fatal error reporting is disabled 1: fatal error reporting is enabled 1rw 0 nfere: non fatal error reporting enable this bit controls the reporting of non fatal errors internal to the mch in the pci express port. 0: non fatal error reporting is disabled 1: non fatal error reporting is enabled 0rw 0 cere: correctable error reporting enable this bit controls the reporting of correctable errors internal to the mch in the pci express port. 0: correctable error reporting is disabled 1: correctable fatal error reporting is enabled device: 0, 2-3 function: 0 offset: 74h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 74h version: intel 5000z chipset device: 4-7 function: 0 offset: 74h version: intel 5000p chipset bit attr default description device: 0, 2-3 function: 0 offset: 76h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 76h version: intel 5000z chipset device: 4-7 function: 0 offset: 76h version: intel 5000p chipset bit attr default description 15:6 rv 000h reserved. 5ro 0h tp: transactions pending 1: indicates that the pci express port has issued non-posted requests which have not been completed. 0: a device reports this bit cleare d only when all completions for any outstanding non-posted requests have been received. since the mch root port that do not issue non-posted requests on their own behalf, it is hardwired to 0b.
intel ? 5000x chipset memory controller hub (mch) datasheet 145 register description 3.8.11.6 pexlnkcap[7:2,0] - pci ex press link capabilities register the link capabilities register identifies the pci express specific link capabilities. 4ro 0 apd: aux power detected 1- aux power is detected by the pci express port. 0: no aux power is detected 3rwc 0 urd: unsupported request detected this bit indicates that the device received an unsupported request in the pci express port . errors are logged in this register regardless of whether error reporting is enabled or not in the device control register. 1: unsupported request detected at the port this records the detection of receiving an unsupported request, error io2. 2rwc 0 fed: fatal error detected this bit indicates that status of a fatal (uncorrectable) error detected in the pci express port. errors are logged in this register regardless of whether error reporting is enabled or not in the device control register. 1: fatal errors detected 0: no fatal errors detected 1rwc 0 nfed: non fatal error detected this bit indicates status of non-fatal errors detected. this bit gets set if a non- fatal uncorrectable error is detected in the pci express port. errors are logged in this register regardless of whether er ror reporting is enab led or not in the device control register. 1: non fatal errors detected 0: no non-fatal errors detected 0rwc 0 ced: correctable error detected this bit indicates status of correctable errors detected. this bit gets set if a correctable error is detected in the pci express port. errors are logged in this register regardless of whether error reporting is enabled or not in the pci express device control register. 1: correctable errors detected 0: no correctable errors detected device: 0, 2-3 function: 0 offset: 76h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 76h version: intel 5000z chipset device: 4-7 function: 0 offset: 76h version: intel 5000p chipset bit attr default description
register description 146 intel ? 5000x chipset memory controller hub (mch) datasheet device: 0, 2-3 function: 0 offset: 78h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 78h version: intel 5000z chipset device: 4-7 function: 0 offset: 78h version: intel 5000p chipset bit attr default description 31:24 rwo if (port 0) {0h} elsif (port 2) {02h} elsif (port 3) {03h} elsif (port 4) {04h} elsif (port 5) {05h} elsif (port 6) {06h} elsif (port 7) {07h} endif pn: port number this field indicates the pci express por t number for the link and is initialized by software/bios. this will corre spond to the device number for each port. port 0- device number of 0 (esi) port 2 - device number of 2 port 3 - device number of 3 port 4 - device number of 4 port 5- device number of 5 port 6- device number of 6 port 7- device number of 7 23:18 rv 0h reserved. 17:15 ro 7h l1el: l1 exit latency this field indicates the l1 exit la tency for the given pci express port. it indicates the length of time this port requires to complete transition from l1 to l0. 000: less than 1s 001: 1 s to less than 2 s 010: 2 s to less than 4 s 011: 4 s to less than 8 s 100: 8 s to less than 16 s 101: 16 s to less than 32 s 110: 32 s to 64 s 111: more than 64us the intel 5000p chipset mch does not su pport l1 acceptable latency and is set to the maximum value for safety 14:12 ro 7h l0sel: l0s exit latency this field indicates the l0s exit latenc y (i.e l0s to l0) for the pci express port. 000: less than 64 ns 001: 64 ns to less than 128 ns 010: 128 ns to less than 256 ns 011: 256 ns to less than 512 ns 100: 512 ns to less than 1 s 101: 1 s to less than 2 s 110: 2 s to 4 s 111: more than 4 s note that intel 5000p chipset mch do es not support l0s exit latency implementation and for safety, this field is set to the maximum value.
intel ? 5000x chipset memory controller hub (mch) datasheet 147 register description ta b l e 3 - 3 5 shows various combining options for pci express ports. when ports combine, the control registers for the combined port revert to the lower numbered port. thus when ports 2 and 3 are combined, the combined x8 port is accessed through port 2 control registers. 11:10 ro 01 actpms: active state link pm support this field indicates the level of active state power management supported on the given pci express port. 00: disabled 01: l0s entry supported 10: reserved 11: l0s and l1 supported the intel 5000p chipset mch does not initiate l0s active state power management but it does permit a downst ream device from placing the link in l0s 9:4 ro if (port 0,1,3,5,7) {x4} elseif (port 2,6) {x8} elseif (port 4) {x16} endif mlw: maximum link width this field indicates the maximum wi dth of the given pci express link attached to the port. 000001: x1 000100: x4 001000: x8 010000: x16 others - reserved see ta b l e 3 - 3 5 . 3:0 ro 0001 mls: maximum link speed this field indicates the maximum link speed of the given pci express port. 0001: 2.5 gb/s others - reserved table 3-35. maximum link width default value for different pci express ports device/port maximum link width value 0,3,5,7 x4 000100 2,6 x8 001000 4 x16 010000 x8 001000 device: 0, 2-3 function: 0 offset: 78h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 78h version: intel 5000z chipset device: 4-7 function: 0 offset: 78h version: intel 5000p chipset bit attr default description
register description 148 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.11.7 pexlnkctrl[7:2, 0] - pci express link control register the pci express link control register controls the pci express link specific parameters. device: 0, 2-3 function: 0 offset: 7ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 7ch version: intel 5000z chipset device: 4-7 function: 0 offset: 7ch version: intel 5000p chipset bit attr default description 15:8 rv 00h reserved. 7rw 0 ext_synch: extended synch this bit when set forces the transmiss ion of 4096 fts ordered sets in the l0s state followed by a single skp ordered set prior to entering the l0 state, and the transmission of 1024 ts1 ordered sets in the l1 state prior to entering the recovery state. this mode provides ex ternal devices (for example, logic analyzers) monitoring the link time to achieve bit and symbol lock before the link enters the l0 or recovery states and resumes communication. 6rw 0 cccon : common clock configuration 0: indicates that this pci express port and its counterpart at the opposite end of the link are operating with an asynchronous reference clock . 1: indicates that this pci express por t and its counterpart at the opposite end of the link are operating with a distributed common reference clock . components utilize this common clock configuration information to report the correct l0s and l1 exit latencies. 5wo 0 rlnk: retrain link this bit, when set, initiates link retrai ning in the given pci express port. it consistently returns 0 when read. 4rw 0 lnkdis: link disable this field indicates whether the link associated with the pci express port is enabled or disabled. 0: enables the link associated with the pci express port 1: disables the link associated with the pci express port software should wait a minimum of 2 ms to make sure the link has entered the electrical idle state before clearing this bit. 3ro 0 rcb: read completion boundary this field defines the read completion boundary for the pci express port. defined encodings for rcb capabilities are: 0: 64 byte 1: 128 byte the intel 5000p chipset mch supports only 64 b read completion boundary and is hardwired to 0. 2rv 0 reserved.
intel ? 5000x chipset memory controller hub (mch) datasheet 149 register description 3.8.11.8 pexlnksts[7:2, 0] - pci express link status register the pci express link status register provid es information on the status of the pci express link such as negotiated width, training, and so forth. 1:0 rw 00 astpmctrl: active state link pm control this field controls the level of active state power management supported on the given pci express port. 00: disabled 01: l0s entry supported 10: reserved 11: l0s and l1 supported note: this has no effect on the intel 5000p chipset mch. device: 0, 2-3 function: 0 offset: 7ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 7ch version: intel 5000z chipset device: 4-7 function: 0 offset: 7ch version: intel 5000p chipset bit attr default description device: 0, 2-3 function: 0 offset: 7eh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 7eh version: intel 5000z chipset device: 4-7 function: 0 offset: 7eh version: intel 5000p chipset bit attr default description 15:13 rv 0h reserved. 12 rwo 1 sccon: slot clock configuration this bit indicates that the component us es the same physical reference clock that the platform provides on the connector. if the device uses an independent clock irrespective of the presence of a reference on the connector, this bit must be clear. 1: indicates same physical clock in the pci express connector as in the platform. 0: indicates independent clock on the pci express connector from that of the platform. the intel 5000p chipset mch initializes this bit to '1' because the expected state of the platform is to have one clock source shared between the intel 5000p chipset mch component and any down-d evices or slot connectors. it is the responsibility of bios to be aware of the real platform configuration, and clear this bit if the reference clocks differ.
register description 150 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.11.9 pexslotcap[7:2, 0] - pci express slot capabilities register the slot capabilities register identifies the pci express specific slot capabilities. 11 ro 0 lnktrg: link training this field indicates the status of an ong oing link training session in the current pci express port and is controlled by the hardware. 0: indicates that the ltssm is neither in ?configuration? nor ?recovery? states. 1: indicates link trai ning in progress (physical layer ltssm is in configuration or recovery state or the rlnk (retrain link) was set in section 3.8.11.7 but training has not yet begun. also refer to the bctrl.sbusreset for de tails on how the link training bit can be used for sensing hot-reset states. 10 ro 0 terr: training error this field indicates the occurrence of a link training error. 0: indicates no link training error occurred. 1: indicates link training error occurred. 9:4 ro 000100 nlnkwd: negotiated link width 1 this field indicates the negotiated width of the given pci express link after training is completed. only x1, x4, x8, and x16 link width nego tiations are possible in the intel 5000p chipset mch. refer to ta b l e 3 - 3 6 for the port and link width assignment after training is completed. 3:0 ro 1h lnkspd: link speed this field indicates the negotiated link speed of the given pci express link: 0001- 2.5 gb/s pci express link others - reserved notes: 1. the nlnkwd field is set to a default value correspondin g to x4 internally within the intel 5000p chipset mch. note that this field is a don?t care until training is completed for the link. software should not use this field to determine whether a link is up (enabled) or not. table 3-36. negotiated link width for di fferent pci express ports after training device/port negotiated link width value 2,3,4,5,6,7 x1 000001 0,2,3,4,5,6,7 x4 000100 2,4,6 x8 001000 1 notes: 1. ports 3, 5, and 7 report 000000 as appropriate. 4 x16 010000 2 2. ports 5, 6, and 7 report 000000 as appropriate. device: 0, 2-3 function: 0 offset: 7eh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 7eh version: intel 5000z chipset device: 4-7 function: 0 offset: 7eh version: intel 5000p chipset bit attr default description
intel ? 5000x chipset memory controller hub (mch) datasheet 151 register description device: 0, 2-3 function: 0 offset: 80h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 80h version: intel 5000z chipset device: 4-7 function: 0 offset: 80h version: intel 5000p chipset bit attr default description 31:19 rwo 0h psn: physical slot number this field indicates the physical slot number connected to the pci express port. it should be initialized to 0 for ports connected to devices that are either integrated on the system board or integrated within the same silicon such as the root port in intel 5000p chipset mch . 18:17 rv 0h reserved. 16:15 rwo 0h spls: slot power limit scale this field specifies the scale used for the slot power limit value. range of values: 00: 1.0x 01: 0.1x 10: 0.01x 11: 0.001x 14:7 rwo 00h splv: slot power limit value this field specifies the up per limit on power supplied by slot in conjunction with the slot power limit scale value defined previously. power limit (in watts) = spls x splv 6rwo 0h hpc: hot-plug capable this field defines hot-plug support cap abilities for the pci express port. 0: indicates that this slot is not capable of supporting hot-plug operations. 1: indicates that this slot is capable of supporting hot-plug operations 5ro 0h hps: hot-plug surprise this field indicates that a device in this slot may be removed from the system without prior notification. 0: indicates that hot-plug surprise is not supported 1: indicates that hot-plug surprise is supported the intel 5000p chipset mch does not support hot-plug surprise feature. 4rwo 0h pip: power indicator present this bit indicates that a power indicato r is implemented on th e chassis for this slot. 0: indicates that power indicator is not present 1: indicates that power indicator is present 3rwo 0h aip: attention indicator present this bit indicates that an attention i ndicator is implemented on the chassis for this slot. 0: indicates that an attention indicator is not present 1: indicates that an attention indicator is present
register description 152 intel ? 5000x chipset memory controller hub (mch) datasheet 2rwo 0h mrlsp: mrl sensor present this bit indicates that an mrl sensor is implemented on the chassis for this slot. 0: indicates that an mrl sensor is not present 1: indicates that an mrl sensor is present 1rwo 0h pcp: power controller present this bit indicates that a power contro ller is implemented on the chassis for this slot. 0: indicates that a power controller is not present 1: indicates that a power controller is present 0rwo 0h abp: attention button present this bit indicates that an attention bu tton is implemented on the chassis for this slot. 0: indicates that an attention button is not present 1: indicates that an attention button is present device: 0, 2-3 function: 0 offset: 80h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 80h version: intel 5000z chipset device: 4-7 function: 0 offset: 80h version: intel 5000p chipset bit attr default description
intel ? 5000x chipset memory controller hub (mch) datasheet 153 register description 3.8.11.10 pexslotctrl[7:2, 0] - pci express slot control register the slot control register identifies the pc i express specific slot control specific parameters for operations such as hot-plug and power management. software issues a command to a hot-plug capable port by issuing a write transaction that targets slot control register fields viz, pwrctrl, pwrl ed, atnled described below. a single write to the slot control register is considered to be a single command, even if the write affects more than one field in the slot control register. in response to this transaction, the port must carry out the requested actions and then set the associated status field (pexslots.cmdcmp) for the command completed event. the pexslotsts.cmdcmp bit will be set only when there is a uniqu e change to the state of the pwrctrl, pwrled, atnled in this register. device: 0, 2-3 function: 0 offset: 84h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 84h version: intel 5000z chipset device: 4-7 function: 0 offset: 84h version: intel 5000p chipset bit attr default description 15:11 rv 0h reserved. 10 rw 0h pwrctrl: power controller control this bit indicates the current state of the power applied to the slot of the pci express port . 0: power on 1: power off 9:8 rw 0h pwrled: power indicator control this bit indicates the current state of the power indicator of the pci express port 00: reserved . 01: on 10: blink (the intel 5000p chipset mch dr ives 1.5 hz square wave for chassis mounted leds in the case of legacy ca rd form factor for pci express devices) 11: off default is set to 11b (off) when this field is written, the in tel 5000p chipset mch sends appropriate power_indicator messages through the pci express port. for legacy card based pci express devices, the even t is signaled via the virtual pins 1 of the intel 5000p chipset mch, in addition. for pci express modules with advanced form factor that incorporate leds and onboard decoding logic, the pci express messages are interpreted directly (no virtual pins).
register description 154 intel ? 5000x chipset memory controller hub (mch) datasheet 7:6 rw 0h atnled: attention indicator control this bit indicates the current state of the attention indicator of the pci express port 00: reserved. 01: on 10: blink (the intel 5000p chipset mch drives 1.5 hz square wave) 11: off default is set to 11b (off) when this field is written, the inte l 5000p chipset mch sends appropriate attention_indicator messages through the pci express port. for legacy card based pci express devices, the event is signaled via the virtual pins of the intel 5000p chipset mch, in addi tion. for pci express modules with advanced form factor that incorporate leds and onboard decoding logic, the pci express messages are interpreted directly (no virtual pins). 5rw 0h hpinten: hot-plug interrupt enable this field enables the generation of hot-plug interrupts and events in the pci express port. 0: disables hot-plug events and interrupts 1: enables hot-plug events and interrupts 4rw 0h ccien: command completed interrupt enable this field enables the generation of hot-plug interrupts when a command is completed by the hot-plug controller connected to the pci express port 0: disables hot-plug interrupts on a command completion by a hot-plug controller. 1: enables hot-plug interrupts on a command completion by a hot-plug controller. 3rw 0h prsinten: presence detect changed enable this bit enables the generation of hot-pl ug interrupts or wake messages via a presence detect changed event. 0: disables generation of hot-plug interrupts or wake messages when a presence detect changed event happens. 1- enables generation of hot-plug interrupts or wake messages when a presence detect changed event happens. 2rw 0h mrlinten: mrl sensor changed enable this bit enables the generation of hot-pl ug interrupts or wake messages via a mrl sensor changed event. 0: disables generation of hot-plug interrupts or wake messages when an mrl sensor changed event happens. 1: enables generation of hot-plug interrupts or wake messages when an mrl sensor changed event happens. device: 0, 2-3 function: 0 offset: 84h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 84h version: intel 5000z chipset device: 4-7 function: 0 offset: 84h version: intel 5000p chipset bit attr default description
intel ? 5000x chipset memory controller hub (mch) datasheet 155 register description 3.8.11.11 pexslotsts[7:2, 0] - pci express slot status register the pci express slot status register defines important status information for operations such as hot-plug and power management. 1rw 0h pwrinten: power fault detected enable this bit enables the generation of hot-plug interrupts or wake messages via a power fault event. 0: disables generation of hot-plug interrupts or wake messages when a power fault event happens. 1: enables generation of hot-plug interrupts or wake messages when a power fault event happens. 0rw 0h atninten: attention button pressed enable this bit enables the generation of hot-pl ug interrupts or wake messages via an attention button pressed event. 0: disables generation of hot-plug in terrupts or wake messages when the attention button is pressed. 1: enables generation of hot-plug interrupts or wake messages when the attention button is pressed. device: 0, 2-3 function: 0 offset: 84h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 84h version: intel 5000z chipset device: 4-7 function: 0 offset: 84h version: intel 5000p chipset bit attr default description device: 0, 2-3 function: 0 offset: 86h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 86h version: intel 5000z chipset device: 4-7 function: 0 offset: 86h version: intel 5000p chipset bit attr default description 15:7 rv 0h reserved. 6ro 1h pds: presence detect state this field conveys the presence detect status determined via an in-band mechanism or through the present detect pins and shows the presence of a card in the slot. 0: slot empty 1: card present in slot
register description 156 intel ? 5000x chipset memory controller hub (mch) datasheet note that the assert_intx/assert_hpgpe messa ge is sent to esi port when any of the events defined in bits[4:0] (cmdcomp,p rsint, mrlsc, pwrint, abp) of the pexslotsts register are set provided the corresponding events in bits [4:0] of the section 3.8.11.10 and hpinten are enabled. software writes to clear these bits and mch will send a deassert_hpgpe message to esi port (wired-or). for the case when msi is enabled, any new event that sets these bits (e.g abp, prsint and so forth) will cause an msi message to be sent to the fsb for each occurrence. that is, each bit is considered unique. whereas in the case of legacy interrupts, a wired-or approach is used to mimic the level sensitive behavior and only one assert_intx/assert_gpe (deassert_intx/ deassert_gpe) is sent even when multiple in terrupt generating bits of the register get set. refer to figure 3-5 . 5ro 0h mrlss: mrl sensor state this bit reports the status of an mrl sensor if it is implemented. 0: mrl closed 1: mrl open 4rwc 0h cmdcomp: command completed this bit is set by the intel 5000p chipset mch when the hot-plug controller completes an issued command and is ready to accept a new command. it is subsequently cleared by software after the field has been read and processed. 3rwc 0h prsint: presence detect changed this bit is set by th e intel 5000p chipset mch when a presence detect changed event is detected. it is subsequently cleared by software after the field has been read and processed. 2rwc 0h mrlsc: mrl sensor changed this bit is set by the intel 5000p chipset mch w hen an mrl sensor changed event is detected. it is subsequently cl eared by software after the field has been read and processed. 1rwc 0h pwrint: power fault detected this bit is set by the intel 5000p chipset mch wh en a power fault event is detected by the power controller. it is subsequently cleared by software after the field has been read and processed. 0rwc 0h abp: attention button pressed this bit is set by the intel 5000p chipset mch when the attention button is pressed. it is subsequently cleared by software after the field has been read and processed. device: 0, 2-3 function: 0 offset: 86h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 86h version: intel 5000z chipset device: 4-7 function: 0 offset: 86h version: intel 5000p chipset bit attr default description
intel ? 5000x chipset memory controller hub (mch) datasheet 157 register description figure 3-5. pci express hot-plug interrupt flow n pexslotctrl[x]. hpinten = 1? y sw polls status (hpgpeen == 1) n intel? 5000p chipset sends msi per msiar and msidr pexhpint intel? 5000p chipset sends desassert_intx message via dmi when the respective bits of pexslotsts str cleared (wired- y intel? 5000p chipset sends assert_hpgpe message via dmi n hpgpeen msien output 1 x assert_hpgpe 0 1 msi 0 0 assert_intx intx disable x x 0 0 0 1 -- hpinten x 1 1 1 0 0 x x -- pexcmd[x].intx disable == 1? y (msictrl[x]. msien == 1) ? y n intel? 5000p chipset sends assert_intx message via dmi per intp intel? 5000p chipset sends desassert_hpgp e message via dmi when the when the respective bits pexslotsts str cleared (wired-or) or)
register description 158 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.11.12 pexrtctrl[7:2, 0] - pci express root control register the pci express root control register specifies parameters specific to the root complex port. device: 0, 2-3 function: 0 offset: 88h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 88h version: intel 5000z chipset device: 4-7 function: 0 offset: 88h version: intel 5000p chipset bit attr default description 15:4 rv 0h reserved. 3rw 0h pmeinten: pme interrupt enable this field controls the generati on of interrupts for pme messages. 1: enables interrupt generation upon receipt of a pme message as reflected in the pme status bit defined in the pexrtsts register. a pme interrupt is generated if the pmestatus register bit defined in section 3.8.11.13 , is set when this bit is set from a cleared state. 0: disables interrupt generation for pme messages. 2rw 0h sefeen: system error on fatal error enable this field controls generation of system errors in the pci express port hierarchy for fatal errors. 1: indicates that a system error should be generated if a fatal error (err_fatal) is reported by any of t he devices in the hierarchy associated with and including this pci express port. 0: no system error should be generated on a fatal error (err_fatal) reported by any of the devices in the hierarchy. 1rw 0h senfeen: system error on non-fatal error enable this field controls generation of system errors in the pci express port hierarchy for non-fatal errors. 1: indicates that a system error should be generated if a non-fatal error (err_nonfatal) is reported by any of the devices in the hierarchy associated with and including this pci express port. 0: no system error should be generated on a non-fatal error (err_nonfatal) reported by any of the devices in the hierarchy. 0rw 0h seceen: system error on correctable error enable this field controls generation of system errors in the pci express port hierarchy for correctable errors. 1: indicates that a system error should be generated if a correctable error (err_cor) is reported by any of the dev ices in the hierarchy associated with and including this pci express port 0: no system error should be generated on a correctable error (err_cor) reported by any of the devices in the hierarchy associated with and including this pci express port.
intel ? 5000x chipset memory controller hub (mch) datasheet 159 register description 3.8.11.13 pexrtsts[7:2, 0] - pci express root status register the pci express root status register specifies parameters specific to the root complex port. device: 0, 2-3 function: 0 offset: 8ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 8ch version: intel 5000z chipset device: 4-7 function: 0 offset: 8ch version: intel 5000p chipset bit attr default description 31:18 rv 0h reserved. 17 ro 0h pmepend: pme pending this field indicates that another pme is pending when the pme status bit is set. when the pme status bit is cleared by software; the pending pme is delivered by hardware by setting the pme status bit again and updating the requestor id appropriately. the pme pending bit is cleared by hardware if no more pmes are pending. note: the intel 5000p chipset mch can handle two outstanding pm_pme messages in its internal queues of the power management controller per port. if the downstream device issues more than 2 pm_pme messages successively, it will be dropped. 16 rwc 0h pmestatus: pme status 1 this field indicates status of a pme t hat is underway in the pci express port. 1: pme was asserted by a requester as indicated by the pmereqid field this bit is cleared by software by writing a ?1?. subsequent pmes are kept pending until the pme status is cleared. notes: 1. pmeinten defined in pexrtctrl ha s to be set for pm interrupts to be generated. for non-msi pm interrupts, the pmestatus bit in each of the pexrtsts [2:7] registers are wired or together and when set, the mch will send the ?assert_pmegpe? message to the intel 631xesb/632xes b i/o controller hub for power management. when all the bits are clear, it will send the ?dea ssert_pmegpe? message. pmeinten defined in pexrtctrl has to be set for pm interrupts to be generated. pm_pme events that generate msi will depend on the msien field in section 3.8.10.3 . refer to the pm interrupt flow in power management chapter. 15:0 ro 0000h pmereqid: pme requester id this field indicates the pci requester id of the last pme requestor.
register description 160 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.11.14 esictrl[0] - esi control register the esictrl register holds control informatio n and defeature bits pertaining to the esi interface for power management. 3.8.12 pci express advanced error reporting capability 3.8.12.1 pexenhcap[7:2, 0] - pci express enhanced capability header this register identifies the capability structure and points to the next structure. device: 0 function: 0 offset: d4h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:15 rv 0h reserved. 14 rw 1 dl23r: override l23 ready - recommend setting this bit to 1. 0: wait for pme_enter_l23 on all pcie* ports 1: do not wait for pme_enter_l23 on all pcie ports 13:12 rv 0 reserved 11 rwc 0 pte: pme_to_ack time expired 0: default mode, ?pme_to_ack? mess age received on all pci express ports before timeout. 1: signal that time expiration has occurred when the ptov field described below crosses the threshold in the intel 5000p chipset mch. 10:9 rw 0h ptov: pme_to_ack time out value 00: 1 ms (default) 01: 10 ms 10: 50 ms 11: reserved this register field provid es the timer limit for the intel 5000p chipset mch to keep track of the elapsed time from sending ?pme_turn_off? to receiving a ?pme_to_ack?. 8:4 rv 0h reserved. 3:0 rw 0h sac: stopgrant ack count this field tracks the number of stop gr ant acks received from the fsbs. the mch will forward the last stopgrantack received from the fsb to the intel 631xesb/632xesb i/o controller hub usin g the ?req_c2? command. software is expected to set this field to ?threads-1? where the variable ?thread? is the total number of logical threads present in the system (currently can handle up to 16). typically each cpu thread will issue a stopgrantack in response to a stpclk# assertion from the intel 631xesb/632xesb i/o controller hub. when the final stopgrantack is received from the fsb and the internal counter hits the value of sac+1 (which is equal to thread), the mch will initiate the ?req_c2? command on the dmi. it is illegal for the cpu to send more st op grant acks than that specified in the ?thread? variable. note: for sx power management in h/w or s/w mode
intel ? 5000x chipset memory controller hub (mch) datasheet 161 register description 3.8.12.2 uncerrsts[7:2] - uncorrectable error status this register identifies uncorrectable errors detected for the pci express port. if an error occurs and is unmasked in the de tect register (emsak_uncor_pex), the appropriate error bit will be recorded in this register. if an error is recorded in the uncerrsts register and the appropriate bi t (along with the severity bit of the uncerrsev register) determines which bi t in the pex_fat_ferr, pex_nf_cor_ferr, pex_fat_nerr, pex_nf_cor_nerr register ge ts recorded.these error log registers are described starting from section 3.8.12.24 . device: 0, 2-3 function: 0 offset: 100h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 100h version: intel 5000z chipset device: 4-7 function: 0 offset: 100h version: intel 5000p chipset bit attr default description 31:20 ro 140h ncapoff: next capability offset this field points to the next capab ility in extended configuration space. 19:16 ro 1h cv: capability version set to 1h for this version of the pci express logic 15:0 ro 0001h pexcapid: pci express extended cap_id assigned for advanced error reporting device: 2-3 function: 0 offset: 104h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 104h version: intel 5000z chipset device: 4-7 function: 0 offset: 104h version: intel 5000p chipset bit attr default description 31:21 rv 0h reserved 20 rwcst 0 io2err: received an unsupported request 19 rv 0 reserved 18 rwcst 0 io9err: malformed tlp status 17 rwcst 0 io10err: receiver buffer overflow status 16 rwcst 0 io8err: unexpected completion status 15 rwcst 0 io7err: completer abort status 14 rwcst 0 io6err: completion time-out status
register description 162 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.12.3 uncerrsts[0] - uncorrectab le error status for esi port this register identifies uncorrectable errors detected on esi port. if an error occurs and is unmasked in the detect register (emask _uncor_pex), the appropriate error bit will be recorded in this register. if an error is recorded in the uncerrsts register and the appropriate bit (along with the severity bit of the uncerrsev register) determines which bit in the pex_fat_ferr, pex_nf_cor_ferr, pex_fat_nerr, pex_nf_cor_nerr registers get recorded. th ese error log registers are described starting from section 3.8.12.24. 13 rwcst 0 io5err: flow control protocol error status 12 rwcst 0 io4err: poisoned tlp status 11:6 rv 0h reserved 5rwst 0 io19err: surprise link down error status 4rwcst 0 io0err: data link protocol error status 3:1 rv 0h reserved 0rwcst 0 io3err:training error status this field should not be used for obtaining training error status due to a recent pci express base specification , revision 1.0a errata dec 2003 to remove training error. device: 2-3 function: 0 offset: 104h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 104h version: intel 5000z chipset device: 4-7 function: 0 offset: 104h version: intel 5000p chipset bit attr default description device: 0 function: 0 offset: 104h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:22 rv 0h reserved 21 rwcst 0 io18err: esi reset time-out 20 rwcst 0 io2err: received an unsupported request 19 rv 0 reserved 18 rwcst 0 io9err: malformed tlp status 17 rwcst 0 io10err: receiver buffer overflow status 16 rwcst 0 io8err: unexpected completion status 15 rwcst 0 io7err: completer abort status 14 rwcst 0 io6err: completion time-out status 13 rwcst 0 io5err: flow control protocol error status 12 rwcst 0 io4err: poisoned tlp status
intel ? 5000x chipset memory controller hub (mch) datasheet 163 register description 3.8.12.4 uncerrmsk[7:2] - uncorrectable error mask this register masks uncorrectable errors from the uncerrsts[2:7] register from being signaled. 11:6 rv 0h reserved 5rwst 0 ioerr: surprise link down error status 4rwcst 0 io0err: data link protocol error status 3:1 rv 0h reserved 0rwcst 0 io3err:training error status note: this field should not be used for obtaining training error status due to a recent pci express base specification , revision 1.0a errata dec 2003 to remove training error. hardware behavior is undefined. device: 0 function: 0 offset: 104h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description device: 2-3 function: 0 offset: 108h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 108h version: intel 5000z chipset device: 4-7 function: 0 offset: 108h version: intel 5000p chipset bit attr default description 31:21 rv 0h reserved 20 rwst 0 io2msk: received an unsupported request 19 rv 0 reserved 18 rwst 0 io9msk: malformed tlp status 17 rwst 0 io10msk: receiver buffer overflow mask 16 rwst 0 io8msk: unexpected completion mask 15 rwst 0 io7msk: completer abort status 14 rwst 0 io6msk: completion time-out mask 13 rwst 0 io5msk: flow control protocol error mask 12 rwst 0 io4msk: poisoned tlp mask 11:6 rv 0h reserved 5rwst 0 io19msk: surprise link down error mask 4rwst 0 io0msk: data link layer protocol error mask 3:1 rv 000 reserved 0rwst 0 io3msk:training error mask note: this field should not be used for setting training error mask due to a recent pci express base specification , revision 1.0a errata dec 2003 to remove training error. hardware behavior is undefined.
register description 164 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.12.5 uncerrmsk[0] - uncorrec table error mask for esi port this register masks uncorrectable errors from the uncerrsts[0] register (esi port) from being signaled. 3.8.12.6 uncerrsev[0] - uncorrectable error severity for esi port this register indicates the severity of the un correctable errors for the esi port. an error is reported as fatal when the corresponding e rror bit in the severity register is set. if the bit is cleared, the corresponding error is considered non-fatal. if an error is recorded in the uncerrsts register, the co rresponding bit of uncerrsev determines if the error gets reflected as a device fatal or nonfatal error in the pex_fat_ferr, pex_nf_cor_ferr, pex_fat_nerr, pex_nf_cor_nerr registers. device: 0 function: 0 offset: 108h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:22 rv 0h reserved 21 rwst 0 io18msk: esi reset time-out 20 rwst 0 io2msk: received an unsupported request 19 rv 0 reserved 18 rwst 0 io9msk: malformed tlp status 17 rwst 0 io10msk: receiver buffer overflow mask 16 rwst 0 io8msk: unexpected completion mask 15 rwst 0 io7msk: completer abort status 14 rwst 0 io6msk: completion time-out mask 13 rwst 0 io5msk: flow control protocol error mask 12 rwst 0 io4msk: poisoned tlp mask 11:5 rv 0h reserved 5rwst 0 io19msk: surprise link down error mask 4rwst 0 io0msk: data link layer protocol error mask 3:1 rv 000 reserved 0rwst 0 io3msk:training error mask this field should not be used for setting training error mask due to a recent pci express base specification , revision 1.0a errata dec 2003 to remove training error. hardware behavior is undefined. device: 0 function: 0 offset: 10ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:22 rv 0h reserved 21 rwst 1 io18severity: esi reset time-out 20 rwst 0 io2severity: received an unsupported request 19 rv 0 reserved 18 rwst 1 io9severity: malformed tlp severity
intel ? 5000x chipset memory controller hub (mch) datasheet 165 register description 3.8.12.7 uncerrsev[7:2] - uncorrectable error severity this register indicates the severity of the unc orrectable errors. an error is reported as fatal when the corresponding error bit in the severity register is set. if the bit is cleared, the corresponding error is considered non-fatal. if an error is recorded in the uncerrsts register, the appropriate bit of uncerrsev determines if the error gets reflected as a device fatal or nonfatal e rror in the pex_fat_ferr, pex_nf_cor_ferr, pex_fat_nerr, pex_nf_cor_nerr registers. 17 rwst 1 io10severity: receiver buffer overflow severity 16 rwst 0 io8severity: unexpected completion severity 15 rwst 0 io7severity: completer abort status 14 rwst 0 io6severity: completion time-out severity 13 rwst 1 io5severity: flow control protocol error severity 12 rwst 0 io4severity: poisoned tlp severity 11:6 rv 0h reserved 5rwst 0 io19 severity: surprise link down severity 4rwst 1 io0severity: data link protocol error severity (see figure 3-17 in pci express base specification , revision 1.0a) 3:1 rv 000 reserved 0rwst 1 io3severity:training error severity this field should not be used for setting training error severity due to a recent pci express base specification , revision 1.0a errata dec 2003 to remove training error. hardware behavior is undefined. device: 0 function: 0 offset: 10ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description device: 2-3 function: 0 offset: 10ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 10ch version: intel 5000z chipset device: 4-7 function: 0 offset: 10ch version: intel 5000p chipset bit attr default description 31:21 rv 0h reserved 20 rwst 0 io2severity: received an unsupported request 19 rv 0 reserved 18 rwst 1 io9severity: malformed tlp severity 17 rwst 1 io10severity: receiver buffer overflow severity 16 rwst 0 io8severity: unexpected completion severity 15 rwst 0 io7severity: completer abort status
register description 166 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.12.8 corerrsts[7:2, 0] - correctable error status this register identifies which unmasked corre ctable error has been detected. the error is directed to the respective device correctable error bit in the pex_nf_cor_ferr, pex_nf_cor_nerr registers (if the error is unmasked in the corerrmsk register defined in section 3.8.12.9 ). these registers are discussed starting from section 3.8.12.25 . 14 rwst 0 io6severity: completion time-out severity 13 rwst 1 io5severity: flow control protocol error severity 12 rwst 0 io4severity: poisoned tlp severity 11:6 rv 0h reserved 5rwst 0 io19severity: surprise link down severity 4rwst 1 io0severity: data link protocol error severity (see figure 3-17 in pci express base specification , revision 1.0a) 3:1 rv 000 reserved 0rwst 1 io3severity:training error severity this field should not be used for setting training error severity due to a recent pci express base specification , revision 1.0a errata dec 2003 to remove training error. hardware behavior is undefined. device: 2-3 function: 0 offset: 10ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 10ch version: intel 5000z chipset device: 4-7 function: 0 offset: 10ch version: intel 5000p chipset bit attr default description device: 0, 2-3 function: 0 offset: 110h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 110h version: intel 5000z chipset device: 4-7 function: 0 offset: 110h version: intel 5000p chipset bit attr default description 31:13 rv 0h reserved 12 rwcst 0 io16err: replay timer time-out status 11:9 rv 0h reserved 8rwcst 0 io15err: replay_num rollover status
intel ? 5000x chipset memory controller hub (mch) datasheet 167 register description 3.8.12.9 corerrmsk[7:2, 0] - correctable error mask this register masks correctable errors from being signalled. they are still logged in the corerrsts register. 3.8.12.10 aerrcapctrl[7:2, 0] - advan ced error capabilities and control register this register identifies the capability structure and points to the next structure. 7rwcst 0 io14err: bad dllp status 6rwcst 0 io13err: bad tlp status 5:1 rv 0h reserved 0rwcst 0 io12err: receiver error status device: 0, 2-3 function: 0 offset: 110h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 110h version: intel 5000z chipset device: 4-7 function: 0 offset: 110h version: intel 5000p chipset bit attr default description device: 0, 2-3 function: 0 offset: 114h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 114h version: intel 5000z chipset device: 4-7 function: 0 offset: 114h version: intel 5000p chipset bit attr default description 31:13 rv 0h reserved 12 rwst 0 io16msk: replay timer time-out mask 11:9 rv 0h reserved 8rwst 0 io15msk: replay_num rollover mask 7rwst 0 io14msk: bad dllp mask 6rwst 0 io13msk: bad tlp mask 5:1 rv 0h reserved 0rwst 0 io12msk: receiver error mask
register description 168 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.12.11 hdrlog0[7:2, 0] - header log 0 this register contains the first 32 bits of the header log locked down when the first uncorrectable error occurs. headers of the subsequent errors are not logged. 3.8.12.12 hdrlog1[7:2, 0] - header log 1 this register contains the second 32 bits of the header log. device: 0, 2-3 function: 0 offset: 118h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 118h version: intel 5000z chipset device: 4-7 function: 0 offset: 118h version: intel 5000p chipset bit attr default description 31:9 rv 0h reserved 8ro 0 ecrcchken: ecrc check enable this bit when set enables ecrc checking. 7ro 0 ecrcchkcap: ecrc check capable intel 5000p chipset mch does not support ecrc. 6ro 0 ecrcgenen: ecrc generation enable intel 5000p chipset mch does not generate ecrc. 5ro 0 ecrcgencap: ecrc generation capable intel 5000p chipset mch does not generate ecrc. 4:0 rost 0h ferrptr: first error pointer the first error pointer is a read-only regi ster that identifies the bit position of the first error reported in the uncorrectable error status register. left most error bit if multiple bits occurred simultaneously. device: 0, 2-3 function: 0 offset: 11ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 11ch version: intel 5000z chipset device: 4-7 function: 0 offset: 11ch version: intel 5000p chipset bit attr default description 31:0 rost 0h hdrlogdw0: header of tlp (dword 0) associated with first uncorrectable error
intel ? 5000x chipset memory controller hub (mch) datasheet 169 register description 3.8.12.13 hdrlog2[7:2, 0] - header log 2 this register contains the third 32 bits of the header log. 3.8.12.14 hdrlog3[7:2, 0] - header log 3 this register contains the fourth 32 bits of the header log. device: 0, 2-3 function: 0 offset: 120h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 120h version: intel 5000z chipset device: 4-7 function: 0 offset: 120h version: intel 5000p chipset bit attr default description 31:0 rost 0h hdrlogdw1: header of tlp (dword 1) associated with error device: 0, 2-3 function: 0 offset: 124h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 124h version: intel 5000z chipset device: 4-7 function: 0 offset: 124h version: intel 5000p chipset bit attr default description 31:0 rost 0h hdrlogdw2: header of tlp (dword 2) associated with error device: 0, 2-3 function: 0 offset: 128h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 128h version: intel 5000z chipset device: 4-7 function: 0 offset: 128h version: intel 5000p chipset bit attr default description 31:0 rost 0h hdrlogdw3: header of tlp (dword 3) associated with error
register description 170 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.12.15 rperrcmd[7:2, 0] - root port error command this register controls behavior upon detection of errors. 3.8.12.16 rperrsts[7:2, 0] - root error status register the root error status register reports status of error messages (err_cor, err_nonfatal, and err_fatal) received by the root complex in the mch, and errors detected by the root port itself (which are treated conceptually as if the root port had sent an error message to itself). the err_nonfatal and err_fatal messages are grouped together as uncorrectable. each co rrectable and uncorrectable (non-fatal and fatal) error source has a first error bit and a next error bit associated with it respectively. when an error is received by a root complex, the respective first error bit is set and the requestor id is logged in the error source identification register. a set individual error status bit indicates that a particular error category occurred; software may clear an error status by writing a 1 to th e respective bit. if software does not clear the first reported error before another error message is received of the same category (correctable or uncorrectable), the correspon ding next error status bit will be set but the requestor id of the subsequent error me ssage is discarded. the next error status bit may be cleared by software by writing a 1 to the respective bit as well. this register is updated regardless of the settings of the root control register in section 3.8.11.12 and the root error command register defined in section 3.8.12.15 . device: 0, 2-3 function: 0 offset: 12ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 12ch version: intel 5000z chipset device: 4-7 function: 0 offset: 12ch version: intel 5000p chipset bit attr default description 31:8 rv 0h reserved 7:3 rv 0h reserved 2 rw 0 en_fat_err: fatal error reporting enable enable interrupt on fatal errors when set. 1 rw 0 en_nonfat_err: non-fatal error reporting enable enable interrupt on a non-fatal (uncorrectable) error when set 0 rw 0 en_corr_err: correctable error reporting enable enable interrupt on correctable errors when set
intel ? 5000x chipset memory controller hub (mch) datasheet 171 register description 3.8.12.17 rperrsid[7:2, 0] - error source identification register the error source identification register iden tifies the source (requestor id) of first correctable and uncorrectable (non-fatal/fatal) errors reported in the root error status register defined in section 3.8.12.16 . this register is updated regardless of the settings of the root control register defined in section 3.8.11.12 and the root error command register defined in. section 3.8.12.15 . device: 0, 2-3 function: 0 offset: 130h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 130h version: intel 5000z chipset device: 4-7 function: 0 offset: 130h version: intel 5000p chipset bit attr default description 31:27 ro 0h adverr_int_msg_num: advanced error interrupt message number advanced error interrupt message number offset between base message data an the msi message if assigned more than one message number to be used of any status in this capability. 26:7 rv 0h reserved 6rwcst 0 fat_err_rcvd: fatal error messages received set when one or more fatal uncorrectable error messages 1 have been received. notes: 1. this applies to both internal generated root port errors and those messages received from an external source. 5rwcst 0 nfat_err_rcvd : non-fatal error messages received set when one or more non-fatal uncorrectable error messages have been received. 4rwcst 0 frst_uncor_fatal: first uncorrectable fatal set when the first uncorrectable error message (which is fatal) is received. 3rwcst 0 mult_err_nofat_err: multiple err_fatal no fatal_received set when either a fatal or a non-fatal error message is received and err_fat_nonfat_rcvd is already set, i.e log from the 2nd fatal or no fatal error message onwards 2rwcst 0 err_fat_nofat_rcvd: error fatal nofatal received set when either a fatal or a non-fatal error message is received and this bit is already not set. that is, log the first error message 1rwcst 0 mult_err_cor_rcvd: multiple correctable error received set when either a correctable error message is received and err_corr_rcvd is already set, i.e log from the 2nd correctable error message onwards 0rwcst 0 err_corr_rcvd: first correctable error received set when a correctable error message is received and this bit is already not set. that is, log the first error message
register description 172 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.12.18 intel 5000p chipset mch spcapi d[7:2, 0] - mch specific capability id this register identifies the capability structure and points to the next structure. 3.8.12.19 pex_err_docmd[7:2, 0] - pci express error do command register link error commands for doing the various signaling: err[2:0] and mcerr. device: 0, 2-3 function: 0 offset: 134h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 134h version: intel 5000z chipset device: 4-7 function: 0 offset: 134h version: intel 5000p chipset bit attr default description 31:16 rost 0h err_fat_nofat_sid: fatal no fatal error source id requestor id of the source when an fatal or no fatal error is received and the err_fat_nofat_rcvd bit is not already set. i.e log id of the first fatal or non fatal error 15:0 rost 0h err_corr_sid: correctable error source id requestor id of the source when a correctable error is received and the err_corr_rcvd is not already set. i.e log id of the first correctable error. device: 0, 2-3 function: 0 offset: 140h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 140h version: intel 5000z chipset device: 4-7 function: 0 offset: 140h version: intel 5000p chipset bit attr default description 31:20 ro 0h nxtcapoff: next capability offset this field points to the next capability in extended configur ation space. it is set 000h since this is the final structure in the chain. 19:16 ro 0h vn: version number version number for this capability structure. 15:0 ro 0h extcapid: extended cap_id
intel ? 5000x chipset memory controller hub (mch) datasheet 173 register description 3.8.12.20 emask_uncor_pex[0] - uncorrectable error detect mask for esi this register masks (blocks) the detection of the selected error bits for the esi port. when a specific error is blocked, it does not get reported or logged. device: 0, 2-3 function: 0 offset: 144h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 144h version: intel 5000z chipset device: 4-7 function: 0 offset: 144h version: intel 5000p chipset bit attr default description 31:8 rv 0h reserved . 7:6 rw 00 pex_rp_fat_map: root port steering for fatal errors 00: err[0] 01: err[1] 10: err[2] 11: mcerr the root port fatal errors are routed to one of the err[2:0] pins or mcerr. 5:4 rw 00 pex_rp_nf_map: root port st eering for non-fatal errors 00: err[0], 01: err[1] 10: err[2] 11: mcerr the root port non fatal (uncorrectable) errors are routed to one of the err[2:0] pins or mcerr. 3:2 rw 00 pex_rp_corr_map: root port st eering for correctable errors 00: err[0], 01: err[1] 10: err[2] 11: mcerr the root port correctable errors are routed to one of the err[2:0] pins or mcerr. 1:0 rw 00 pex_dev_unsup_map: report steering for unsupported request errors (master aborts) for legacy devices. 00: err[0] 01: err[1] 10: err[2] 11: mcerr unsupported request error report enable is in the device control register. this is error io2.
register description 174 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.12.21 emask_uncor_pex[7:2] - uncorrectable error detect mask this register masks (blocks) the detection of the selected error bits. when a specific error is blocked, it does not get reported or logged. device: 0 function: 0 offset: 148h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:22 rv 0h reserved 21 rw 0 io18dmirstdetmsk: esi reset time-out 20 rw 0 io2detmsk: received an unsupported request 19 rv 0 reserved 18 rw 0 io9detmsk: malformed tlp status 17 rw 0 io10detmsk: receiver buffer overflow status 16 rw 0 io8detmsk: unexpected completion status 15 rw 0 io7detmsk: completer abort status 14 rw 0 io6detmsk: completion time-out status 13 rw 0 io5detmsk: flow control protocol error status 12 rw 0 io4detmsk: poisoned tlp status 11:5 rv 0h reserved 4rw 0 io0detmsk: data link protocol error status 3:1 rv 0h reserved 0rw 0 io3detmsk: training error status this field should not be used for setting training error severity due to a recent pci-sig ecn (jan 22, 04) to remove training error. hardware behavior is undefined. device: 2-3 function: 0 offset: 148h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 148h version: intel 5000z chipset device: 4-7 function: 0 offset: 148h version: intel 5000p chipset bit attr default description 31:21 rv 0h reserved 20 rw 0 io2detmsk: received an unsupported request 19 rv 0 reserved 18 rw 0 io9detmsk: malformed tlp status 17 rw 0 io10detmsk: receiver buffer overflow status 16 rw 0 io8detmsk : unexpected completion status
intel ? 5000x chipset memory controller hub (mch) datasheet 175 register description 3.8.12.22 emask_cor_pex[7:2, 0] - correctable error detect mask this register masks (blocks) the detection of the selected bits. normally all are detected. but software can choose to disable detecting any of the error bits. 15 rw 0 io7detmsk: completer abort status 14 rw 0 io6detmsk : completion time-out status 13 rw 0 io5detmsk: flow control protocol error status 12 rw 0 io4detmsk: poisoned tlp status 11:6 rv 0h reserved 5 rw 0 io19detmsk: surprise link down mask 4rw 0 io0detmsk: data link protocol error status 3:1 rv 0h reserved 0rw 0 io3detmsk: training error status this field should not be used for setting training error severity due to a recent pci-sig ecn (jan 22, 04) to remove training error. hardware behavior is undefined. device: 2-3 function: 0 offset: 148h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 148h version: intel 5000z chipset device: 4-7 function: 0 offset: 148h version: intel 5000p chipset bit attr default description device: 0, 2-3 function: 0 offset: 14ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 14ch version: intel 5000z chipset device: 4-7 function: 0 offset: 14ch version: intel 5000p chipset bit attr default description 31:13 rv 0h reserved 12 rw 0 io16detmsk: replay timer time-out mask 11:9 rv 0h reserved 8rw 0 io15detmsk: replay_num rollover mask 7rw 0 io14detmsk: bad dllp mask 6rw 0 io13detmsk: bad tlp mask 5:1 rv 0h reserved
register description 176 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.12.23 emask_rp_pex[7:2, 0] - root port error detect mask this register masks (blocks) the detection of the selected bits associated with the root port errors. normally, all are detected. 3.8.12.24 pex_fat_ferr[7:2, 0] - pci express first fatal error register this register records the occurrence of th e first unmasked pci express fatal errors and written by the mch if the respective bits are not set prior. the classification of uncorrectable errors into fatal is based on the severity level of the uncerrsev register described in section 3.8.12.7 . 0rw 0 io12detmsk: receiver error mask device: 0, 2-3 function: 0 offset: 14ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 14ch version: intel 5000z chipset device: 4-7 function: 0 offset: 14ch version: intel 5000p chipset bit attr default description device: 0, 2-3 function: 0 offset: 150h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 150h version: intel 5000z chipset device: 4-7 function: 0 offset: 150h version: intel 5000p chipset bit attr default description 31:3 rv 0h reserved 2rw 0 io1detmsk: fatal message detect mask 1rw 0 io11detmsk: uncorrectable message detect mask 0rw 0 io17detmsk: correctable message detect mask
intel ? 5000x chipset memory controller hub (mch) datasheet 177 register description 3.8.12.25 pex_nf_cor_ferr[7:2, 0] - pci express first non-fatal or correctable error register this register records the occurrence of the first unmasked pci express non-fatal (uncorrectable) and correctable errors. these errors are written by the mch if the respective bits are not set prior. the classification of uncorrectable errors into fatal or non-fatal is based on the uncerrsev register described in section 3.8.12.7 . device: 0, 2-3 function: 0 offset: 154h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 154h version: intel 5000z chipset device: 4-7 function: 0 offset: 154h version: intel 5000p chipset bit attr default description 31:13 rv 0h reserved 12 rwcst 0 first_fat_err_io19: surprise link down status 11 rwcst 0 first_fat_err_io18 : esi reset time-out 10 rwcst 0 first_fat_err_io9: pex - malformed tlp 9rwcst 0 first_fat_err_io10: pex - receive buffer overflow error 8rwcst 0 first_fat_err_io8: pex - unexpected completion error 7rwcst 0 first_fat_err_io7: pex - completer abort 6rwcst 0 first_fat_err_io6: pex - completion timeout 5rwcst 0 first_fat_err_io5: pex - flow control protocol error 4rwcst 0 first_fat_err_io4: pex - poisoned tlp 3rwcst 0 first_fat_err_io3: pex - training error this field should not be used for setti ng training error severity due to a recent pci-sig ecn (jan 22, 04) to remove training error. hardware behavior is undefined. 2rwcst 0 first_fat_err_io2: pex - received unsupported request 1rwcst 0 first_fat_err_io1: pex - received fatal error message 0rwcst 0 first_fat_err_io0: pex - data link layer protocol error
register description 178 intel ? 5000x chipset memory controller hub (mch) datasheet . 3.8.12.26 pex_fat_nerr[7:2, 0] - pci express next fatal error register this register records the subsequent occu rrences after the first unmasked pci express fatal errors and written by the mch if the respective bits are set in the pex_ferr_fat register. device: 0, 2-3 function: 0 offset: 158h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 158h version: intel 5000z chipset device: 4-7 function: 0 offset: 158h version: intel 5000p chipset bit attr default description 31:18 rv 0h reserved 17 rwcst 0 first_nfat_corr_err_io19: su rprise link down (uncorrectable) 16 rwcst 0 first_nfat_cor_err_io17: pex - received correctable error message 15 rwcst 0 first_nfat_cor_err_io16: pex - replay timer timeout (correctable) 14 rwcst 0 first_nfat_cor_err_io15: pex - replay_num rollover (correctable) 13 rwcst 0 first_nfat_cor_err_io14: pex - bad dllp error (correctable) 12 rwcst 0 first_nfat_cor_err_io13: pex - bad tlp error (correctable) 11 rwcst 0 first_nfat_cor_err_io12: pex - receiver error (correctable) 10 rwcst 0 first_nfat_cor_err_io11: pex - received non fatal (uncorrectable) error message 9rwcst 0 first_nfat_cor_err_io10: pex - receive buffer overflow error (uncorrectable) 8rwcst 0 first_nfat_cor_err_io9: pex -malformed tlp (uncorrectable) 7rwcst 0 first_nfat_cor_err_io8: pex - unexpected completion error (uncorrectable) 6rwcst 0 first_nfat_cor_err_io7: pex - completer abort (uncorrectable) 5rwcst 0 first_nfat_cor_err_io6: pex - completion timeout (uncorrectable) 4rwcst 0 first_nfat_cor_err_io5: pex - flow control protocol error (uncorrectable) 3rwcst 0 first_nfat_cor_err_io4: pex - poisoned tlp (uncorrectable) 2rwcst 0 first_nfat_cor_err_io3: pex - training error (uncorrectable) this field should not be used for setti ng training error severity due to a recent pci-sig ecn (jan 22, 04) to remove training error. hardware behavior is undefined. 1rwcst 0 first_nfat_cor_err_io2: pex - received unsupported request (uncorrectable) 0rwcst 0 first_nfat_cor_err_io0: pex - data link layer protocol error (uncorrectable)
intel ? 5000x chipset memory controller hub (mch) datasheet 179 register description 3.8.12.27 pex_nf_cor_nerr[7:2, 0] - pci express non fatal or correctable next error register these errors are written by the mch if the respective bits are set in pex_nf_cor_ferr register. this register records the subsequent occurrences of unmasked pci express non-fatal (uncorrectable) and correctable errors. device: 0, 2-3 function: 0 offset: 15ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 15ch version: intel 5000z chipset device: 4-7 function: 0 offset: 15ch version: intel 5000p chipset bit attr default description 31:13 rv 0h reserved 12 rwcst 0 next_fat_err_io19: surprise link down 11 rwcst 0 next_fat_err_io18: esi reset time-out 10 rwcst 0 next_fat_err_io9: pex - malformed tlp 9rwcst 0 next_fat_err_io10: pex - receive buffer overflow error 8rwcst 0 next_fat_err_io8 : pex - unexpected completion error 7rwcst 0 next_fat_err_io7: pex - completer abort 6rwcst 0 next_fat_err_io6: pex - completion timeout 5rwcst 0 next_fat_err_io5 : pex - flow control protocol error 4rwcst 0 next_fat_err_io4: pex - poisoned tlp 3rwcst 0 next_fat_err_io3 : pex - training error this field should not be used for setti ng training error severity due to a recent pci-sig ecn (jan 22, 04) to remove training error. hardware behavior is undefined. 2rwcst 0 next_fat_err_io2: pex - received unsupported request 1rwcst 0 next_fat_err_io1 : pex - received fatal error message 0rwcst 0 next_fat_err_io0: pex - data link layer protocol error
register description 180 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.12.28 pex_unit_ferr[7:2, 0] - pc i express first unit error register this register records the occurrence of the first unit errors that are specific to this pci express port caused by external activities. for example, vpp error due to a malfunctioning port on the smbus that did not receive acknowledge due to a pci express hot-plug event. the unit errors are sent to the coherency engine to classify as to which port cluster it came from ports 2-3 or ports 4-7 and the errors are recorded in coherency engine and appropriate interrupts generated through err pins. device: 0, 2-3 function: 0 offset: 160h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 160h version: intel 5000z chipset device: 4-7 function: 0 offset: 160h version: intel 5000p chipset bit attr default description 31:18 rv 0h reserved 17 rwst 0 next_nfat_corr_err_io19: surprise link down 16 rwcst 0 next_nfat_cor_err_io17: pex - received correctable error message 15 rwcst 0 next_nfat_cor_err_io16: pex - replay timer timeout (correctable) 14 rwcst 0 next_nfat_cor_err_io15: pex - replay_num rollover (correctable) 13 rwcst 0 next_nfat_cor_err_io14: pex - bad dllp error (correctable) 12 rwcst 0 next_nfat_cor_err_io13: pex - bad tlp error (correctable) 11 rwcst 0 next_nfat_cor_err_io12: pex - receiver error (correctable) 10 rwcst 0 next_nfat_cor_err_io11: pex - received non fatal (uncorrectable) error message 9rwcst 0 next_nfat_cor_err_io10: pex - receive buffer overflow error (uncorrectable) 8rwcst 0 next_nfat_cor_err_io9: pex -malformed tlp (uncorrectable) 7rwcst 0 next_nfat_cor_err_io8: pex - unexpected completion error (uncorrectable) 6rwcst 0 next_nfat_cor_err_io7: pex - completer abort (uncorrectable) 5rwcst 0 next_nfat_cor_err_io6: pex - completion timeout (uncorrectable) 4rwcst 0 next_nfat_cor_err_io5: pex - flow control protocol error (uncorrectable) 3rwcst 0 next_nfat_cor_err_io4: pex - poisoned tlp (uncorrectable) 2rwcst 0 next_nfat_cor_err_io3: pex - training error (uncorrectable) this field should not be used for setti ng training error severity due to a recent pci-sig ecn (jan 22, 04) to remove training error. hardware behavior is undefined. 1rwcst 0 next_nfat_cor_err_io2: pex - received unsupported request (uncorrectable) 0rwcst 0 next_nfat_cor_err_io0: pex - data link layer protocol error (uncorrectable)
intel ? 5000x chipset memory controller hub (mch) datasheet 181 register description . 3.8.12.29 pex_unit_nerr[7:2] - pci express next unit error register this register records the occurrence of subseq uent unit errors that are specific to this pci express port caused by external activities. for example, vpp error due to a malfunctioning port on the smbus that di d not receive acknowledge due to a pci express hot-plug event. the next unit errors are sent to the coherency engine where the errors are further recorded and appropriate interrupts are generated through err pins. . 3.8.12.30 pex_sserr[7:2,0]: pci express stop and scream error register this register records the occurrence of stop and scream error due to data poisoning. device: 2-3 function: 0 offset: 168h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 168h version: intel 5000z chipset device: 4-7 function: 0 offset: 168h version: intel 5000p chipset bit attr default description 31:1 rv 0h reserved 0rwcst 0 first_fat_vpp_err: vpp error for pci express port records the occurrence of the first vpp error if this bit is not set prior. software clears this when the error has been serviced. device: 2-3 function: 0 offset: 16ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 16ch version: intel 5000z chipset device: 4-7 function: 0 offset: 16ch version: intel 5000p chipset bit attr default description 31:1 rv 0h reserved 0rwcst 0 next_fat_vpp_err: vpp error for pci express port records the occurrence of subsequent vpp errors after the pex_unit_ferr.first_fat_vp_err is set. software clears this when the error has been serviced.
register description 182 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.13 error registers this section describes the registers that record the first and next errors, logging, detection masks, signalling masks, and erro r injection control. the ferr_global (first error register) is used to record the first error condition. the nerr_global register is used to record subsequent errors. the contents of ferr_global and nerr_glob al are ?sticky? across a reset (while pwrgood remains asserted). this provid es the ability for firmware to perform diagnostics across reboots. note that only the contents of ferr_global affects the update of the any error log registers. 3.8.13.1 ferr_global - global first error register the first fatal and/or first non-fatal errors are flagged in the ferr_global register, subsequent errors are indicated in the nerr_global register. 3.8.13.2 nerr_global - global next error register once an error has been logged in the ferr_ global, subsequent errors are logged in the nerr_global register. . device: 7-2, 0 function: 0 offset: 170h bit attr default description 7:1 rv 0h reserved 0rwcst 0 sserr: stop and scream error for pci express port records the occurrence of the first stop and scream error on the pci express port if this bit is clear. device: 16 function: 2 offset: 44h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31 rwcst 0 global_nerr_31: internal fatal error 30 rwcst 0 global_nerr_30: dma engine device fatal error 29 rwcst 0 global_nerr_29: fsb1 fatal error 28 rwcst 0 global_nerr_28: fsb 0 fatal error 27:25 rv 0 reserved 24 rwcst 0 global_nerr_24: fb-dimm channel 0,1,2 or 3 fatal error 23 rwcst 0 global_nerr_23: pci express device 7 fatal error 22 rwcst 0 global_nerr_22: pci express device 6 fatal error
intel ? 5000x chipset memory controller hub (mch) datasheet 183 register description 21 rwcst 0 global_nerr_21: pci express device 5 fatal error 20 rwcst 0 global_nerr_20: pci express device 4 fatal error 19 rwcst 0 global_nerr_19: pci express device 3 fatal error 18 rwcst 0 global_nerr_18: pci express device 2 fatal error 17 rv 0 reserved 16 rwcst 0 global_nerr_16: esi fatal error 15 rwcst 0 global_nerr_15: internal intel 5000p chipset mch non-fatal error 14 rwcst 0 global_nerr_14: dma engine device non fatal error 13 rwcst 0 global_nerr_13: fsb1 non-fatal error 12 rwcst 0 global_nerr_12: fsb 0 non-fatal error 11:9 rv 0h reserved 8rwcst 0 global_nerr_08: fb-dimm channel 0,1, 2 or 3 non-fatal error 7rwcst 0 global_nerr_07: pci express device 7 non-fatal error 6rwcst 0 global_nerr_06: pci express device 6 non-fatal error 5rwcst 0 global_nerr_05: pci express device 5 non-fatal error 4rwcst 0 global_nerr_04: pci express device 4 non-fatal error 3rwcst 0 global_nerr_03: pci express device 3 non-fatal error 2rwcst 0 global_nerr_02: pci express device 2 non-fatal error 1rv 0reserved 0rwcst 0 global_nerr_00: esi non-fatal error device: 16 function: 2 offset: 44h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description
register description 184 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.13.3 ferr_fat_fsb[1:0]: fsb first fatal error register 3.8.13.4 ferr_nf_fsb[1:0]: fsb first non-fatal error register 3.8.13.5 nerr_fat_fsb[1:0]: fsb next fatal error register this register logs all fsb subsequent erro rs after the ferr_fat_fsb has logged the 1st fatal error. . 3.8.13.6 nerr_nf_fsb[1:0]: fsb next non-fatal error register this register logs all fsb subsequent errors after the ferr_nf_fsb has logged the 1st fatal error. device: 16 function: 0 offset: 480h, 180h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7:6 rv 00 reserved 5rwcst 0 f9err: fsb protocol error 4 rv 0h reserved 3rwcst 0 f2err: unsupported processor bus transaction 2:1 rv 0h reserved 0rwcst 0 f1err: request/address parity error device: 16 function: 0 offset: 481h, 181h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7:3 rv 00000 reserved 2rwcst 0 f7err: detected mcerr from a processor 1rwcst 0 f8err: detected binit from a processor 0rwcst 0 f6err: parity error in data from fsb interface device: 16 function: 0 offset: 482h, 182h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7:6 rv 00 reserved 5rwcst 0 f9err: fsb protocol error 4 rv 0h reserved 3rwcst 0 f2err: unsupported processor bus transaction 2:1 rv 0h reserved 0rwcst 0 f1err: request/address parity error
intel ? 5000x chipset memory controller hub (mch) datasheet 185 register description . 3.8.13.7 nrecfsb[1:0]: non recoverable fsb error log register fsb log registers for non recoverable errors when a fatal error is logged in its corresponding ferr_fat_fsb register. 3.8.13.8 recfsb[1:0]: recoverable fsb error log register the following error log registers captures the fsb fields on the logging of an error in the corresponding ferr_nf_fsb register. device: 16 function: 0 offset: 483h, 183h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7:3 rv 00000 reserved 2rwcst 0 f7err: detected mcerr from a processor 1rwcst 0 f8err: detected binit from a processor 0rwcst 0 f6err: parity error in data from fsb interface device: 16 function: 0 offset: 484h, 184h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:29 rv 000 reserved 28:24 rost 00000 reqa: reqa[4:0] fields of the fsb 23:21 rost 000 reqb: reqb[2:0] fields of the fsb 20:16 rost 00000 exf: exf[4:0] fields of the fsb 15:8 rost 00h attr: attr[7:0] fields of the fsb 7:0 rost 00h did: did[7:0] fields of the fsb device: 16 function: 0 offset: 488h, 188h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:29 rv 000 reserved 28:24 rost 00000 reqa: reqa[4:0] fields of the fsb 23:21 rost 000 reqb: reqb[2:0] fields of the fsb 20:16 rost 00000 exf: exf[4:0] fields of the fsb 15:8 rost 00h attr : attr[7:0] fields of the fsb 7:0 rost 00h did: did[7:0] fields of the fsb
register description 186 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.13.9 nrecaddrl[1:0]: non recoverable fsb address low error log register this register captures the lower 32 bits of the fsb address for non recoverable errors when a fatal error is logged in its corresponding ferr_fat_fsb register. this register is only valid for request fsb errors. . 3.8.13.10 nrecaddrh[1:0]: non recove rable fsb address high error log register this register captures the upper 8 bits of the fsb address for non recoverable errors when a fatal error is logged in its corresponding ferr_fat_fsb register. this register is only valid for request fsb errors. . 3.8.13.11 emask_fsb[1:0]: fsb error mask register a ?0? in any field enables that error. device: 16 function: 0 offset: 48ch, 18ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:4 rost 0h a31dt4: fsb address [31:4] 3rost 0 a3: fsb address [3] 2:0 rv 000 reserved device: 16 function: 0 offset: 490h, 190h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7:0 rost 00h a39dt32: fsb address [39:32] device: 16 function: 0 offset: 492h, 192h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 15:9 rv 0h reserved 8rwst 1 f9msk: fsb protocol error 7rwst 1 f8msk: b-init 6rwst 1 f7msk: detected mcerr 5rwst 1 f6msk: data parity error 4rv 0hreserved 3rv 0hreserved 2rv 0hreserved 1rwst 1 f2msk: unsupported processor bus transaction 0rwst 1 f1msk: request/address parity error
intel ? 5000x chipset memory controller hub (mch) datasheet 187 register description 3.8.13.12 err2_fsb[1:0]: fsb error 2 mask register this register enables the signaling of err[2] wh en an error flag is set. note that one and only one error signal should be enabled err2_fsb, err1_fsb, err0_fsb, and mcerr_fsb for each of the corresponding bits. . 3.8.13.13 err1_fsb[1:0]: fsb error 1 mask register this register enables the signaling of err[1] wh en an error flag is set. note that one and only one error signal should be enabled err2_fsb, err1_fsb, err0_fsb, and mcerr_fsb for each of the corresponding bits. 3.8.13.14 err0_fsb[1:0]: fsb error 0 mask register this register enables the signaling of err[0] wh en an error flag is set. note that one and only one error signal should be enabled err2_fsb, err1_fsb, err0_fsb, and mcerr_fsb for each of the corresponding bits. device: 16 function: 0 offset: 498h, 198h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 15:9 rv 0h reserved 8rwst 1 f9msk: fsb protocol error 7rwst 1 f8msk: b-init 6rwst 1 f7msk: detected mcerr 5rwst 1 f6msk: data parity error 4rv 0reserved 3 rv 0h reserved 2 rv 0h reserved 1rwst 1 f2msk: unsupported processor bus transaction 0rwst 1 f1msk: request/address parity error device: 16 function: 0 offset: 496h, 196h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 15:9 rv 0h reserved 8rwst 1 f9msk: fsb protocol error 7rwst 1 f8msk: b-init 6rwst 1 f7msk: detected mcerr 5rwst 1 f6msk: data parity error 4 rv 0h reserved 3 rv 0h reserved 2 rv 0h reserved 1rwst 1 f2msk: unsupported processor bus transaction 0rwst 1 f1msk: request/address parity error
register description 188 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.13.15 mcerr_fsb[1:0]: fsb mcerr mask register this register enables the signaling of mcerr when an error flag is set. note that one and only one error signal should be en abled err2_fsb, err1_fsb, err0_fsb, and mcerr_fsb for each of the corresponding bits. device: 16 function: 0 offset: 494h, 194h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 15:9 rv 0h reserved 8rwst 1 f9msk: fsb protocol error 7rwst 1 f8msk: b-init 6rwst 1 f7msk: detected mcerr 5rwst 1 f6msk: data parity error 4 rv 0h reserved 3 rv 0h reserved 2 rv 0h reserved 1rwst 1 f2msk: unsupported processor bus transaction 0rwst 1 f1msk: request/address parity error device: 16 function: 0 offset: 49ah, 19ah version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 15:9 rv 0h reserved 8rwst 1 f9msk: fsb protocol error 7rwst 1 f8msk: b-init 6rwst 1 f7msk: detected mcerr 5rwst 1 f6msk: data parity error 4 rv 0h reserved 3 rv 0h reserved 2 rv 0h reserved 1rwst 1 f2msk: unsupported processor bus transaction 0rwst 1 f1msk: request/address parity error
intel ? 5000x chipset memory controller hub (mch) datasheet 189 register description 3.8.13.16 nrecsf - non-recoverable erro r control informatio n of snoop filter 3.8.13.17 recsf - recoverable error control information of snoop filter 3.8.13.18 ferr_fat_int - intern al first fatal error register ferr_fat _int latches the first mch internal fatal error. all subsequent errors get logged in the nerr_fat_int. device: 16 function: 2 offset: b0h version: intel 5000x chipset bit attr default description 63:38 rv 0h reserved 37 rost 0 hit(1), miss(0) 36:16 rost 0h tag(a[39:19]) 15:4 rost 000h set(a[18:7]) 3rost 0 interleave(a[6]) 2rost 0 state 1:0 rost 00 presence vector device: 16 function: 2 offset: b8h version: intel 5000x chipset bit attr default description 63:38 rv 0h reserved 37 rost 0 hit(1), miss(0) 36:16 rost 0h tag(a[39:19]) 15:4 rost 000h set(a[18:7]) 3rost 0 interleave(a[6]) 2rost 0 state 1:0 rost 00 presence vector device: 16 function: 2 offset: c0h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7:5 rv 000 reserved 4rwcst 0 b7err: multiple ecc error in any of the ways during sf lookup 3rv 0 reserved 2rwcst 0 b3err: coherency violation error for wewb 1rwcst 0 b2err: multi-tag hit sf 0rwcst 0 b1err: dm parity error
register description 190 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.13.19 ferr_nf_int - internal first non-fatal error register 3.8.13.20 nerr_fat_int - intern al next fatal error register 3.8.13.21 nerr_nf_int - internal next non-fatal error register 3.8.13.22 nrecint - non recoverabl e internal mch error log register this register will log non-recoverable errors (fatal and non fatal) based on the internal mch errors that originate from the ferr_fat_int, ferr_nf_int described starting from section 3.8.13.18 . for debugging vpp errors in th is register, for example, if vpp_pex_port2-3 is set, then software ca n scan the pci express configuration space for unit errors logged in the device 2,3 for pex_unit_ferr/nerr register as defined in section 3.8.12.28 to determine the failing port. the same can be repeated for the fb-dimm channels when vpp_fbd is set. device: 16 function: 2 offset: c1h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7:3 rv 0h reserved 2rwcst 0 b8err: sf coherency error for bil (sf) 1rwcst 0 b6err: single ecc error on sf lookup (sf) 0rwcst 0 b5err: single address map error (coh) device: 16 function: 2 offset: c2h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7:5 rv 000 reserved 4rwcst 0 b7err: multiple ecc error in any of the ways during sf lookup (sf) 3rv 0 reserved 2rwcst 0 b3err: coherency violation error (coh) for ewb 1rwcst 0 b2err: multi-tag hit sf (sf) 0rwcst 0 b1err: dm parity error (dm) device: 16 function: 2 offset: c3h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7:3 rv 0h reserved 2rwcst 0 b8err: sf coherency error for bil (sf) 1rwcst 0 b6err: single ecc error on sf lookup (sf) 0rwcst 0 b5err: address map error (coh)
intel ? 5000x chipset memory controller hub (mch) datasheet 191 register description 3.8.13.23 recint - recoverable in ternal mch data log register this register is not currently used as there are no correctable errors with in the internal data path of the mch. 3.8.13.24 emask_int - internal error mask register a ?0? in any bit position enables the corresponding error. device: 16 function: 2 offset: c4h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:21 rv 0h reserved 20:13 rost 0h dm entry 12:11 rv 00 reserved 10:8 rost 00000 internal block that detected the failure 001: vpp_pex_port2-3 010: vpp_pex_port4-7 011: vpp_fbd 100: coh 101: dm others: reserved 7rv 0reserved 6:0 rost 0h coh entry of failed location device: 16 function: 2 offset: c8h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:21 rv 0h reserved 20:13 rost 0h dm entry 12:11 rv 00 reserved 10:8 rost 000 internal block that detected the failure 001: vpp_pex_port2-3 010: vpp_pex_port4-7 011: vpp_fbd 101: coh 101: dm others: reserved 7rv 0reserved 6:0 rost 00h coh entry of failed location
register description 192 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.13.25 err2_int - intern al error 2 mask register this register enables the signaling of err[2] wh en an error flag is set. note that one and only one error signal should be enabled in the err2_int, err1_int, err0_int, and mcerr_int for each of the corresponding bits. 3.8.13.26 err1_int - intern al error 1 mask register this register enables the signaling of err[1] wh en an error flag is set. note that one and only one error signal should be enabled in the err2_int, err1_int, err0_int, and mcerr_int for each of the corresponding bits. device: 16 function: 2 offset: cch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7rv 1 b8msk: sf coherency error for bil 6rwst 1 b7msk: multiple ecc error in any of the ways during sf lookup 5rwst 1 b6msk: single ecc error on sf lookup 4rwst 1 b5msk: address map error 3rwst 1 b4msk: virtual pin port error 2rwst 1 b3msk: coherency violation error for ewb 1rwst 1 b2msk: multi-tag hit sf 0rwst 1 b1msk: dm parity error device: 16 function: 2 offset: d2h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7rwst 1 b8err2msk: sf coherency error for bil 6rwst 1 b7err2msk: multiple ecc error in any of the ways during sf lookup 5rwst 1 b6err2msk: single ecc error on sf lookup 4rwst 1 b5err2msk: address map error 3rwst 1 b4err2msk: smbus virtual pin error 2rwst 1 b3err2msk: coherency violation error for ewb 1rwst 1 b2err2msk: multi-tag hit sf 0rwst 1 b1err2msk: dm parity error device: 16 function: 2 offset: d1h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7rwst 1 b8err1msk: sf coherency error for bil 6rwst 1 b7err1msk: multiple ecc error in any of the ways during sf lookup 5rwst 1 b6err1msk: single ecc error on sf lookup
intel ? 5000x chipset memory controller hub (mch) datasheet 193 register description 3.8.13.27 err0_int - internal error 0 mask register this register enables the signaling of err[0] wh en an error flag is set. note that one and only one error signal should be enabled in the err2_int, err1_int, err0_int, and mcerr_int for each of the corresponding bits. 4rwst 1 b5err1msk: address map error 3rwst 1 b4err1msk: smbus virtual pin error 2rwst 1 b3err1msk: coherency violation error 1rwst 1 b2err1msk: multi-tag hit sf 0rwst 1 b1err1msk: dm parity error device: 16 function: 2 offset: d1h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description device: 16 function: 2 offset: d0h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7rwst 1 b8err0msk: sf coherency error for bil 6rwst 1 b7err0msk: multiple ecc error in any of the ways during sf lookup 5rwst 1 b6err0msk: single ecc error on sf lookup 4rwst 1 b5err0msk: address map error 3rwst 1 b4err0msk: smbus virtual pin error 2rwst 1 b3err0msk: coherency violation error for ewb 1rwst 1 b2err0msk: multi-tag hit sf 0rwst 1 b1err0msk: dm parity error
register description 194 intel ? 5000x chipset memory controller hub (mch) datasheet 3.8.13.28 mcerr_int - internal mcerr mask register this register enables the signaling of mcerr when an error flag is set. note that one and only one error signal should be enabled . note that one and only one error signal should be enabled in the err2_int, err1_i nt, err0_int, and mcerr_int for each of the corresponding bits. 3.9 memory control registers 3.9.1 mc - memory control settings miscellaneous controls not implemented in other registers. device: 16 function: 2 offset: d3h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7rwst 1 b8mcerrmsk: sf coherency error for bil 6rwst 1 b7mcerrmsk: multiple ecc error in any of the ways during sf lookup 5rwst 1 b6mcerrmsk: single ecc error on sf lookup 4rwst 1 b5mcerrmsk: address map error 3rwst 1 b4mcerrmsk: smbus virtual pin error 2rwst 1 b3mcerrmsk: coherency violation error for ewb 1rwst 1 b2mcerrmsk: multi-tag hit sf 0rwst 1 b1mcerrmsk: dm parity error device: 16 function: 1 offset: 40h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31 rv 0 reserved 30 rw 0 retry: retry enable ?1? = enables retry. ?0? = disables retry. 29 rv 0 reserved 28:25 rw 0h badramth: badram threshold number of consecutive instances of adjacent symbol errors required to mark a bad device in a rank. number of patrol scrub cycles required to decrement a non- saturated badcnt. if software desires to enable the ?enhanced mode? and use the badramth, it needs to set a non-zero value to this regist er field prior. otherwise, a value of 0 is considered illegal and memory ras oper ations may lead to indeterministic behavior. 24:22 rv 0 reserved 21 rw 0 initdone: initialization complete. this scratch bit communicates software state from intel 5000p chipset mch to bios. bios sets this bit to 1 after initialization of the dram memory array is complete. this bit has no effect on intel 5000p chipset mch operation.
intel ? 5000x chipset memory controller hub (mch) datasheet 195 register description 20 rw 0 fsmen: fsm enable. ?1? = enables operation of ddr protocol. this can be used as a synchronous reset to the fsm. (normal) ?0? = inhibits processing of enqueued transactions. disables all dram accesses which means that the fb-dimm link comes up , trains, goes to l0, sends nops, does alerts, syncs, fast resets, amb configurations, and so forth, but does not perform: a) memory reads b) memory writes c) refreshes not preserved by savcfg bit in the syre register. 19:18 rw 0h ethrot: dimm electrical throttling limit electrical throttling is required to prevent data corruption by limiting the number of activates within a specific time interval and is enabled by mtr.ethrottle register bit. for each rank in the dimm, maximum number of activates is four per sliding electrical throttle window as defined below: 00: 10 clocks(ddr533) 01: 13 clocks(ddr667) 10: 15 clocks(ddr800) 11: 20 clocks(safe/conservative setting) the memory controller should stop sending more than 4 activates for each sliding electrical throttle window. when the slid ing window boundary crosses, the counter is reset and the process repeats. 17 rw 0 gtw_mode: global throttling window mode this register field is used to reduce the global throttling window size for the purposes of debug/validation. 0: global/open-loop throttling window of 16384*1344 (default, normal working mode). if global throttling is enabled in this normal window , it will be held active for 16 global throttling windows without any dimm exceeding gblact. 1: global/open-loop throttling window of 4*1344 (debug, validation). if global throttling is enabled in this debug window , it will be held active for 2 global throttling windows without an y dimm exceeding gblact. 16 rw 0 mirror: mirror mode enable ?1? = mirroring enabled ?0? = mirroring disabled. fbdhpc.nextstate defines other characteristics of mirrored mode. the intel 5000p chipset mch does not support mirroring while sparing is enabled: this bit should not be set if spcpc.sparen is set. the intel 5000p chipset mch does not support mirroring with demand scrub: this bit should not be set if demsen is set. note: when mirror mode is enabled, both way0 and way1 of mir register should be set to 1. otherwise, it is a programming error. 15:9 rv 0h reserved 8rw 0 scrbalgo: scrub algorithm for x8 uncorrectable error detection 0: normal mode 1: enhanced mode 7rw 0 scrben: patrol scrub enable 1: enables patrol scrubbing. 0: disables patrol scrubbing the scrub engine will start th e scrub operations from th e beginning to the end of the memory each time the scrben register bit is set. note that scrben should be disabled during mir updates. 6rw 0 demsen: demand scrub enable enables demand scrubbing. this bit must not be set when mirror is set. device: 16 function: 1 offset: 40h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description
register description 196 intel ? 5000x chipset memory controller hub (mch) datasheet 3.9.2 gblact - global acti vation throttle register this register contains the hostel limit for global activation throttle control. 5rw 0 errdeten: error detection enable ?1? = northbound crc/ecc checking enabled. ?0? = northbound crc/ecc checking disabled fb-dimm ?alert? detection is disabled, status packets are ignored, northbound error logging and data poisoning are disabled when northbound crc/ecc checking is disabled. 4rwc 0 scrbdone: scrub complete the scrub unit will set this bit to ?1? wh en it has completed scrubbing the entire memory. software should poll this bit afte r setting the scrub enable (scrben) bit to determine when the operation has comple ted. if the scrub enable bit is cleared midway during the scrub cycle, then the scrbdone bit will not be set and the intel 5000p chipset mch will stop the scrub cycle immediately. 3:0 rv 0h reserved device: 16 function: 1 offset: 40h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description device: 16 function: 1 offset: 60h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7:0 rw 0 gblactlm: global activation throttle limit this field controls the activation of global throttling based on the number of activates sampled per dimm pair on each branch. if the number of activates in the global throttling window 1 exceeds the number indicated by the gblactlm file d in this register, then glob al throttling is started by setting the thrsts[1:0].gblthrt bit for the respective branch and the global activation throttling logic to use the thrtmid register for throttling. the granularity of this field is 65536 activations. refer to ta b l e 3 - 3 7 if software sets this value greater th an 168, the chipset will cap the gblactlm field to 168. notes: 1. if (mc.gtw_mode==1), then the global throttling window is 4*1344 cycles (debug, validation). else if (mc.gtw_mode==0), then the window is set to 16384*1344 cycles (normal). table 3-37. global activation throttling as a f unction of global acti vation throttling limit (gblactm) and global throttling wind ow mode (gtw_mode) register fields gblact.gblactm range (0.168) number of activations mc.gtw_mode=0 (16384*1344 window) mc.gtw_mode=1 (4*1344 window) 0 no throttling (unlimited activations) no throttling (unlimited activations) 1 65536 16 2 131072 32 16 1048576 256 32 2097152 512 64 4194304 1024
intel ? 5000x chipset memory controller hub (mch) datasheet 197 register description 3.9.3 thrtsts[1:0] - thermal throttling status register 96 6291456 1536 100 6553600 1600 128 8388608 2048 150 9830400 2400 168 11010048 (100% bw) 2688 (100% bw) device: 16 function: 1 offset: 6ah, 68h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 15:9 rv 0h reserved 8ro 0h gblthrt: global activation throttle 1 this field is set by the inte l 5000p chipset mch to indica te the start of the global activation throttling based on the number of activates sampled in the global window. if the number of activates in the global window (16384*1344 cycles) exceeds the number indicated by the gblactlm field in this register, then thrtsts.gblthrt bit is set to enable the global activation throttling logic. global activation throttling logic will rema in active until 16 (or 2) global throttling 2 windows in a row have gone by without any dimm exceeding the gblact.gblactlm register at which poin t this register field will be reset. notes: 1. the intel 5000p chipset mch will use an internal sign al called gblthrt* from its combinatorial cluster for controlling open loop throttling. 2. if mc.gtw_mode=1, then the debug mode is enab led and the intel 5000p chipset mch will use 2 windows for global activation logic to be valid. 7:0 ro 0h thrmthrt: thermal throttle value this field holds the current activation throttling value based on the intel 5000p chipset mch/fb-dimm throttling algorithm. 0: no throttling (un limited activation) 1: 4 activations per activation window 2: 8 activations per activation window 168: 672 activations per activation window this field will be set by the intel 5000p ch ipset mch and the value of this field will vary between thrtlow and thrthi registers based on the throttling. table 3-37. global activation throttling as a fu nction of global activation throttling limit (gblactm) and global th rottling window mode (gtw_mode) register fields gblact.gblactm range (0.168) number of activations mc.gtw_mode=0 (16384*1344 window) mc.gtw_mode=1 (4*1344 window)
register description 198 intel ? 5000x chipset memory controller hub (mch) datasheet 3.9.4 thrtlow - thermal throttling low register 3.9.5 thrtmid - therma l throttle mid register device: 16 function: 1 offset: 64h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7:0 rw 0h thrtlowlm: thermal throttle low limit a base throttling level that is applied wh en the temperature is in the low range (below tlow) and thrtctrl.thrmhunt is set and the thrtsts.gblthrt* bit is not set by the global throttling window logic. note: the gblthrt* is an internal signal from the intel 5000p chipset mch open loop combinatorial cluste r before it is latched in the thrsts.glthrt register. this will prevent any stale/ delayed information from being used for the open loop throttling logic. this base throttling is also enab led if thrtctrl.thrmhunt = 0 and thrtsts.gblthrt* bit =0. the maximum value this field can be initia lized by software is 168 (decimal). this corresponds to 672 activations per activation (throttling) window and gives 100% bw. the granularity of this field is 4 activations. 0: no throttling (unlimited activation) 1: 4 activations per activation window 2: 8 activations per activation window 168: 672 activations per activation window if software sets this value greater th an 168, the chipset will cap the thrtlowlm field to 168. device: 16 function: 1 offset: 65h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7:0 rw 0h thrtmidlm: thermal throttle middle limit a mid level throttling level that is applie d when the temperature is in the middle range (above tlow but below tmid) and thrtctrl.thrmhunt is set or the thrtsts.gblthrt* bit is set by the glob al throttling window logic in the intel 5000p chipset mch. the maximum value this field can be initia lized by software is 168 (decimal). this corresponds to 672 activations per activation window and gives 100% bw. the granularity of this field is 4 activations. 0: no throttling (unlimited activation) 1: 4 activations per activation window 2: 8 activations per activation window 168: 672 activations per activation window if software sets this value greater th an 168, the chipset will cap the thrtmidlm field to 168. this field should be less than or equal to the thrtlow.thrtlowlm.
intel ? 5000x chipset memory controller hub (mch) datasheet 199 register description 3.9.6 thrthi - thermal throttle high register 3.9.7 thrtctrl - thermal throttling control register 3.9.8 mca - memory control settings a additional miscellaneous control not reflected in other registers. device: 16 function: 1 offset: 66h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7:0 rw 0h thrthilm: thermal throttle high limit the highest level of throttling (that is, minimum number of activations). when thrtctrl.thrmode=1, this le vel is applied whenever the temperature is above tmid. when thrtctrl.thrmode=0, this level is the ceilin g of the hunting algorithm of the closed loop throttling. the temperature being above tmid has priority over the global throttling window enabling throttling (the higher throttling level takes precedence). this throttling will be enabled if thrtctrl.thrmhunt is set. the maximum value this field can be initiali zed by software is 168 (decimal). this corresponds to 672 activations per activation window and gives 100% bw. the granularity of this field is 4 activations. 0: no throttling (un limited activation) 1: 4 activations per activation window 2: 8 activations per activation window 168: 672 activations per activation window if software sets this value greater than 168, the chipset will cap the thrthilm field to 168. this field should be less than or equal to the thrtmid.thrtmidlm. device: 16 function: 1 offset: 67h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7:2 rv 0h reserved 1rw 0 thrmode: thermal throttle mode 0: thrtsts.thrmthrt register is initia lized by the intel 5000p chipset mch such that they vary in range between thrtmid and thrthi above tmid (staircase) 1: thrtsts.thrmthrt register field is ?slammed? to thrthi above tmid. 0rw 0 thrmhunt: intelligent thermal throttle enable 0: thrtsts.thrmthrt register is not enabled 1: thrtsts.thrmthrt register is enabled for the temperature to have any influence on the throttle parameters. if thrmhunt=0 only the gblthrt bit from the global throttle window can chan ge the thrmthrt register field. device: 16 function: 1 offset: 58h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:28 rw 0h to: starvation timeout a value of zero represents eight cycles. each increment adds eight cycles. maximum is 128 cycles. 27:15 rv 0h reserved
register description 200 intel ? 5000x chipset memory controller hub (mch) datasheet 3.9.9 ddrfrq - ddr frequency ratio this register specifies the core:ddr frequency ratio. 3.9.10 fbdtohostgrcfg0: fb-d imm to host gear ratio configuration 0 this register consists of 8 nibbles of mux se lect data for the proper selection of gearing behavior on the fb-dimm. this is the first of two registers to control the behavior for the fb-dimm to host (north bound) data flow. 14 rw 0 schdimm: single channel dimm operation 0: the mc assumes that the intel 5000p chip set mch is operating normally, that is, mc is not operating with only one fb-d imm channel as in single channel mode. 1: in this mode, the intel 5000p chipset mch mc will operate such that only 1 channel (that is, branch 0, channel 0) is active and there can be one or more dimms present in channel 0. 13:0 rv 0h reserved . device: 16 function: 1 offset: 58h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description device: 16 function: 1 offset: 56h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7:6 rv 0000h reserved1 5:4 ro 00h now: present core:ddr frequency ratio ?00? = 1:1 . for example, if busclk =333 mhz, then ddr=667 mhz. ?01? = reserved ?10? = 4:5 . for example, if busclk =266 mhz, then ddr=667 mhz. ?11? = 5:4 . for example, if busclk =333 mhz, then ddr=533 mhz. this field will only specify the relati onship between the core-domain and fb- dimm-domain clocks. this field does not indicate the frequency of the fb-dimm scid link... that is entire ly determined by the frequency of the fbdclk reference clocks. to achieve successful fb-dimm channel initialization, the frequency of the fbdclk reference clock must match the frequency of the fb-dimm-domain clock. e.g. if the busclk=333 mhz and the now field specifies a ratio of 1:1, then fb-dimm channel initialization will succee d with an fbdclk frequency of 333 mhz. 3:2 rv 00h reserved 1:0 rwst 00 next: future core:ddr frequency ratio this frequency ratio will take effect and tr ansfer to the ?now? field after the next intel 5000p chipset mch hard reset. ?00? = 1:1 . for example, if busclk =333 mhz, then ddr=667 mhz. ?01? = reserved ?10? = 4:5 . for example, if busclk =266 mhz, then ddr=667 mhz. ?11? = 5:4 . for example, if busclk =333 mhz, then ddr=533 mhz. this field will only set the relationshi p between the core-domain and fb-dimm- domain clocks. this field will not set the frequency of the fb-dimm scid link... that is entirely determined by the frequency of the fbdclk reference clocks. to achieve successful fb-dimm channel initialization, the frequency of the fbdclk reference clock must match the frequency of the fb-d imm-domain clock. for example, if the busclk=333 mhz and the next field specifie s a ratio of 1:1, then after the next intel 5000p chipset mch hard reset, fb-di mm channel initialization will succeed with an fbdclk frequency of 333 mhz.
intel ? 5000x chipset memory controller hub (mch) datasheet 201 register description 3.9.11 fbdtohostgrcfg1: fb-d imm to host gear ratio configuration 1 this register consists of eight nibbles of mux select data for the proper selection of gearing behavior on the fb-dimm for the 1:1 and 4:5 modes.this is the second register for fb-dimm to host gearing control. device: 16 function: 1 offset: 160h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:0 rwst 11111111h fbdhstgrmux: fb-dimm to host clock gearing mux selector. eight nibbles of mux select for memory/ddr2 to fsb/core geared clock boundary crossing phase enables. refer to ta b l e 3 - 3 8 for the programming details. table 3-38. fb-dimm to host gear ratio mux fsb:memory frequency gear ratio 1 notes: 1. for 4:5 gear ratio, software should use either conservative or aggressive mode for all the respective memory gearing registers (no mix and match). value 333:333 267:267 400:400 1:1 11111111h 333:267 5:4 00023230h 267:333 4:5 (conservative) 00004323h 267:333 4:5 (aggressive) 00002323h device: 16 function: 1 offset: 164h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:0 rwst 00000000h fbdhstgrmux: fb-dimm to host clock gearing mux selector. eight nibbles of mux select for memory/ddr2 to fsb/core geared clock boundary crossing phase enables. refer to ta b l e 3 - 3 9 for the programming details. table 3-39. fb-dimm to host gear ratio mux fsb:memory frequency gear ratio 1 value 333:333 267:267 400:400 1:1 00000000h 333:267 5:4 00000000h 2 267:333 4:5 (conservative) 00002000h 267:333 4:5 (aggressive) 00000400h
register description 202 intel ? 5000x chipset memory controller hub (mch) datasheet 3.9.12 hosttofbdgrcfg: host to fb-dimm gear ratio configuration this register consists of eight nibbles of mux select data for the proper selection of gearing behavior on the host to fb-dimm path (south bound). 3.9.13 grfbdvldcfg: fb-d imm valid configuration this register provides valid signals to assert data in the fb-dimm side for various gearing ratios. it primarily affects the southbound data path for 4:5 gearing and determines when a nop packet is to be inserted into the fb-dimm. notes: 1. for 4:5 gear ratio, software should use either conservative or aggressive mode for all the respective memory gearing registers (no mix and match). 2. ignored by mgr registers in the 5:4 mode. device: 16 function: 1 offset: 168h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:0 rwst 11111111h hstfbdgrmux: host to fb-dimm clock gearing mux selector. eight nibbles of mux select for fsb/core to memory/ddr2 geared clock boundary crossing phase enables. refer to table 3-40 for the programming details. table 3-40. host to fb-dimm gear ratio mux select fsb:memory frequency gear ratio 1 notes: 1. for 4:5 gear ratio, software should use either conservative or aggressive mode for all the respective memory gearing registers (no mix and match). value 333:333 267:267 400:400 1:1 11111111h 333:267 5:4 00004323h 267:333 4:5 (conservative) 00023230h 267:333 4:5 (aggressive) 00023023h device: 16 function: 1 offset: 16ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7:0 rwst 0h fbdvldmux: fb-dimm data valid mux selector. determines which valid host cy cle to insert nop. refer to ta b l e 3 - 4 1 for the programming details. this primarily affects the 4:5 gearing ratio.
intel ? 5000x chipset memory controller hub (mch) datasheet 203 register description table 3-41. fb-dimm host data cycle valid mux select fsb:memory frequency gear ratio 1 notes: 1. for 4:5 gear ratio, software should use either conservative or aggressive mode for all the respective memory gearing registers (no mix and match). value 333:333 267:267 400:400 1:1 00h 333:267 5:4 00h 2 2. ignored by mgr registers in the 5:4 mode. 267:333 4:5 (conservative) 01h 267:333 4:5 (aggressive) 04h
register description 204 intel ? 5000x chipset memory controller hub (mch) datasheet 3.9.14 grhostfullcfg: host full flow control configuration this register configures flow control when the host is full. it primarily effects the southbound data path and determines when the flow control signal to the core is asserted. 3.9.15 grbubblecfg: fb-dimm host bubble configuration this register provides valid signals to assert data in the fb-dimm side for various gearing ratios. this primarily affects the nort hbound data path for the 5:4 configuration and determines when a bubble is inserted when gearing up. . device: 16 function: 1 offset: 16dh bit attr default description 7:0 rwst 0h fcmux: flow control mux selector configures flow control on the host according to ta b l e 3 - 4 2 . this primarily affect the 5:4 gearing ratio. table 3-42. fb-dimm to host flow control mux select fsb:memory frequency gear ratio 1 notes: 1. for 4:5 gear ratio, software should use either conservative or aggressive mode for all the respective memory gearing registers (no mix and match). value 333:333 267:267 400:400 1:1 00h 333:267 5:4 02h 267:333 4:5 (conservative) 02h 267:333 4:5 (aggressive) 08h device: 16 function: 1 offset: 16eh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7:0 rwst 0h fbdbblmux: fb-dimm data bubble mux selector. configures bubbles in the host according to ta b l e 3 - 4 3 . this primarily affect the 5:4 gearing ratio. table 3-43. fb-dimm bubble mux select fsb:memory frequency gear ratio value 333:333 267:267 400:400 1:1 00h 333:267 5:4 04h 267:333 4:5 00h 1 notes: 1. ignored by mgr registers in 4:5 mode.
intel ? 5000x chipset memory controller hub (mch) datasheet 205 register description 3.9.16 grfbdtohostdblcfg: fb-dimm to host double configuration this register provides valid signals to assert data in the fb-dimm side for various gearing ratios. this primarily affects the no rthbound data path of the 4:5 config and determines when both the lanes in core contain valid fb-dimm data. 3.9.17 summary of memory gear ing register operating modes ? fbdtohostgrcfg1, grfbdvldcfg, and grfbdtohostdblcfg are used only in 4:5 mode. ? grbubblecfg is only used in 5:4 mode. ? grhostfullcfg is used in both 4:5 and 5:4 modes. ? fbdtohostgrcfg0 and hosttofbdgrcfg are used in 4:5, 5:4, and 1:1 modes. 3.9.18 drta - dram timing register a this register defines timing parameters for all ddr2 sdrams in the memory subsystem. the parameters for these devices are obtained by serial presence detect. this register must be set to provide timings that satisfy the specifications of all drams detected. for example, if drams present have different trcs, the maximum should be used to program this register. consult the jedec ddr2 dram specifications for the technology of the devices in use. device: 16 function: 1 offset: 16fh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7:0 rwst 0h fbdhstdblmux: fb-dimm to host double mux selector configures when both data lines are valid according to ta b l e 3 - 4 4 . this primarily affect the 4:5 gearing ratio. table 3-44. fb-dimm to host double config mux select fsb:memory frequency gear ratio 1 notes: 1. for 4:5 gear ratio, software should use either conservative or aggressive mode for all the respective memory gearing registers (no mix and match). value 333:333 267:267 400:400 1:1 00h 333:267 5:4 00h 2 2. ignored by mgr registers in the 5:4 mode. 267:333 4:5 (conservative) 08h 267:333 4:5 (aggressive) 04h
register description 206 intel ? 5000x chipset memory controller hub (mch) datasheet device: 16 function: 1 offset: 48h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31 rv 0 reserved 30:28 rw 0h tal: additive latency for posted cas this parameter is the posted-cas ?t al ? ddr2 timing parameter. it must match the value written to the emrs register in the dram. 27:22 rw 0h twrc: activate command to activate command delay following a ddr write this parameter is the minimum delay fr om an activate command followed by a write with page-close to another acti vate command on the same bank. this parameter prevents bank activation protocol violations in the dram?s. this parameter is defined as follows: trcd + (tcl ? 1) + bl/2 + twr + trp where t rcd is the ddr ras-to-cas delay, t cl is the cas-to-first-read-data latency, bl is the burst length, t wr is the write recovery time, and trp is the precharge time.this parameter is defined in core cycles. this parameter is set to greater than or equal to the largest twrc of any dimm on the branch. 21:16 rw 0h trc: activate command to activate command delay (same bank) this parameter is the minimum delay fr om an activate command to another activate or refresh command to the same bank. this parameter ensures that the page of the bank that was opened by the first activate command is closed before the next activate command is issued. this parameter is defined in core cycles. this parameter is set to greater than or equa l to the largest trc of any dimm on the branch. 15:8 rw 00h trfc: refresh command to activate command delay this parameter is the minimum delay from a refresh command to another activate or refresh command. this parameter ensure s that the banks that were opened by the refresh command are closed before the next activate command is issued. this parameter is defined in core cycles. this parameter is set to greater than or equal to the largest trfc of any dimm on the branch. 7:4 rw 0h trrd: activate command to activate command delay (different banks) this parameter is the minimum delay fr om an activate command to another activate or refresh command to a different bank on the same rank. this parameter ensures that the electrical disturbance to the sdram die caused by the first activate has attenuated sufficiently before the next activate is applied. this parameter is defined in core cycles. this parameter is se t to greater than or equal to the largest trrd of any dimm on the branch. 3:0 rw 0h tref: refresh command to refresh command delay this parameter is the maximum delay from a refresh command to another refresh command to the same rank. this parameter ensures that a sufficient number of refreshes per time interval are issued to ea ch rank. this parameter is defined as an integral multiple of fbd super frames. an fbd super frame is 42 fbd packets (1:1, 5:4) or 40 fbd packets for 4:5 gear ratios in the intel 5000p chipset. this parameter is set to less than or equa l to the smallest tref of any dimm on the memory sub-system. the refresh interval is typically 7.80 us for a ddrii dimm rank. refer to table 3-45, ?optimum tref values as a function of core: fbd gear ratios (in fbd super frames)? . the refresh period is calculated as follows: dimm refresh period = tref * super_frame_size * 8 * fbd clock period where the number ?8? is a constant denoting the maximum number of ranks supported by the intel 5000p chipset. as an example, the refresh period is given as 7 * 42 * 8 * 3 ns = 7056 ns for a ddrii667 system with an fsb to fbd ratio of 1:1 a value of zero disables refresh and clears the refresh counter, allowing a test program to align refresh even ts with the test and thus improve failure repeatability.
intel ? 5000x chipset memory controller hub (mch) datasheet 207 register description 3.9.19 drtb - ddr timing register b this register defines timing parameters th at work with all ddr ports in the memory subsystem. this register must be set to provide timings that satisfy the specifications of all detected ddr ports. for example, if ddr ports have different tr2ws, the maximum should be used to program this register. table 3-45. optimum tref values as a functi on of core: fbd gear ratios (in fbd super frames) dimm optimum tref values as a function of core: fbd gear ratios (in fbd super frames) 1:1 5:4 4:5 ddrii533 6 6 n/a ddrii667 7 n/a 8 device: 16 function: 1 offset: 4ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:19 rv 000h reserved 18:16 rw 0h tw2rdr: write command to read command delay, different rank this parameter is the minimum delay from a write command to a read command on different ranks of the same dimm. this parameter prevents data strobe protocol violations on the dimms ddr data bus. this parameter is defined in core cycles. this parameter is dependent on cache line si ze. the formula for th is value is bl/2 + t frr - 1. t frr is the turnaround time required to read from different ranks on the dimm. 15:12 rw 0h tr2w: read command to write command delay this parameter is the minimum delay from a read command to a write command on the same dimm. this parameter prevents data strobe protocol violations on the dimms ddr data bus. this parameter is defined in core cycles. this parameter is dependent on cache line size. the formula for this value is bl/2 + t frr + 1. t frr is the turnaround time from read to write on the dimm. this value applies to a dimm- hit in the conflict checking unit. 11:8 rw 0h tw2r: write command to read command delay, same rank this parameter is the minimum delay from a write command to a read command on the same rank. this parameter prevents data strobe protocol violations on the dimms ddr data bus. this parameter is defined in core cycles. this parameter is dependent on cache line size. th e formula for this value is t cl - 1 + bl/2 + t wtr . 7:4 rw 0h tr2r: read command to read command delay this parameter is the minimum delay fr om a read command to another read command on a different rank of the same dimm. this parameter prevents data strobe protocol violations on the dimms ddr data bus. this parameter is defined in core cycles. the formula for this value is bl/2 + t frr . t frr is the turnaround time required to read from different ranks on the dimm. 3:0 rw 0h tw2w: write command to write command delay this parameter is the minimum delay from a write command to another write command on the same dimm. this parameter prevents data strobe protocol violations on the dimms ddr data bus. this parameter is defined in core cycles. this parameter is dependent on cache line size.the formula for this value is bl/2.
register description 208 intel ? 5000x chipset memory controller hub (mch) datasheet 3.9.20 errper - error period non-zero uerrcnt and cerrcnt counts ar e decremented when the error period counter reaches this threshold. the error peri od counter is cleared on reset or when it reaches this threshold. the error period counter increments every 32,768 cycles. ta b l e 3 - 4 6 indicates the timing characteristics of this register: 3.9.21 memory map registers 3.9.21.1 tolm - top of low memory this register defines the low mmio gap below 4gb. see section 3.9.21.2 . whereas the mir.limits are adjustable, to lm establishes the maximum address below 4 gb that should be treated as a memory access. tolm is defined in a 256 mb boundary. this register must not be modified while servicing memory requests. table 3-46. timing characteristics of errper core frequency per increment maximum period 333 mhz 98.304us 4 days, 21 hours, 16 minutes, 52.465056596 seconds 266 mhz 122.880us 6 days, 2 hours , 36 minutes, 5.581331712 seconds device: 16 function: 1 offset: 50h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:0 rw 0h thresh: uerrcnt / cerrcnt decrement threshold. device: 16 function: 1 offset: 6ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 15:12 rw 1h tolm: top of low memory this register defines the maximum dr am memory address that lies below 4gb. addresses equal to or greater than the tolm, and less than 4g, are decoded as low mmio, mmcfg (if map within this range by he cbase), chipset, interrupt/smm and firmware as described in the address ma pping chapter. all accesses less than the tolm are treated as dram accesses (except for the vga region when enabled and pam gaps). configuration software should set this field either to maximize the amount of memory in the system (same as the top mir.limit), or to minimize the allocated space for the lower pci memo ry (low mmio) plus 32 mb (chipset/ interrupt/smm and firmware) at a 256 mb boundary. this field must be set to at least 1h, for a minimum of 256 mb of dram. there is also a minimum of 256mb between tolm and 4 gb (for low mmio, mmcfg, chipset, interrupt/smm and firmware) since tolm is on a 256mb boundary. this field corresponds to a[31:28]. setti ng of ?1111? corre sponds to 3.75 gb dram, and so on down to ?0001? corresponds to 0.25gb dram. ?0000? setting is illegal and a programming error. 11:0 rv 000h reserved
intel ? 5000x chipset memory controller hub (mch) datasheet 209 register description 3.9.21.2 mir[2:0] - memory interleave range these registers define each memory branch?s interleave participation in processor- physical (a) space. each register defines a range. if the processor-physical address falls in the range defined by an mir, the ?way? fields in that mir defines branch participation in the interleave. the way-sensitive address bit is a[6]. for a mir to be effective, way0 and way1 fields can not be set to 00b. in mi rror mode, the way0 and way1 fields should be set to 11b. matching addresses participate in the corresponding ways. compensation for a non-4gb mmio gap size is performed by adjustin g the limit of each range upward if it is above tolm as shown in ta b l e 3 - 4 7 . mir updates can only occur in the reset, ready, fault, disabled, recoveryreset, recoveryfault, and recoveryready states. 3.9.21.3 amir[2:0] - adjusted memory interleave range for the convenience of software which is tryi ng to determine the physical location to which a processor bus address is sent, 16 scratch bits are associated with each mir. table 3-47. interleaving of an address is governed by mir[i] limit with respect to tolm match mir[i] if mir[i].limit[7:0] <= tolm then mir[i].limit[7:0] > a[35:28] >= mir[i- 1].limit[7:0] if mir[i].limit[7:0] > tolm > mir[i-1].limit[7:0] then mir[i].limit[7:0] + (10h - tolm) > a[35:28] >= mir[i-1] 1 .limit[7:0] notes: 1. for mir[0], mir[i-1] is defined to be 0. if mir[i].limit[7:0] > mir[i-1].limit[7:0] >= tolm then mir[i].limit[7:0] + (10h - tolm) > a[35:28] >= mir[i-1].limit[7:0] + (10h - tolm) device: 16 function: 1 offset: 88h, 84h, 80h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 15:4 rw 000h limit this field defines the highest addr ess in the range a[39:28] prior to modification by the tolm register. since mirs only comprehend 64gb - (tolm.tolm * 256 mb) of address space, limit[11:8] (bits [15:12] of this register) are ignored, and the largest legal value is (64 gb - (tolm.tolm * 256 mb)) / 2 28 . 3:2 rv 00 reserved 1rw 0 way1 branch 1 participate in this mir range if this bit is set and (the way-sensitive bit is 1b or way0 of this mir is 0b). 0rw 0 way0 branch 0 participate in this mir range if this bit is set and (the way-sensitive bit is 1b or way1 of this mir is 0b).
register description 210 intel ? 5000x chipset memory controller hub (mch) datasheet 3.9.22 fb-dimm error registers 3.9.22.1 ferr_fat_fbd - fb-dimm first fatal errors the first fatal error for an fb-dimm branch is flagged in these registers. only one flag is ever set. lower-numbered branches have higher priority th an higher-numbered branches. lower-numbered channels have higher priority than higher-numbered channels. higher-order error bits within a regi ster have higher priority than lower-order bits. the fbdchan_indx field is not an erro r. this register will display invalid index channel data until an error has occurred. 3.9.22.2 nerr_fat_fbd - fb-dimm next fatal errors if an error is already fla gged in ferr_fat_fbd, subsequent and lower-priority fatal errors are logged in nerr_fat_fbd. 3.9.22.3 ferr_nf_fbd - fb-dimm first non-fatal errors the first non-fatal error for a fb-dimm branch is flagged in these registers. only one flag is ever set. lower-numbered branches have higher priority than higher-numbered branches. lower-numbered channels have higher priority than higher-numbered device: 16 function: 1 offset: 94h, 90h, 8ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 15:0 rw 0000h adjlimit: adjusted mir limit device: 16 function: 1 offset: 98h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:30 rv 00 reserved 29:28 rv 00 fbdchan_indx: logs channel in whic h the error occurred 27:3 rv 0000000h reserved 2rwcst 0 m3err: >tmid thermal event with in telligent throttling disabled 1rwcst 0 m2err: northbound crc error on non-redundant retry 0rwcst 0 m1err: alert on non-redundant retry or fast reset timeout device: 16 function: 1 offset: 9ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:3 rv 0h reserved 2rwcst 0 m3err: >tmid thermal event with intelligent throttling disabled 1rwcst 0 m2err: northbound crc error on non-redundant retry 0rwcst 0 m1err: alert on non-redundant retr y or fast reset timeout
intel ? 5000x chipset memory controller hub (mch) datasheet 211 register description channels. higher-order error bits within a regi ster have higher priority than lower-order bits. the fbdchan_indx field is not an erro r. this register will display invalid index channel data until an error has occurred. device: 16 function: 1 offset: a0h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr defaul t description 31:30 rv 00 reserved 29:28 rwcst 00 fbdchan_indx: logs channel in which the error occurred the least-significant-bit of this field has no significance for m4err through m12err and m17err through m20err. the leas t-significant-bit of this field only bears significance for m13err through m15err and m21err and higher. 27:25 rv 0h reserved 24 rwcst 0 m28err: dimm-spare copy completed 23 rwcst 0 m27err: dimm-spare copy started 22 rwcst 0 unused: this register field is of type ?rwcst? and have no associated functionality currently. they are allocated for future use. 21 rwcst 0 unused: this register field is of type ?rwcst? and have no associated functionality currently. they are allocated for future use. 20 rwcst 0 unused: this register field is of type ?rwcst? and have no associated functionality currently. they are allocated for future use. 19 rwcst 0 unused: this register field is of type ?rwcst? and have no associated functionality currently. they are allocated for future use. 18 rwcst 0 m22err: spd protocol error 17 rwcst 0 m21err: fbd northbound crc error on fbd sync status 16 rwcst 0 m20err: correctable patrol data ecc 15 rwcst 0 m19err: correctable spare-copy data ecc 14 rwcst 0 m18err: correctable mirrored demand data ecc 13 rwcst 0 m17err: correctable non-mirrored demand data ecc 12 rv 0 reserved 11 rwcst 0 m15err: non-retry or redundant retry fbd northbound crc error on read data 10 rwcst 0 m14err: non-retry or redundant retry fbd configuration alert 9rwcst0 m13err: non-retry or redundant retry fbd memory alert or redundant fast reset timeout 8rwcst0 m12err: non-aliased uncorrectable patrol data ecc 7rwcst0 m11err: non-aliased uncorrectable spare-copy data ecc 6rwcst0 m10err: non-aliased uncorrectable mirrored demand data ecc 5rwcst0 m9err: non-aliased uncorrectable non-mirrored demand data ecc 4rwcst0 m8err: aliased uncorrectable patrol data ecc 3rwcst0 m7err: aliased uncorrectable spare-copy data ecc 2rwcst0 m6err: aliased uncorrectable mi rrored demand data ecc 1rwcst0 m5err: aliased uncorrectable non-mirrored demand data ecc
register description 212 intel ? 5000x chipset memory controller hub (mch) datasheet 3.9.22.4 nerr_nf_fbd - fb-dimm next fatal errors if an error is already flagged in ferr_nf_fb d, subsequent and lower-priority non-fatal errors are logged in nerr_nf_fbd. 0rwcst0 m4err: uncorrectable data ecc on replay device: 16 function: 1 offset: a0h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr defaul t description device: 16 function: 1 offset: a4h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr defaul t description 31:25 rv 00h reserved 24 rwcst 0 m28err: dimm-spare copy completed 23 rwcst 0 m27err: dimm-spare copy started 22 rwcst 0 unused: this register field is of type ?rwcst? and have no associated functionality currently. they are allocated for future use. 21 rwcst 0 unused: this register field is of type ?rwcst? and have no associated functionality currently. they are allocated for future use. 20 rwcst 0 unused: this register field is of type ?rwcst? and have no associated functionality currently. they are allocated for future use. 19 rwcst 0 unused: this register field is of type ?rwcst? and have no associated functionality currently. they are allocated for future use. 18 rwcst 0 m22err: spd protocol error 17 rwcst 0 m21err: fbd northbound crc error on fbd sync status 16 rwcst 0 m20err: correctable patrol data ecc 15 rwcst 0 m19err: correctable spare-copy data ecc 14 rwcst 0 m18err: correctable mirrored demand data ecc 13 rwcst 0 m17err: correctable non-mirrored demand data ecc 12 rv 0 reserved 11 rwcst 0 m15err: non-retry or redundant retry fbd northbound crc error on read data 10 rwcst 0 m14err: non-retry or redundant retry fbd configuration alert 9rwcst0 m13err: non-retry or redundant retry fbd memory alert or redundant fast reset timeout 8rwcst0 m12err: non-aliased uncorrectable patrol data ecc 7rwcst0 m11err: non-aliased uncorrectable spare-copy data ecc 6rwcst0 m10err: non-aliased uncorrectable mirrored demand data ecc 5rwcst0 m9err: non-aliased uncorrectable non-mirrored demand data ecc 4rwcst0 m8err: aliased uncorrectable patrol data ecc
intel ? 5000x chipset memory controller hub (mch) datasheet 213 register description 3.9.22.5 emask_fbd - fb-dimm error mask register a ?0? in any field enables that error. 3rwcst0 m7err: aliased uncorrectable spare-copy data ecc 2rwcst0 m6err: aliased uncorrectable mirrored demand data ecc 1rwcst0 m5err: aliased uncorrectable non-mirrored demand data ecc 0rwcst0 m4err: uncorrectable data ecc on replay device: 16 function: 1 offset: a4h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr defaul t description device: 16 function: 1 offset: a8h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:28 rv 00h reserved 27 rwst 1 m28err: dimm-spare copy completed 26 rwst 1 m27err: dimm-spare copy started 25 rwst 1 unused: this register field is of type ?rwcst? and have no associated functionality currently. they are allocated for future use 24 rwst 1 unused: this register field is of type ?rwcst? and have no associated functionality currently. they are allocated for future use 23 rwst 1 unused: this register field is of type ?rwcst? and have no associated functionality currently. they are allocated for future use 22 rwst 1 unused: this register field is of type ?rwcst? and have no associated functionality currently. they are allocated for future use 21 rwst 1 m22err: spd protocol error 20 rwst 1 m21err: fbd northbound crc error on fbd sync status 19 rwst 1 m20err: correctable patrol data ecc 18 rwst 1 m19err: correctable spare-copy data ecc 17 rwst 1 m18err: correctable mirrored demand data ecc 16 rwst 1 m17err: correctable non-mirrored demand data ecc 15 rv 0 reserved 14 rwst 1 m15err: non-retry or redundant retry fbd northbound crc error on read data 13 rwst 1 m14err: non-retry or redundant retry fbd configuration alert 12 rwst 1 m13err: non-retry or redundant retry fbd memory alert or redundant fast reset timeout 11 rwst 1 m12err: non-aliased uncorrectable patrol data ecc 10 rwst 1 m11err: non-aliased uncorrectable spare-copy data ecc 9rwst1 m10err: non-aliased uncorrectable mirrored demand data ecc 8 rwst 1 m9err: non-aliased uncorrectable non-mirrored demand data ecc
register description 214 intel ? 5000x chipset memory controller hub (mch) datasheet 7rwst1 m8err: aliased uncorrectable patrol data ecc 6rwst1 m7err: aliased uncorrectable spare-copy data ecc 5rwst1 m6err: aliased uncorrectable mirrored demand data ecc 4rwst1 m5err: aliased uncorrectable non-mirrored demand data ecc 3rwst1 m4err: uncorrectable data ecc on replay 2rwst1 m3err: >tmid thermal event with intelligent throttling disabled 1rwst1 m2err: northbound crc error on retry 0rwst1 m1err: alert on non-redundant retry or fast reset timeout device: 16 function: 1 offset: a8h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description
intel ? 5000x chipset memory controller hub (mch) datasheet 215 register description 3.9.22.6 err0_fbd: fb-dimm error 0 mask register a ?0? in any field enables that error. this register enables the signaling of err[0] when an error flag is set. device: 16 function: 1 offset: ach version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:28 rv 0h reserved 27 rwcst 1 m28err: dimm-spare copy completed 26 rwcst 1 m27err: dimm-spare copy started 25 rwcst 1 unused: this register field is of type ?rwcst? and have no associated functionality currently. they are allocated for future use 24 rwcst 1 unused: this register field is of type ?rwcst? and have no associated functionality currently. they are allocated for future use 23 rwcst 1 unused: this register field is of type ?rwcst? and have no associated functionality currently. they are allocated for future use 22 rwcst 1 unused: this register field is of type ?rwcst? and have no associated functionality currently. they are allocated for future use 21 rwcst 1 m22err: spd protocol error 20 rwcst 1 m21err: fbd northbound crc error on fbd sync status 19 rwcst 1 m20err: correctable patrol data ecc 18 rwcst 1 m19err: correctable spare-copy data ecc 17 rwcst 1 m18err: correctable mirrored demand data ecc 16 rwcst 1 m17err: correctable non-mirrored demand data ecc 15 rv 0 reserved 14 rwcst 1 m15err: non-retry or redundant retry fbd northbound crc error on read data 13 rwcst 1 m14err: non-retry or redundant retry fbd configuration alert 12 rwcst 1 m13err: non-retry or redundant retry fbd memory alert or redundant fast reset timeout 11 rwcst 1 m12err: non-aliased uncorrectable patrol data ecc 10 rwcst 1 m11err: non-aliased uncorrectable spare-copy data ecc 9rwcst1 m10err: non-aliased uncorrectable mirrored demand data ecc 8rwcst1 m9err : non-aliased uncorrectable non-mirrored demand data ecc 7rwcst1 m8err: aliased uncorrectable patrol data ecc 6rwcst1 m7err: aliased uncorrectable spare-copy data ecc 5rwcst1 m6err: aliased uncorrectable mirrored demand data ecc 4rwcst1 m5err: aliased uncorrectable non-mirrored demand data ecc 3rwcst1 m4err: uncorrectable data ecc on replay 2rwcst1 m3err: >tmid thermal event with intelligent throttling disabled 1rwcst1 m2err: northbound crc error on retry 0rwcst1 m1err: alert on non-redundant retry or fast reset timeout
register description 216 intel ? 5000x chipset memory controller hub (mch) datasheet 3.9.22.7 err1_fbd: fb-dimm error 1 mask register a ?0? in any field enables that error. this register enables the signaling of err[1] when an error flag is set. device: 16 function: 1 offset: b0h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr def ault description 31:28 rv 0h reserved 27 rwcst 1 m28err: dimm-spare copy completed 26 rwcst 1 m27err: dimm-spare copy started 25 rwcst 1 unused: this register field is of type ?rwcst? and have no associated functionality currently. they are allocated for future use 24 rwcst 1 unused: this register field is of type ?rwcst? and have no associated functionality currently. they are allocated for future use 23 rwcst 1 unused: this register field is of type ?rwcst? and have no associated functionality currently. they are allocated for future use 22 rwcst 1 unused: this register field is of type ?rwcst? and have no associated functionality currently. they are allocated for future use 21 rwcst 1 m22err: spd protocol error 20 rwcst 1 m21err: fbd northbound crc error on fbd sync status 19 rwcst 1 m20err: correctable patrol data ecc 18 rwcst 1 m19err: correctable spare-copy data ecc 17 rwcst 1 m18err: correctable mirrored demand data ecc 16 rwcst 1 m17err: correctable non-mirrored demand data ecc 15 rv 0 reserved 14 rwcst 1 m15err: non-retry or redundant retry fbd northbound crc error on read data 13 rwcst 1 m14err: non-retry or redundant retry fbd configuration alert 12 rwcst 1 m13err: non-retry or redundant retry fbd memory alert or redundant fast reset timeout 11 rwcst 1 m12err: non-aliased uncorrectable patrol data ecc 10 rwcst 1 m11err: non-aliased uncorrectable spare-copy data ecc 9rwcst1 m10err: non-aliased uncorrectable mirrored demand data ecc 8rwcst1 m9err : non-aliased uncorrectable non-mirrored demand data ecc 7rwcst1 m8err: aliased uncorrectable patrol data ecc 6rwcst1 m7err: aliased uncorrectable spare-copy data ecc 5rwcst1 m6err: aliased uncorrectable mirrored demand data ecc 4rwcst1 m5err: aliased uncorrectable non-mirrored demand data ecc 3rwcst1 m4err: uncorrectable data ecc on replay 2rwcst1 m3err: >tmid thermal event with intelligent throttling disabled 1rwcst1 m2err: northbound crc error on retry 0rwcst1 m1err: alert on non-redundant retry or fast reset timeout
intel ? 5000x chipset memory controller hub (mch) datasheet 217 register description 3.9.22.8 err2_fbd: fb-dimm error 2 mask register a ?0? in any field enables that error. this register enables the signaling of err[2] when an error flag is set . device: 16 function: 1 offset: b4h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr defaul t description 31:28 rv 0h reserved 27 rwcst 1 m28err: dimm-spare copy completed 26 rwcst 1 m27err: dimm-spare copy started 25 rwcst 1 unused: this register field is of type ?rwcst? and have no associated functionality currently. they are allocated for future used 24 rwcst 1 unused: this register field is of type ?rwcst? and have no associated functionality currently. they are allocated for future use 23 rwcst 1 unused: this register field is of type ?rwcst? and have no associated functionality currently. they are allocated for future use 22 rwcst 1 unused: this register field is of type ?rwcst? and have no associated functionality currently. they are allocated for future use 21 rwcst 1 m22err: spd protocol error 20 rwcst 1 m21err: fbd northbound crc error on fbd sync status 19 rwcst 1 m20err: correctable patrol data ecc 18 rwcst 1 m19err: correctable spare-copy data ecc 17 rwcst 1 m18err: correctable mirrored demand data ecc 16 rwcst 1 m17err: correctable non-mirrored demand data ecc 15 rv 0 reserved 14 rwcst 1 m15err: non-retry or redundant retry fbd northbound crc error on read data 13 rwcst 1 m14err: non-retry or redundant retry fbd configuration alert 12 rwcst 1 m13err: non-retry or redundant retry fbd memory alert or redundant fast reset timeout 11 rwcst 1 m12err: non-aliased uncorrectable patrol data ecc 10 rwcst 1 m11err: non-aliased uncorrectable spare-copy data ecc 9rwcst1 m10err: non-aliased uncorrectable mirrored demand data ecc 8rwcst1 m9err : non-aliased uncorrectable non-mirrored demand data ecc 7rwcst1 m8err: aliased uncorrectable patrol data ecc 6rwcst1 m7err: aliased uncorrectable spare-copy data ecc 5rwcst1 m6err: aliased uncorrectable mi rrored demand data ecc 4rwcst1 m5err: aliased uncorrectable non-mirrored demand data ecc 3rwcst1 m4err: uncorrectable data ecc on replay 2rwcst1 m3err: >tmid thermal event with intelligent throttling disabled 1rwcst1 m2err: northbound crc error on retry 0rwcst1 m1err: alert on non-redundant retr y or fast reset timeout
register description 218 intel ? 5000x chipset memory controller hub (mch) datasheet 3.9.22.9 mcerr_fbd - fb-dimm mcerr mask register a ?0? in any field enables that error. this register enables the signaling of mcerr when an error flag is set. device: 16 function: 1 offset: b8h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr def ault description 31:28 rv 0h reserved 27 rwcst 1 m28err: dimm-spare copy completed 26 rwcst 1 m27err: dimm-spare copy started 25 rwcst 1 unused: this register field is of type ?rwcst? and have no associated functionality currently. they are allocated for future used 24 rwcst 1 unused: this register field is of type ?rwcst? and have no associated functionality currently. they are allocated for future use 23 rwcst 1 unused: this register field is of type ?rwcst? and have no associated functionality currently. they are allocated for future used 22 rwcst 1 unused: this register field is of type ?rwcst? and have no associated functionality currently. they are allocated for future used 21 rwcst 1 m22err: spd protocol error 20 rwcst 1 m21err: fbd northbound crc error on fbd sync status 19 rwcst 1 m20err: correctable patrol data ecc 18 rwcst 1 m19err: correctable spare-copy data ecc 17 rwcst 1 m18err: correctable mirrored demand data ecc 16 rwcst 1 m17err: correctable non-mirrored demand data ecc 15 rv 0 reserved 14 rwcst 1 m15err: non-retry or redundant retry fbd northbound crc error on read data 13 rwcst 1 m14err: non-retry or redundant retry fbd configuration alert 12 rwcst 1 m13err: non-retry or redundant retry fbd memory alert or redundant fast reset timeout 11 rwcst 1 m12err: non-aliased uncorrectable patrol data ecc 10 rwcst 1 m11err: non-aliased uncorrectable spare-copy data ecc 9rwcst1 m10err: non-aliased uncorrectable mirrored demand data ecc 8rwcst1 m9err: non-aliased uncorrectable non-mirrored demand data ecc 7rwcst1 m8err: aliased uncorrectable patrol data ecc 6rwcst1 m7err : aliased uncorrectable spare-copy data ecc 5rwcst1 m6err: aliased uncorrectable mi rrored demand data ecc 4rwcst1 m5err: aliased uncorrectable non-mirrored demand data ecc 3rwcst1 m4err : uncorrectable data ecc on replay 2rwcst1 m3err : >tmid thermal event with intelligent throttling disabled 1rwcst1 m2err: northbound crc error on retry 0rwcst1 m1err: alert on non-redundant retry or fast reset timeout
intel ? 5000x chipset memory controller hub (mch) datasheet 219 register description 3.9.22.10 nrecmema - non-recoverable memory error log register a this register latches information on the first detected fatal memory error. 3.9.22.11 nrecmemb - non-recoverabl e memory error log register b this register latches information on the first detected fatal memory error. 3.9.22.12 nrecfglog - non-recoverable dimm configuration access error log register this register latches information on the first detected non-fatal dimm configuration register access. device: 16 function: 1 offset: beh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 15 rv 0 reserved 14:12 rost 0h bank: bank of the failed request 11 rost 0 rdwr ?0? = read ?1? = write 10:8 rost 0h rank: rank of the failed request 7:0 rost 00h rec_fbd_dm_buf_id: dm buffer id of the failed request device: 16 function: 1 offset: c0h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:28 rv 0h reserved 27:16 rost 000h cas: cas address of the failed request 15 rv 0 reserved 14:0 rost 0h ras: ras address of the failed request device: 16 function: 1 offset: c4h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:28 rv 0h reserved 27:24 rost 0h be: byte enables of the failed request 23:16 rost 00h reg: register address of the failed request 15:12 rv 0h reserved 11 rost 0 rdwr ?0? = read ?1? = write 10:8 rost 0h function: function number of the failed request 7:0 rost 00h cfg_fbd_dm_buf_id: dm buffer id of the failed request
register description 220 intel ? 5000x chipset memory controller hub (mch) datasheet 3.9.22.13 nrecfbda: non-recoverable fb-dimm error log register a the nrecfbd registers defined below (a through e) have the following mapping: this register latches information on the first detected fatal northbound crc error. 3.9.22.14 nrecfbdb - non-recoverable fb-dimm error log register b this register latches information on the first detected fatal northbound crc error. table 3-48. nrecfbd mapping information bits description 155:144 crc 143:128 ecc 127:0 data device: 16 function: 1 offset: c8h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:0 rost 0h bits: bits [31:0] of the packet device: 16 function: 1 offset: cch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:0 rost 0h bits: bits [63:32] of the packet
intel ? 5000x chipset memory controller hub (mch) datasheet 221 register description 3.9.22.15 nrecfbdc - non-recoverable fb-dimm error log register c this register latches information on the first detected fatal northbound crc error. 3.9.22.16 nrecfbdd - non-recoverabl e fb-dimm error log register d this register latches information on the first detected fatal northbound crc error. 3.9.22.17 nrecfbde - non-recoverable fb-dimm error log register e this register latches information on the first detected fatal northbound crc error. 3.9.22.18 redmemb: recoverable memo ry data error log register b this register latches information on th e first detected correctable ecc error. device: 16 function: 1 offset: d0h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:0 rost 0h bits: bits [95:64] of the packet device: 16 function: 1 offset: d4h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:0 rost 0h bits: bits [127:96] of the packet device: 16 function: 1 offset: d8h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:28 rv 0h reserved 27:0 rost 0h bits: bits [155:128] of the packet device: 16 function: 1 offset: 7ch bit attr default description 31:18 rv 0 reserved 17:0 rost 0h ecc _locator: identifies the adjacent symbol pair in error for correctable errors according to ta b l e 3 - 4 9 , figure 5-2 and figure 5-4 .
register description 222 intel ? 5000x chipset memory controller hub (mch) datasheet : table 3-49. ecc locator mapping information symbols locator bit ds[1:0] 0 ds[3:2] 1 ds[5:4] 2 ds[7:6] 3 ds[9:8] 4 ds[11:10] 5 ds[13:12] 6 ds[15:14] 7 cs[1:0] 8 ds[17:16] 9 ds[19:18] 10 ds[21:20] 11 ds[23:22] 12 ds[25:24] 13 ds[27:26] 14 ds[29:28] 15 ds[31:30] 16 cs[3:2] 17
intel ? 5000x chipset memory controller hub (mch) datasheet 223 register description 3.9.22.19 recmema - recoverable memory error log register a this register latches information on the first detected non-fatal memory error. 3.9.22.20 recmemb - recoverable memory error log register b this register latches information on the first detected non-fatal memory error. 3.9.22.21 recfglog - recoverable di mm configuration access error log register this register latches information on the first detected fatal dimm configuration register access. device: 16 function: 1 offset: e2h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 15 rv 0 reserved 14:12 rost 0h bank: bank of the failed request 11 rost 0 rdwr ?0? = read ?1? = write 10:8 rost 0h rank: rank of the failed request 7:0 rost 00h rec_fbd_dm_buf_id: dm buffer id of the failed request device: 16 function: 1 offset: e4h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:29 rv 0h reserved 28:16 rost 000h cas: cas address of the failed request 15 rv 0 reserved 14:0 rost 0h ras: ras address of the failed request device: 16 function: 1 offset: e8h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:28 rv 0h reserved 27:24 rost 0h be: byte enables of the failed request 23:16 rost 00h reg: register address of the failed request 15:12 rv 0h reserved 11 rost 0 rdwr ?0? = read ?1? = write 10:8 rost 0h function: function number of the failed request 7:0 rost 00h cfg_fbd_ce_buf_id: dm buffer id of the failed request
register description 224 intel ? 5000x chipset memory controller hub (mch) datasheet 3.9.22.22 recfbda - recoverable fb-dimm error log register a this register latches information on the first northbound crc error. 3.9.22.23 recfbdb - recoverable fb-dimm error log register b this register latches information on the fi rst detected non-fatal northbound crc error. 3.9.22.24 recfbdc - recoverable fb-dimm error log register c this register latches information on the fi rst detected non-fatal northbound crc error. 3.9.22.25 recfbdd - recoverable fb-dimm error log register d this register latches information on the fi rst detected non-fatal northbound crc error. device: 16 function: 1 offset: ech version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:0 rost 0h bits: bits [31:0] of the packet device: 16 function: 1 offset: f0h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:0 rost 0h bits: bits [63:32] of the packet device: 16 function: 1 offset: f4h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:0 rost 0h bits: bits [95:64] of the packet device: 16 function: 1 offset: f8h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 31:0 rost 0h bits: bits [127:96] of the packet
intel ? 5000x chipset memory controller hub (mch) datasheet 225 register description 3.9.22.26 recfbde - recoverable fb-dimm error log register e this register latches information on the first detected non-fatal northbound crc error. 3.9.23 fb-dimm branch registers there are two sets of the following registers, one set for each fb-dimm branch. they each appear in function 0 of different devices as shown in ta b l e 3 - 3 . 3.9.23.1 fbdlvl[1:0][1:0] - fb-dimm packet levelization this register controls the fb-dimm channel delays. 3.9.23.2 fbdhpc[1:0]: fbd state control this register controls the fbd channel for initialization and mirroring recovery. it consists of a next state field. the index in fbdhpc[index] associates the fbdhpc with branch[index]. fbdhpc[0] is associated with fbd branch 0, fbdhpc[1] is associated with fbd branch 1. when software writes to fbdhpc[x].nextstat e, the transition will take effect on one or both channels within the branch depend ing on whether the branch is operating is single- or dual-channel mode. when bnb hardware transitions fbdst.state with the following encodings: 1) disabled, 2) redundant, 3) recovery failed, 4) redundancy loss, and 5) reset, it will transition states of one or both channels within the same branch depending on whether the branch is operating in single- or dual-channel mode. device: 16 function: 1 offset: fch bit attr default description 31:28 rv 0h reserved 27:0 rost 0h bits: bits [155:128] of the packet device: 21 function: 0 offset: 45h, 44h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 22 function: 0 offset: 45h, 44h version: intel 5000p chipset bit attr default description 7:6 rv 00 reserved 5:0 ro 0h trrl: read round-trip latency measured from issue of the fb-dimm channel?s southbound ts2 packet header to the arrival of its northbound response header.
register description 226 intel ? 5000x chipset memory controller hub (mch) datasheet device 1 :22, 21 function:0 offset:4fh notes: 1. the nomenclature is device 22 (branch 1), 21 (branch 0) bit attr default description 7:0 rw 00h nextstate: fbd branch state control field this field is written by software to change the branch state. it returns the last value written when read. some states can only be entered under hardware control and should not be written by software. 00h: reset 10h: init 20h: ready 2 30h: active 2 40h: redundant 2 50h: disabled 60h: redundancy loss 2 - may not be written 70h: recovery reset - (should only be selected when mc.mirror is set) 80h: recovery init - (should only be selected when mc.mirror is set) 90h: recovery ready 2 - (should only be selected when mc.mirror is set) a0h: resilver 2 - (should only be selected when mc.mirror is set) (should not be written while fbdst.state=resilver) b0h: recovery fault c0h: recovery failed d0h: fault 2. both sync and refresh packets are sent during this mode.
intel ? 5000x chipset memory controller hub (mch) datasheet 227 register description 3.9.23.3 fbdst[1:0] - fb-dimm status these registers are inspected by software to determine the current fb-dimm branch state. this register contains mirroring recovery state, and initialization state. the indexing scheme is the same as in fbdh pc registers. the current fb-dimm branch state field indicates state for one or both channels within the same branch depending on whether the branch is operating in single- or dual-channel mode. 3.9.23.4 fbdrst[1:0] - fb-dimm reset the fb-dimm i/o blocks are reset separately from the rest of the intel 5000p chipset mch. these blocks, composed of fast-clocked (ghz unit-interval clocked) logic, are supplied by a pll whose fbdclk is not av ailable when pwrgood is asserted. after fbdclk is enabled and the fb-dimm pll has acquired lock, corereset# is deasserted for a minimum of 21ns, then asserted for a minimum of 2us. after the 2us assertion, corereset# is deasserted followed by a minimum delay of 3ns at which time softcorereset# is deasserted. if the platform removes fbdclk on a hot-remove of the branch, corereset# and softcorereset# must be asserted prior to loss of fbdclk. a ?disabled? (not enabled) fbdclk is fl oated at the source, and pulled to ground through the termination near the rece iver in the intel 5000p chipset mch. all timing specifications in figure 3-6 are minimums. after the sequence in figure 3-6 has been executed, the fb-dimm br anch is ready for initialization. device: 21 function: 0 offset: 4bh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 22 function: 0 offset: 4bh version: intel 5000p chipset bit attr default description 7:0 rost 00h state: fbd branch state this field describes the current state of the fb-dimm branch. it can be read by software to determine which fb-dimm branch is being sequenced through recovery, and how far the fb-dimm branch has progressed. 00h: reset 10h: init 20h: ready 30h: active 40h: redundant 50h: disabled 60h: redundancy loss - may not be written 70h: recovery reset - (should only be selected when mc.mirror is set) 80h: recovery init - (should only be selected when mc.mirror is set) 90h: recovery ready - (should only be selected when mc.mirror is set) a0h: reserved b0h: recovery fault c0h: recovery failed d0h: fault this field is only sticky through hard rese t when syre.s3 is set. this field is not sticky through hard reset when syre.s3 is cleared.
register description 228 intel ? 5000x chipset memory controller hub (mch) datasheet 3.9.23.5 spcpc[1:0] - spare copy control these controls set up sparing for each branch. branch zero (device 21) takes precedence over branch one (device 22): if both spare-control-enabled branches? spare error thresholds trigger in the same cycle, sparing will only commence on branch zero. sparing will not commence on a competing branch until its in-progress competitor?s spare control enable is cleared and it?s uerrcnt/cerrcnt criteria is still met. figure 3-6. fb-dimm reset timing device: 21 function: 0 offset: 53h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 22 function: 0 offset: 53h version: intel 5000p chipset bit attr default description 7: 3 rv 00h reserved 2rwst 0 brselcmpreset: branch select for compensation reset 0: compreset is tied to corereset# from branch 0 1: compreset is tied to corereset# from branch 1 for branch 1 to be selected for reset, th is field has to be a ?1? for both branch instances. 1rwst 0 softcorereset#: soft core reset see timing diagram figure 3-6 . 0: soft core reset asserted 1: soft core reset de-asserted 0rwst 0 corereset#: core reset see timing diagram figure 3-6 . 0: core reset asserted 1: core reset de-asserted fbdclk fbd pll corereset# softcorereset# t 1 21ns 2us 3ns unlocked locked enabled 0
intel ? 5000x chipset memory controller hub (mch) datasheet 229 register description 3.9.23.6 spcps[1:0] - spare copy status device: 21 function: 0 offset: 40h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 22 function: 0 offset: 40h version: intel 5000p chipset bit attr default description 7:4 rw 0h seth: spare error threshold a spare fail-over operation will commence when the sparen bit is set and a uerrcnt.rank[i] and/or cerrcnt.rank[i] count for one and only one rank hits this threshold. 3:1 rwl 0h sprank: spare rank target of the spare copy operation. this rank should not initially appear in a dmir.rank field. after the spare copy, intel 5000p chipset mch will update the failed dmir.rank fields with this valu e. enabled by sparen. changes to this register will not be acknowledged by the hardware while spcps.dscip is set. 0rw 0 sparen: spare control enable ?1? enables sparing, ?0? disables sparing. the sprank field defines other characteristics of the sparing operati on. the intel 5000p chipset mch does not support sparing in mirrored mode: this bit should not be set if mc.mirror is set. if this bit is cleared before spcps.sfo is set, then if this bit is subsequently set while the spare trigger is st ill valid, then the spare copy operation will not resume from where it left off, but will instead restart from the beginning. device: 21 function: 0 offset: 41h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 22 function: 0 offset: 41h version: intel 5000p chipset bit attr default description 7:6 rv 00 reserved 5ro 0 lbthr: leaky bucket threshold reached ?0? = leaky-bucket threshold not reached ?1? = leaky-bucket count matches spcpc.seth. generates error m27. cleared by reducing the offending count(s) in the uerrcnt/cerrcnt registers. 4ro 0 dscip: dimm sparing copy in progress ?0? = dimm sparing copy not in progress. ?1? = dimm sparing copy in progress. set when spcpc.sparen is set, and only one rank in uerrcnt/cerrcnt is at threshold. this bit remains se t until sfo is set. this bit is cleared when sfo is set. error m27 is set when this bit transitions from ?0? to ?1?. 3:1 ro 000 fr: failed rank rank that was spared. updated with the uerrcnt/cerrcnt rank that has reached threshold when dscip is set. 0ro 0 sfo: spare fail-over ?0? = spare has not been subs tituted for failing dimm rank. ?1? = spare has been substituted for failing dimm rank. generates error m28. cleared when spcpc.sparen is cleared.
register description 230 intel ? 5000x chipset memory controller hub (mch) datasheet 3.9.23.7 mtr[1:0][3:0] - memory technology registers these registers define the organization of th e dimm?s. there is one mtr for each pair of slots comprising either one or two ranks. the parameters for these devices can be obtained by serial presence detect. mtr[3:0] defines slot-pairs [3:0] on branch [0]. mtr[7:4] defines slot-pairs [3:0] on branch[1]. mtr[3:0] in ta b l e 3 - 2 4 is mtr[3:0] for device 21 which is mtr[3:0] for this section 3.9.23.7 . mtr[3:0] in ta b l e 3 - 2 4 is mtr[3:0] for device 22 which is mtr[7:4] for this section 3.9.23.7 . this register must not be modified while servicing memory requests. 3.9.23.8 dmir[1:0][4:0] - dimm interleave range these registers define rank participation in various dimm interleaves. device: 21 function: 0 offset: 8ch, 88h, 84h, 80h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 22 function: 0 offset: 8ch, 88h, 84h, 80h version: intel 5000p chipset bit attr default description 15:9 rv 00h reserved 8rw 0 present: dimms are present this bit is set if both dimms are pres ent and their technologies are compatible. 7rw 0 ethrottle: technology - electrical throttle defines the electrical throttling level for these dimms: ?0? = electrical throttling is disabled ?1? = electrical throttling is enabled us ing the throttling level defined by the mc.ethrot configuration field. 6rw 0 width: technology - width defines the data width of the sdrams used on these dimms ?0? = x4 (4 bits wide) ?1? = x8 (8 bits wide) 5rw 0 numbank: technology - number of banks defines the number of (real, not shadow) banks on these dimms ?0? = four-banked ?1? = eight-banked 4rw 0 numrank: technology - number of ranks defines the number of ranks on these dimms. ?0? = single ranked ?1? = double ranked 3:2 rw 00 numrow: technology - number of rows defines the number of rows within these dimms. ?00?= 8,192, 13 rows ?01?= 16,384, 14 rows ?10?= 32,768, 15 rows ?11?= reserved 1:0 rw 00 numcol: technology - number of columns defines the number of columns within these dimms ?00?= 1,024, 10 columns ?01?= 2,048, 11 columns ?10?= 4,096, 12 columns ?11?= reserved
intel ? 5000x chipset memory controller hub (mch) datasheet 231 register description each register defines a range. if the memory (m) address falls in the range defined by an adjacent pair of dmir.limit?s, the rank fields in the upper dmir define the number and interleave position of ranks? way partic ipation. matching addresses participate in the corresponding ways. the combination of two equal ranks with three unequal ranks is illegal. when a dmir is programmed for a 2-way in terleave, rank0/rank2 should be with the same rank number and rank1/rank3 should be another rank number. this register must not be modified while servicing memory requests. 3.9.23.9 fbdicmd[1:0][1:0] - fb-dimm initialization command these registers define channel behavior during the ?init?, ?recovery init?, ?reset?, and ?recovery reset? hot-plug states. the ?ambid? field for the even-numbered channel also defines branch behavior during fast reset. device: 21 function: 0 offset: a0h, 9ch, 98h, 94h, 90h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 22 function: 0 offset: a0h, 9ch, 98h, 94h, 90h version: intel 5000p chipset bit attr default description 31:24 rv 000h reserved 23:16 rw 00h limit this field defines the highest addres s in the range. memory requests participate in this dmir range if limit[i] > m[34:28] >= limit[i-1]. for i = 0, limit[i-1]=0 (m[35] is considered as ze ro for the purpose of this comparison). 15:12 rv 0h reserved 11:9 rw 000 rank3 defines which rank participates in way3. 8:6 rw 000 rank2 defines which rank participates in way2. 5:3 rw 000 rank1 defines which rank participates in way1. 2:0 rw 000 rank0 defines which rank participates in way0. device: 21 function: 0 offset: 47h, 46h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 22 function: 0 offset: 47h, 46h version: intel 5000p chipset bit attr default description 7rw 0 en: enable ?0? = drive electrical idle on the channel. ?1? = drive initpat on the channel. this field is not used during fast reset.
register description 232 intel ? 5000x chipset memory controller hub (mch) datasheet 3.9.23.10 fbdists[1:0][1:0] - fb-dimm initialization status the contents of this register are valid only during ?initialization? states. the thirteen bits [12:0] correspond to the northbound bit-lanes. 6:4 rw 00 initpat: initialization pattern ?000?=ts0: training sequence 0 to last amb (not valid in ?reset?) ?001?=ts1: training sequence 1 to last amb (not valid in ?reset?) ?010?=ts2: training sequence 2 to last amb (not valid in ?reset?) ?011?=ts3: training sequence 3 to last amb (not valid in ?reset?) ?100?= reserved ?101?=ts2: training sequence 2 not to last amb with nb merge disabled (not valid in ?reset?) ?110?=ts2: training sequence 2 not to last amb with nb merge enabled (not valid in ?reset?) ?111?=all ones (valid only in ?reset?) this pattern is superseded by the ?en? bit. this field is not used during fast reset. the note ?(not valid in ?reset?)? in dicates that is not valid when fbdst.state=?reset? or ?recovery reset? and en=?1?. the note ?(valid only in ?reset?)? indicates that this is va lid only when fbdst.state=?reset? or ?recovery reset?. 3:0 rw 0h ambid: advanced memory buffer identifier driven during the training sequences. this field is also used during fast re set to identify the last (southernmost) dimm. device: 21 function: 0 offset: 47h, 46h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 22 function: 0 offset: 47h, 46h version: intel 5000p chipset bit attr default description device: 21 function: 0 offset: 5ah, 58h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 22 function: 0 offset: 5ah, 58h version: intel 5000p chipset bit attr default description 15:13 rv 000 reserved 12:0 ro 0000h patdet: pattern detection ?1? = pattern recognized. ?0? = pattern not recognized. bit-lane status is evaluated at the end of each instance of the pattern specified by the fbdicmd.en and fbdicmd.initpat fields. bit-lane status is evaluated on each change to the fbdicmd.en and fbdicmd.initpat.only bits [2:0] are valid during electrical idle, an d only after the fbdrst reset sequence has been executed. a recognizable training sequence must contain the fbdicmd.ambid. ts1 detection is qualified by test patterns specified in section 4.3 of rev. 0.75 of fbd dfx specification , which defines the ?sb/nb_m apping? (1 bit), the ?test parameters? (24 bits), and the ?electrical stress pattern?.
intel ? 5000x chipset memory controller hub (mch) datasheet 233 register description 3.9.23.11 ambpresent[1:0][1:0] - fb-dimm amb slot present register these registers control configuration transaction routing to amb slots on a per fb- dimm channel basis. this includes both accesses through memory mapped region (based on ambase register, see section 3.8.3.1 ) and ambselect (for smbus/jtag access only, access via device 9, function 0. see section 3.8.3.3 ). software needs to program this register after spd discovery process. intel 5000p chipset mch will check this register before it sends actual fb-dimm amb configuration transaction. device: 21 function: 0 offset: 66h, 64h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 22 function: 0 offset: 66h, 64h version: intel 5000p chipset bit attr default description 15:0 rwo 0h ambsp: slot [bit_position] present in the fbd channel 1: indicates amb slot addressed by ds [3:0] in decimal = [bit_position] is present; configuration tran saction will be routed to fb-dimm channel. bit 15 controls ds[3:0] = 1111b, bit 14 contro ls ds[3:0] = 1110b,..., bit 0 controls ds[3:0] = 0000b. 0: amb slot addressed by ds[3:0] in decimal = [bit_position] is not populated; no configuration transactio n will be sent to fb-dimm channel.
register description 234 intel ? 5000x chipset memory controller hub (mch) datasheet 3.9.24 fb-dimm ras registers there are two sets of the following register s, one set for each fb-dimm branch. they each appear in function 0 of different devices as shown in ta b l e 3 - 3 . 3.9.24.1 uerrcnt[1:0] - uncorrectable error count this register implements the ?leaky-bucket? counters for uncorrectable errors for each rank. each field ?limits? at a value of ?1 5? (?1111?). non-zero counts are decremented when the errper threshold is reached by the error period counter. counts are frozen at the threshold defined by spcpc.seth and se t the spcps.lbthr bit. writing a value of ?1111? clears and thaws the count. changing spcpc.seth has no effect upon a frozen count. note: aliased uncorrectable errors are not co unted as uncorrectable errors in the implementation of this register. they are treated as correctable errors and logged in the cerrcnt register. 3.9.24.2 cerrcnt[1:0] - co rrectable error count this register implements the ?leaky-bucket? counters for correctable errors for each rank. each field ?limits? at a value of ?1 5? (?1111?). non-zero counts are decremented when the errper threshold is reached by the error period counter. counts are frozen at the threshold defined by spcpc.seth and se t the spcps.lbthr bit. writing a value of ?1111? clears and thaws the count. changing spcpc.seth has no effect upon a frozen count. note: aliased uncorrectable errors are counted as co rrectable errors in the implementation of this register. device: 21 function: 0 offset: a4h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 22 function: 0 offset: a4h version: intel 5000p chipset bit attr default description 31:28 rwcst 0h rank7: error count for rank 7 27:24 rwcst 0h rank6 : error count for rank 6 23:20 rwcst 0h rank5: error count for rank 5 19:16 rwcst 0h rank4: error count for rank 4 15:12 rwcst 0h rank3: error count for rank 3 11:8 rwcst 0h rank2: error count for rank 2 7:4 rwcst 0h rank1: error count for rank 1 3:0 rwcst 0h rank0: error count for rank 0
intel ? 5000x chipset memory controller hub (mch) datasheet 235 register description 3.9.24.3 badrama[1:0] - bad dram marker a this register implements ?failed-device? markers for the enhanced demand scrub algorithm. hardware ?marks? bad devices. the ?mark? is a number between 1 and 18 inclusive. a value of ?0 0000h? indicates an ?un-marked? rank: all ram?s are presumed ?good?. only ranks containing x8 dram are ?marked?. 3.9.24.4 badramb[1:0] - bad dram marker b this register implements ?failed-device? markers for the enhanced demand scrub algorithm. hardware ?marks? bad devices. the ?mark? is a number between 1 and 18 inclusive. a value of ?0_0000? indicates an ?un-marked? rank: all dram?s are presumed ?good?. only ranks containing x8 dram are ?marked?. device: 21 function: 0 offset: a8h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 22 function: 0 offset: a8h version: intel 5000p chipset bit attr default description 31:28 rwcst 0h rank7: error count for rank 7 27:24 rwcst 0h rank6: error count for rank 6 23:20 rwcst 0h rank5: error count for rank 5 19:16 rwcst 0h rank4: error count for rank 4 15:12 rwcst 0h rank3: error count for rank 3 11:8 rwcst 0h rank2: error count for rank 2 7:4 rwcst 0h rank1: error count for rank 1 3:0 rwcst 0h rank0: error count for rank 0 device: 21 function: 0 offset: ach version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 22 function: 0 offset: ach version: intel 5000p chipset bit attr default description 31:30 rv 00 reserved 29:25 rwcst 00h rank5: bad device in rank 5 24:20 rwcst 00h rank4: bad device in rank 4 19:15 rwcst 00h rank3: bad device in rank 3 14:10 rwcst 00h rank2: bad device in rank 2 9:5 rwcst 00h rank1: bad device in rank 1 4:0 rwcst 00h rank0: bad device in rank 0
register description 236 intel ? 5000x chipset memory controller hub (mch) datasheet 3.9.24.5 badcnt[1:0] - bad dram counter this register implements ?failing-device? co unters for the aliased uncorrectable error identification algorithm. ?count? double-adj acent symbol errors within x8 devices. ?drip? each counter after ?mc.badramth? pa trol scrub cycles through all of memory. values of ?mc.badramth? and ?0? cannot be ?dripped?. a value of ?mc.badramth? cannot be incremented. ?mark? the badram(a/b) register when a count reaches ?mc.badramth?. 3.9.24.6 fbdsbtxcfg[1:0][1:0]: fb-dimm southbound transmit configuration register this register controls the fb-dimm southbound i/o transmit configuration during normal operation. this value is programmed by bios on per channel basis. device: 21 function: 0 offset: b0h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 22 function: 0 offset: b0h version: intel 5000p chipset bit attr default description 15:10 rv 00h reserved 9:5 rwcst 00h rank7: bad device in rank 7 4:0 rwcst 00h rank6: bad device in rank 6 device: 21 function: 0 offset: b4h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 22 function: 0 offset: b4h version: intel 5000p chipset bit attr default description 31:28 rwcst 0000 rank7: adjacent x8 symbol error count in rank 7 27:24 rwcst 0000 rank6: adjacent x8 symbol error count in rank 6 23:20 rwcst 0000 rank5: adjacent x8 symbol error count in rank 5 19:16 rwcst 0000 rank4: adjacent x8 symbol error count in rank 4 15:12 rwcst 0000 rank3: adjacent x8 symbol error count in rank 3 11:8 rwcst 0000 rank2: adjacent x8 symbol error count in rank 2 7:4 rwcst 0000 rank1: adjacent x8 symbol error count in rank 1 3:0 rwcst 0000 rank0: adjacent x8 symbol error count in rank 0
intel ? 5000x chipset memory controller hub (mch) datasheet 237 register description 3.9.25 fb-dimm intel ibist registers 3.9.25.1 fbd[3:2]ibportctl: fb-d imm ibist port control register this register contains bits to control the operation of the intel ibist dft feature. device: 21 function: 0 offset: c1h, c0h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 22 function: 0 offset: c1h, c0h version: intel 5000p chipset bit attr default description 7:4 rv 0h reserved. 3:2 rwst 01 sbtxdrvcur: south bound tx drive current 00: 120% current 01: 100% current 10: 80% current 11: 60% current 1:0 rwst 00 sbtxdeemp: south bound tx de-emphasis with de-emphasis, the tx differential p- p swing (eye height) is maintained at nominal during data transitions, but drops down to the de-emphasized value when there is no transition between the previous bit and current bit 00: no de-emphasis 01: -3.5db 10: -6db 11: -9.5 db device: 22 function: 0 offset: 280h, 180h bit attr default description 31:26 rv 0h reserved 25 rwst 0 rxinvswpmd: rx inversion sweep mode 0: match sweep according to the sb-to-nb_mapping field in the ts1 training sequence. the default setting forces the rx inve rsion pointers to follow the unique northbound inversion across the port width. it is based on a modulo 5 of intel 5000p chipset mchmap bit setti ng. if e lanes example; if intel 5000p chipset mchmap = 0 then lanes [4:0] are used as the reference for checking lanes[13:10], [9:5], and [4:0]. if intel 5000p chipset mchmap = 1 then lanes [9:5] are used as the reference for checking lanes[13:10], [9:5], and [4:0]. for intel 5000p chipset mch lane [13] does not exist but it does participate in rotate-left-shift operations. 1: enable full inversion sweep across the entire port. when enabled the rx inversion po inters become a single entity. lanes [13:10] rotate left-shift completely across the width of the port. even though lane[13] is a dft lane it will be ?shifted through? to make the logic design easier. 0->1->2->3->4->5->6->7->8->9->10->11->12->13->0.
register description 238 intel ? 5000x chipset memory controller hub (mch) datasheet 24 rw 1 rxautoinvswpen: auto-inversion sweep enable this bit enable the inversion shift register to continuously rotate the pattern in the fibrxshft register. this register enables the inversion pattern to the lane at the bit position indicated by a logic 1. 0: disable auto-inversion 1: enable auto-inversion 23 rw 0 intel 5000p chipset mchmap: southbound to northbound mapping for loopback testing this bit indicates which set of lanes are replicated onto the northbound lanes. 0: lower sb lanes 1: upper sb lanes 22 rw 0 cmmstr: compliance measurement mode this bit forces the component into link reset then transmits the default intel ibist pattern set of a fixed binary ?1100? pattern continuously (depending on implementation) on all tx lanes until this bit is cleared. if the intel ibist engine is used for cmm, then the standa rd initialization sequence is follow with ts0, ts1 training set prior to entry into intel ibist. 0: disable cmm 1: enable cmm. this feature requires the intel ibist start bit to be set before the mode is enabled. 21:12 rwst 000h errcnt: error counter [9:0] total number of errors encountered in this port. errors are accumulated per lane. if several errors occurred in one phit time then a binary encoded value of the number of errors is added to the error count. 11:8 rost 00h errlnnum: error lane number [3:0] this points to the first lane that encoun tered an error. if more than one lane reports an error in a cycle, the most significant lane number that reported the error will be logged. 7:6 rwcst 0 errstat: port error status [1:0] when intel ibist is started, status goes to 01 until first start delimiter is received and then goes to 00 until the end or to10/11 as appropriate. 00: no error. 01: did not receive first start delimiter. 10: transmission error (first error). 11: reserved. 5rw 1 autoinvswpen: auto-inversion sweep enable this bit enable the inversion shift register to continuously rotate the pattern in the fibtxshft and fibrxshft registers. these registers enable the inversion pattern to the lane at the bit position indicated by a logic 1. 0: disable auto-inversion 1: enable auto-inversion 4rw 1 stoponerr: stop intel ib ist on error 0: do not stop on error, only update error counter 1: stop on error 3rw 0 loopcon: loop forever 0: no looping 1: loop forever 2rwcst 0 ibdone: intel ibist done flag 0: not done 1: done device: 22 function: 0 offset: 280h, 180h bit attr default description
intel ? 5000x chipset memory controller hub (mch) datasheet 239 register description 1rwst 1 mstrmd: master mode enable when this bit is set the next ts1 traini ng set that has the loopback bit set will cause the transmitter to operate as a mast er. even though the intel ibist is in the loopback state it is not in loopback. 0: disable master mode. this component will not enter into master when a ts1 training set with loopback bit set. 1: enable master mode on the next ts1 training with loopback bit set 0rwst 0 ibstr: ibist start when set, it enables receiver logic to l ook for start delimiters during ts1 training set. if the mstrmd bit is set, the start bit enables the transmit state machine to start transmitting patterns during the ts1 training set. the rece iver is enable in both cases. for master-slave mode, the pattern will be looped back as defined in the fb- dimm spec. in master-master mode, the ibist controller will originate patterns and also check the incoming pattern for errors. 0: stop ibist transmitter 1: start ibist transmitter device: 22 function: 0 offset: 280h, 180h bit attr default description
register description 240 intel ? 5000x chipset memory controller hub (mch) datasheet 3.9.25.2 fbd[1:0]ibportctl: fb-dimm intel ibist port control register this register contains bits to control the operation of the intel ibist dft feature. device: 21 function: 0 offset: 280h, 180h bit attr default description 31:26 rv 0h reserved 25 rwst 0 rxinvswpmd: rx inversion sweep mode 0: match sweep according to the sb-to-nb_mapping field in the ts1 training sequence. the default setting forces the rx in version pointers to follow the unique northbound inversion across the port width. it is based on a modulo 5 of intel 5000p chipset mchmap bit setting. if e lanes example; if intel 5000p chipset mchmap = 0 then lanes [4:0] are used as the reference for checking lanes[13:10], [9:5], and [4:0]. if intel 5000p chipset mchmap = 1 then lanes [9:5] are used as the reference for checking lanes[13:10], [9:5], and [4:0]. for intel 5000p chipset mch lane [13] does not exist but it does participate in rotate-left-shift operations. 1: enable full inversion sweep across the entire port. when enabled the rx inversion po inters become a single entity. lanes [13:10] rotate left-shift completely across the width of the port. even though lane[13] is a dft lane it will be ?shifted through? to make the logic design easier. 0->1->2->3->4->5->6->7->8->9->10->11->12->13->0. 24 rw 1 rxautoinvswpen: auto-inversion sweep enable this bit enable the inversion shift register to continuously rotate the pattern in the fibrxshft register. 0: disable auto-inversion 1: enable auto-inversion 23 rw 0 intel 5000p chipset mchmap: southbound to northbound mapping for loopback testing this bit indicates which set of lanes are replicated onto the northbound lanes. 0: lower sb lanes 1: upper sb lanes 22 rw 0 cmmstr: compliance measurement mode this bit forces the component into link reset then transmits the contents of the default intel ibist pattern set conti nuously (depending on implementation) on all tx lanes until this bit is cleared and th e ibstr bit is cleared. if the intel ibist engine is used for cmm then the standard initialization sequence is follow with ts0, ts1 training set prior to entry into intel ibist. 0: disable cmm 1: enable cmm. this feature requires the intel ibist start bit to be set before the mode is enabled. 21:12 rwst 000h errcnt: error counter [9:0] total number of errors encountered in this port. errors are accumulated per lane. if several errors occurred in one phit time then a binary encoded value of the number of errors is added to the error count. 11:8 rost 00h errlnnum: error lane number [3:0] this points to the first lane that encoun tered an error. if more than one lane reports an error in a cycle, the most significant lane number that reported the error will be logged. 7:6 rwcst 0 errstat: port error status [1:0] when intel ibist is started, status goes to 01 until first start delimiter is received and then goes to 00 until the end or to10/11 as appropriate. 00: no error. 01: did not receive first start delimiter. 10: transmission error (first error). 11: reserved.
intel ? 5000x chipset memory controller hub (mch) datasheet 241 register description 5rw 1 txautoinvswpen: auto-inversion sweep enable this bit enable the inversion shift register to continuously rotate the pattern in the fibtxshft register. 0: disable auto-inversion 1: enable auto-inversion 4rw 1 stoponerr: stop intel ibist on error 0: do not stop on error, only update error counter 1: stop on error 3rw 0 loopcon: loop continuously enable ibist operations to loop continuously. the intel ibist pattern generator executes the each pattern loop for the counts specified in the bit fields but the overall loop runs continuously. this bit should be protected (gated) by the component?s security mechanisms. 0: no continuous operation 1: loop continuously 2rwcst 0 ibdone: intel ibist done flag 0: not done 1: done 1rwst 1 mstrmd: master mode enable when this bit is set the next ts1 traini ng set that has the loopback bit set will cause the transmitter to operate as a mast er. even though the intel ibist is in the loopback state it is not in loopback. 0: disable master mode. this component will not enter into master when a ts1 training set with loopback bit set. 1: enable master mode on the next ts1 training with loopback bit set 0rwst 0 ibstr: intel ibist start when set, it enables receiver logic to l ook for start delimiters during ts1 training set. if the mstrmd bit is set, the start bit enables the transmit state machine to start transmitting patterns during the ts1 training set. the rece iver is enable in both cases. for master-slave mode, the pattern will be looped back as defined in the fb- dimm spec. in master-master mode, the intel ibist controller will originate patterns and also check the incoming pattern for errors. 0: stop intel ibist transmitter 1: start intel ibist transmitter device: 21 function: 0 offset: 280h, 180h bit attr default description
register description 242 intel ? 5000x chipset memory controller hub (mch) datasheet 3.9.25.3 fbd[3:2]ibtxpgctl: fb-dimm in tel ibist pattern generator control register this register contains bits to control the operation of the intel ibist pattern generator. device: 22 function: 0 offset: 284h, 184h bit attr default description 31:26 rwst 04h ovrlopcnt: overall loop count[5:0] 0h: send no intel ibist data in payload 1h-3fh: the number of times to loop through all the patterns 25:21 rwst 0h cnstgencnt: constant generator loop counter[4:0] 00h: disable constant generator output 01h: 1fh the number of times the modulo-n counter should be repeated before going to the next pattern type. each buffer transfer is composed of two frames (loop counts of 24-bits each). 20 rwst 0 cnstgenset: constant generator setting 0: generate 0 1: generate 1 19:13 rwst 19h modlopcnt: modulo-n loop counter [7:0] each count represents 24-bits of the patte rn specified by the modperiod bit field. 00h: disable pattern output 01h: 7fh the number of times the pattern buffer should loop before going to the next 12:10 rwst 1h modperiod: period of the modulo-n counter 001: l/2 0101_0101_0101_0101_0101_0101 010: l/4 0011_0011_0011_0011_0011_0011 011: l/6 0001_1100_0111_0001_1100_0111 100: l/8 0000_1111_0000_1111_0000_1111 110: l/12 0000_0000_0000_1111_1111_1111 9:3 rwst 19h pattlopcnt: pattern buffer loop counter[6:0] 00h: disable pattern output 01h-3fh: the number of times the pattern buffer should be repeated before going to the next pattern type. each buffer transfer is composed of two frames (loop counts of 24-bits each). 2:0 rwst 000 ptgenord: pattern generation order 000: pattern store + modulo n cntr + constant generator 001: pattern store + constant generator + modulo n cntr 010: modulo n cntr + pattern store + constant generator 011: modulo n cntr + constant generator + pattern store 100: constant generator + pattern store + modulo n cntr 101: constant generator + modulo n cntr + pattern store 110: reserved 111: reserved
intel ? 5000x chipset memory controller hub (mch) datasheet 243 register description 3.9.25.4 fbd[1:0]ibtxpgctl: fb-dimm in tel ibist pattern generator control register this register contains bits to control the operation of the intel ibist pattern generator. device: 21 function: 0 offset: 284h, 184h bit attr default description 31:26 rwst 04h ovrlopcnt: overall loop count[5:0] 0h: send no ibist data in payload 1h-3fh: the number of times to loop through all the patterns 25:21 rwst 0h cnstgencnt: constant generator loop counter[4:0] 00h: disable constant generator output 01h: 1fh the number of times the modulo-n counter should be repeated before going to the next pattern type. each buffe r transfer is composed of two frames (loop counts of 24-bits each). 20 rwst 0 cnstgenset: constant generator setting 0: generate 0 1: generate 1 19:13 rwst 19h modlopcnt: modulo-n loop counter each count represents 24-bits of the patte rn specified by the modperiod bit field. 00h: disable pattern output 01h: 7fh the number of times the pattern bu ffer should loop before going to the next 12:10 rwst 1h modperiod: period of the modulo-n counter 001: l/2 0101_0101_0101_0101_0101_0101 010: l/4 0011_0011_0011_0011_0011_0011 011: l/6 0001_1100_0111_0001_1100_0111 100: l/8 0000_1111_0000_1111_0000_1111 110: l/12 0000_0000_0000_1111_1111_1111 9:3 rwst 19h pattlopcnt: pattern buffer loop counter[6:0] 00h: disable pattern output 01h-3fh: the number of times the pattern buffer should be repeated before going to the next pattern type. each buffer tran sfer is composed of two frames (loop counts of 24-bits each). 2:0 rwst 000 ptgenord: pattern generation order 000: pattern store + modulo n cntr + constant generator 001: pattern store + constant generator + modulo n cntr 010: modulo n cntr + pattern store + constant generator 011: modulo n cntr + constant generator + pattern store 100: constant generator + pattern store + modulo n cntr 101: constant generator + modu lo n cntr + pattern store 110: reserved 111: reserved
register description 244 intel ? 5000x chipset memory controller hub (mch) datasheet 3.9.25.5 fbd[3:2]ibpatbuf: fb-dimm intel bist pattern buffer register this register contains the pattern bits used in intel ibist operations. 3.9.25.6 fbd[1:0]ibpatbuf: fb-dimm in tel ibist pattern buffer register this register contains the pattern bits used in intel ibist operations. 3.9.25.7 fbd[3:2]ibtxmsk: in tel ibist transmitter mask this register determines which lanes are enabled for intel ibist operations. these bits also control the power saving features of each lane. if a particular lane is masked off, the power to that lane is reduced as much as possible. 3.9.25.8 fbd[1:0]ibtxmsk: in tel ibist transmitter mask this register determines which lanes are enabled for intel ibist operations. these bits also control the power saving features of each lane. if a particular lane is masked off, the power to that lane is reduced as much as possible. device: 22 function: 0 offset: 288h, 188h bit attr default description 31:24 rv 0 reserved 23:0 rwst 02ccfdh ibpatbuf: ibist pattern buffer pattern buffer storing the default an d the user programmable pattern. default: 0000_0010_1100_1100_1111_1101 device: 21 function: 0 offset: 288h, 188h bit attr default description 31:24 rv 0 reserved 23:0 rwst 02ccfdh ibpatbuf: ibist pattern buffer pattern buffer storing the default an d the user programmable pattern. default: 0000_0010_1100_1100_1111_1101 device: 22 function: 0 offset: 28ch, 18ch bit attr default description 31:14 rv 0h reserved 13:10 rwst 0h txmaskhvm: transmit mask extra dft pins for hvm symmetry selects which lanes to enable for testing. a lane that is not selected remains in electrical idle. 9:0 rwst 3ffh txmask: transmit mask selects which lanes to enable for testing. a lane that is not selected remains in electrical idle. device: 21 function: 0 offset: 28ch, 18ch bit attr default description 31:14 rv 0h reserved
intel ? 5000x chipset memory controller hub (mch) datasheet 245 register description 3.9.25.9 fbd[3:2]ibrxmsk: intel ibist receiver mask this register determines which lanes are enabled for intel ibist operations. these bits also control the power saving features of each lane. if a particular lane is masked off, the power to that lane is reduced as much as possible. 3.9.25.10 fbd[1:0]ibrxmsk: intel ibist receiver mask this register determines which lanes are enabled for intel ibist operations. these bits also control the power saving features of each lane. if a particular lane is masked off, the power to that lane is reduced as much as possible. 3.9.25.11 fbd[3:2]ibtxshft: intel ibis t transmit shift inversion register this register indicates which channel is currently inverting the pattern to create cross talk conditions on the port. 13:10 rwst 0h txmaskhvm: transmit mask extra dft pins for hvm symmetry selects which lanes to enable for testing. a lane that is not selected remains in electrical idle. 9:0 rwst 3ffh txmask: transmit mask selects which lanes to enable for testing. a lane that is not selected remains in electrical idle. device: 21 function: 0 offset: 28ch, 18ch bit attr default description device: 22 function: 0 offset: 290h, 190h bit attr default description 31:14 rv 0h reserved 13:0 rwst 1fffh rxmask: receive mask selects which lanes to enable for testing. an rx lane that is not selected is not included in rx channel training does not contribute to the accumulation of error counts. device: 21 function: 0 offset: 290h, 190h bit attr default description 31:14 rv 0h reserved 13:0 rwst 1fffh rxmask: receive mask selects which lanes to enable for testing. an rx lane that is not selected is not included in rx channel training does not contribute to the accumulation of error counts. device: 22 function: 0 offset: 294h, 194h bit attr default description 31:14 rv 0h reserved
register description 246 intel ? 5000x chipset memory controller hub (mch) datasheet 3.9.25.12 fbd[1:0]ibtxshft: intel ibis t transmit shift inversion register this register indicates which channel is currently inverting the pattern to create cross talk conditions on the port. 3.9.25.13 fbd[3:2]ibrxshf t: intel ibist receive shift inversion register this register indicates which channel is currently inverting the pattern to create cross talk conditions on the port. 13:10 rwst 0h txinvshfthvm: transmit inversion shift register extra dft pins for hvm symmetry the pattern loaded in this register indicates which lanes are used for inversion. a logic 1 enables the lane conne cted to a particular bit position to invert the pattern that is being transmitte d. because this is a shift register the initial value will be left-shifted at the end of the loop count during intel ibist operations. 9:0 rwst 001h txinvshft: transmitter inversion shift register the pattern loaded in this register indicates which lanes are used for inversion. a logic 1 enables the lane conne cted to a particular bit position to invert the pattern that is being transmitte d. because this is a shift register the initial value will be left-shifted at the end of the loop count during intel ibist operations. device: 22 function: 0 offset: 294h, 194h bit attr default description device: 21 function: 0 offset: 294h, 194h bit attr default description 31:14 rv 0h reserved 13:10 rwst 0h txinvshfthvm: transmit inversion shift register extra dft pins for hvm symmetry the pattern loaded in this register indicates which lanes are used for inversion. a logic 1 enables the lane conne cted to a particular bit position to invert the pattern that is being transmitte d. because this is a shift register the initial value will be left-shifted at the end of the loop count during intel ibist operations. 9:0 rwst 001h txinvshft: transmitter inversion shift register the pattern loaded in this register indicates which lanes are used for inversion. a logic 1 enables the lane conne cted to a particular bit position to invert the pattern that is being transmitte d. because this is a shift register the initial value will be left-shifted at the end of the loop count during intel ibist operations. device: 22 function: 0 offset: 298h, 198h bit attr default description 31:14 rv 0h reserved 13 rwst 0 rxinvshfthi: receiver inversion shift register for dft the pattern loaded in this bit fiel d indicates which lanes are used for inversion. a logic 1 enables the lane conne cted to a particular bit position to invert the pattern that is being transmi tted. this bit location will experience rotate-left-shift operation with bits[12:0].
intel ? 5000x chipset memory controller hub (mch) datasheet 247 register description 3.9.25.14 fbd[1:0]ibrxshft: intel ib ist receive shift inversion register this register indicates which channel is currently inverting the pattern to create cross talk conditions on the port. 3.9.25.15 fbd[3:2]lnerr: ibist receive lane error register this register enables ibist operations for individual lanes. 3.9.25.16 fbd[1:0]lnerr: intel ib ist receive lane error register this register enables intel ibist operations for individual lanes. 12:0 rwst 0001h rxinvshft: receiver inversion shift register the pattern loaded in this register indicates which lanes are used for inversion. a logic 1 enables the lane connected to a particular bit position to invert the pattern that is being transmitte d. this register acts as a rotate-left shift register regardless of the setting of rxinvswpmd bit. the modulo-5 value is used to compare each sub-section of the northbound lanes for error checking. device: 22 function: 0 offset: 298h, 198h bit attr default description device: 21 function: 0 offset: 298h, 198h bit attr default description 31:14 rv 0h reserved 13 rwst 0 rxinvshfthi: receiver inversion shift register for dft the pattern loaded in this bit fiel d indicates which lanes are used for inversion. a logic 1 enables the lane connected to a particular bit position to invert the pattern that is being transmitted. this bit location will experience rotate-left-shift operation with bits[12:0]. 12:0 rwst 0001h rxinvshft: receiver inversion shift register the pattern loaded in this register indicates which lanes are used for inversion. a logic 1 enables the lane connected to a particular bit position to invert the pattern that is being transmitte d. this register acts as a rotate-left shift register regardless of the setting of rxinvswpmd bit. the modulo-5 value is used to compare each sub-section of the northbound lanes for error checking. device: 22 function: 0 offset: 29ch, 19ch bit attr default description 31:14 rv 0h reserved 13 rost 0 rxerrstat: receive error lane status for dft. this register records the error from lane 13 of this port. 12:0 rost 0 rxerrstat: receive error lane status. this register records the errors from all lanes of this port. device: 21 function: 0 offset: 29ch, 19ch bit attr default description 31:14 rv 0h reserved
register description 248 intel ? 5000x chipset memory controller hub (mch) datasheet 3.9.25.17 fbd[3:2]ibrxpgctl: fb-dimm intel ibist rx pattern generator control register this register contains bits to control the operation of the rx pattern generator. 13 rost 0 rxerrstat: receive error lane status for dft. this register records the error from lane 13 of this port. 12:0 rost 0 rxerrstat: receive error lane status. this register records the errors from all lanes of this port. device: 21 function: 0 offset: 29ch, 19ch bit attr default description device: 22 function: 0 offset: 2a0h, 1a0h bit attr default description 31:26 rwst 04h ovrlopcnt: overall loop count[5:0] 0h: send no intel ibist data in payload 1h-3fh: the number of times to loop through all the patterns 25:21 rwst 0h cnstgencnt: constant generator loop counter[4:0] 00h: disable constant generator output 01h: 1fh the number of times the modulo-n counter should be repeated before going to the next pattern type. each buffer transfer is composed of two frames (loop counts of 24-bits each). 20 rwst 0 cnstgenset: constant generator setting 0: generate 0 1: generate 1 19:13 rwst 19h modlopcnt: modulo-n loop counter [7:0] each count represents 24-bits of the patte rn specified by the modperiod bit field. 00h: disable pattern output 01h: 7fh the number of times the pattern buffer should loop before going to the next 12:10 rwst 1h modperiod: period of the modulo-n counter 001: l/2 0101_0101_0101_0101_0101_0101 010: l/4 0011_0011_0011_0011_0011_0011 011: l/6 0001_1100_0111_0001_1100_0111 100: l/8 0000_1111_0000_1111_0000_1111 110: l/12 0000_0000_0000_1111_1111_1111 9:3 rwst 19h pattlopcnt: pattern buffer loop counter[6:0] 00h: disable pattern output 01h-3fh: the number of times the pattern buffer should be repeated before going to the next pattern type. each buffer transfer is composed of two frames (loop counts of 24-bits each). 2:0 rwst 000 ptgenord: pattern generation order 000: pattern store + modulo n cntr + constant generator 001: pattern store + constant generator + modulo n cntr 010: modulo n cntr + pattern store + constant generator 011: modulo n cntr + constant generator + pattern store 100: constant generator + pattern store + modulo n cntr 101: constant generator + modulo n cntr + pattern store 110: reserved 111: reserved
intel ? 5000x chipset memory controller hub (mch) datasheet 249 register description 3.9.25.18 fbd[1:0]ibrxpgctl: fb-dimm intel ibist rx pa ttern generator control register this register contains bits to control the operation of the rx pattern generator. device: 21 function: 0 offset: 2a0h, 1a0h bit attr default description 31:26 rwst 04h ovrlopcnt: overall loop count[5:0] 0h: send no intel ib ist data in payload 1h-3fh: the number of times to loop through all the patterns 25:21 rwst 0h cnstgencnt: constant generator loop counter[4:0] 00h: disable constant generator output 01h: 1fh the number of times the modulo-n counter should be repeated before going to the next pattern type. each buffe r transfer is composed of two frames (loop counts of 24-bits each). 20 rwst 0 cnstgenset: constant generator setting 0: generate 0 1: generate 1 19:13 rwst 19h modlopcnt: modulo-n loop counter each count represents 24-bits of the patte rn specified by the modperiod bit field. 00h: disable pattern output 01h: 7fh the number of times the pattern bu ffer should loop before going to the next 12:10 rwst 1h modperiod: period of the modulo-n counter 001: l/2 0101_0101_0101_0101_0101_0101 010: l/4 0011_0011_0011_0011_0011_0011 011: l/6 0001_1100_0111_0001_1100_0111 100: l/8 0000_1111_0000_1111_0000_1111 110: l/12 0000_0000_0000_1111_1111_1111 9:3 rwst 19h pattlopcnt: pattern buffer loop counter[6:0] 00h: disable pattern output 01h-3fh: the number of times the pattern buffer should be repeated before going to the next pattern type. each buffer tran sfer is composed of two frames (loop counts of 24-bits each). 2:0 rwst 000 ptgenord: pattern generation order 000: pattern store + modulo n cntr + constant generator 001: pattern store + constant generator + modulo n cntr 010: modulo n cntr + pattern store + constant generator 011: modulo n cntr + constant generator + pattern store 100: constant generator + pattern store + modulo n cntr 101: constant generator + modu lo n cntr + pattern store 110: reserved 111: reserved
register description 250 intel ? 5000x chipset memory controller hub (mch) datasheet 3.9.25.19 fbd[3:2]ibpatbuf2: fb-dimm in tel ibist pattern buffer 2 register this register contains the pattern bits used in intel ibist operations. 3.9.25.20 fbd[1:0]ibpatbuf2: fb-dimm in tel ibist pattern buffer 2 register this register contains the pattern bits used in intel ibist operations. 3.9.25.21 fbd[3:2]ibtxpat2en: inte l ibist tx pattern buffer 2 enable this register enables which channels are inverted when intel ibist operations are activated. 3.9.25.22 fbd[1:0]ibtxpat2en: inte l ibist tx pattern buffer 2 enable this register enables which channels are inverted when intel ibist operations are activated. device: 22 function: 0 offset: 2a4h, 1a4h bit attr default description 31:24 rv 0 reserved 23:0 rwst 02ccfdh ibpatbuf: intel ibist pattern buffer pattern buffer storing the default an d the user programmable pattern. default: 0000_0010_1100_1100_1111_1101 device: 21 function: 0 offset: 2a4h, 1a4h bit attr default description 31:24 rv 0 reserved 23:0 rwst 02ccfdh ibpatbuf: intel ibist pattern buffer pattern buffer storing the default an d the user programmable pattern. default: 0000_0010_1100_1100_1111_1101 device: 22 function: 0 offset: 2a8h, 1a8h bit attr default description 31:14 rv 0h reserved 13:10 rwst fh txpatt2hvmen: receiver pattern buffer 2 enable for the hvm lanes selects which channels to enab le the second pattern buffer. 9:0 rwst 3ffh txpatt2en: receiver pattern buffer 2 enable selects which channels to enab le the second pattern buffer.
intel ? 5000x chipset memory controller hub (mch) datasheet 251 register description 3.9.25.23 fbd[3:2]ibrxpat2en: intel ibist rx pattern buffer 2 enable this register enables inversion pattern testing on individual lanes. 3.9.25.24 fbd[1:0]ibrxpat2en: intel ibist rx pattern buffer 2 enable this register enables inversion pattern testing on individual lanes. device: 21 function: 0 offset: 2a8h, 1a8h bit attr default description 31:14 rv 0h reserved 13:10 rwst fh txpatt2hvmen: receiver pattern buffer 2 enable for the hvm lanes selects which channels to enab le the second pattern buffer. 9:0 rwst 3ffh txpatt2en: receiver pattern buffer 2 enable selects which channels to enab le the second pattern buffer. device: 22 function: 0 offset: 2ach, 1ach bit attr default description 31:14 rv 0h reserved 13:0 rwst 3fffh rxpatt2en: receiver pattern buffer 2 enable selects which channels to enab le the second pattern buffer. device: 21 function: 0 offset: 2ach, 1ach bit attr default description 31:14 rv 0h reserved 13:0 rwst 3fffh rxpatt2en: receiver pattern buffer 2 enable selects which channels to enab le the second pattern buffer.
register description 252 intel ? 5000x chipset memory controller hub (mch) datasheet 3.9.26 serial presence detect registers there are two sets of the following register s, one set for each fb-dimm branch. they each appear in function 0 of different devices as shown in ta b l e 3 - 3 . 3.9.26.1 spd[1:0][1:0] - serial pr esence detect status register this register provides the interface to the spd bus (scl and sda signals) that is used to access the serial presence detect eeprom that defines the technology, configuration, and speed of th e dimm?s controlled by the mch. 3.9.26.2 spdcmd[1:0][1:0] - serial presence detect command register a write to this register initiates a dimm eeprom access through the spd bus. device: 21 function: 0 offset: 76h, 74h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 22 function: 0 offset: 76h, 74h version: intel 5000p chipset bit attr default description 15 ro 0 rdo: read data valid. this bit is set by the amb when the data field of this register receives read data from the spd eeprom after successful co mpletion of an sp dr command. it is cleared by the intel 5000p chipset mch when a subsequent spdr command is issued. 14 ro 0 wod: write operation done. this bit is set by the intel 5000p chipset mch when a spdw command has been completed on the spd bus. it is cleare d by the intel 5000p chipset mch when a subsequent spdw command is issued. 13 ro 0 sbe: spd bus error. this bit is set by the intel 5000p chipset mch if it initiates an spd bus transaction that does not complete successfully. it is cleared by the amb when an spdr or spdw command is issued. 12 ro 0 busy: busy state. this bit is set by the intel 5000p chipse t mch while an spd command is executing. 11:8 rv 0h reserved. 7:0 ro 00h data: data. holds data read from spdr commands.
intel ? 5000x chipset memory controller hub (mch) datasheet 253 register description 3.10 dma engine configuration registers 3.10.1 pcicmd: pci command register device: 21 function: 0 offset: 7ch, 78h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 22 function: 0 offset: 7ch, 78h version: intel 5000p chipset bit attr default description 31:28 rwst 1010 dti: device type identifier. this field specifies the device type identifi er. only devices with this device-type will respond to commands. ?1010? specifies ee prom?s. ?0110? specifies a write-protect operation for an eeprom. other identifiers can be specified to target non-eeprom devices on the spd bus. 27 rwst 1 ckovrd: clock override. ?0? = clock signal is driven low, overriding writing a ?1? to cmd. ?1? = clock signal is released high, allowing normal operation of cmd. toggling this bit can be used to ?move? the port out of a ?stuck? state. 26:24 rwst 000 sa: slave address. this field identifies the dimm eeprom to be accessed through the spd register. 23:16 rwst 00h ba: byte address. this field identifies the byte address to be accessed through the spd register. 15:8 rwst 00h data: data. holds data to be written by spdw commands. 7:1 rv 0h reserved 0rwst 0 cmd: command. writing a ?0? to this bit initiates an spdr command. writing a ?1? to this bit initiates an spdw command. device: 8 function: 0 offset: 04h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 15:11 rv 0h reserved 10 rw 0 intxdisable: interrupt disable this bit controls the ability of the dma engine device to assert a legacy pci interrupt during dma comp letions or dma errors. 1: legacy interrupt mode is disabled 0: legacy interrupt mode is enabled 9ro0 fb2b: fast back-to-back enable this bit does not apply to the dma engine device and hardwired to 0.
register description 254 intel ? 5000x chipset memory controller hub (mch) datasheet the pci command register follows a subset of the pci local bus specification, revision 2.3 specification. this register provides the basic control of the ability of the dma engine device to initiate and respond to transactions sent to it and maintains compatibility with pci configuration space. 8rw0 serre: serr message enable this bit indicates whether the dma engine device is allowed to signal a serr condition. this field handles the reporting of fata l and non-fatal errors by enabling the error pins err[2:0]. 1: the dma engine device is enabled to send fatal/non-fatal errors. 0: the dma engine device is disabled from generating fatal/non-fatal errors. 7rv0 reserved 6rw0 perrrsp: parity error response controls the response when a parity error is detected in the dma engine 1: the device can report parity errors 0: parity errors can be ignored by the device. 5:4 rv 00 reserved 3ro0 spcen: special cycle enable this bit does not apply to the dma engine device. 2rw0 bme: bus master enable controls the ability for the dma engine de vice to initiate transactions to memory including mmio 1: enables the dma engine device to successfully complete memory read/write requests. 0: disables upstream memory writes/reads if this bit is not set and the dma engine is programmed by software to process descriptors, the chipset w ill flag read(write) errors (*dma8/*dma9) and also record the errors in the chanerr register s when it attempts to issue cacheline requests to memory. 1rw0 maen: memory access enable controls the ability for the dma engine device to respond to memory mapped i/o transactions initiated in the intel 5000p chipset mch in its range. 1: allow mmio accesses in the dma engine 0: disable mmio accesses in dma engine this only applies to access cb_bar space in device 8, fn 1 where the mmio space resides (requests from both fast/s low paths will be master-aborted) 0ro0 ioaen: i/o access enable controls the ability for the dma engine device to respond to legacy i/o transactions. the dma engine device does not support/allow legacy i/o cycles. device: 8 function: 0 offset: 04h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description
intel ? 5000x chipset memory controller hub (mch) datasheet 255 register description 3.10.2 pcists: pci status register the pci status register follows a subset of the pci local bus specification, revision 2.3 specification. this register maintains comp atibility with pci configuration space. since this register is part of the standard pci header, there is a pcists register per pci function. device: 8 function: 0 offset: 06h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 15 rwc 0 dpe: detected parity error this bit is set when the dma engine device receives an uncorrectable data error or address/control parity errors regardless of the parity error enable bit (perre). this applies only to parity errors that target the dma engine device (inbound/outbound direction). the detected parity error maps to b1, f6, m2 and m4 (uncorrectable data error from fsb, memory or internal sources). the dma engine also records the data parity error in bit[6] ( cdata_par_err )of the chanerr register. 14 rwc 0 sse: signalled system error 1: the dma engine device reported internal fatal/non fatal errors (dma0-15) through the err[2:0] pins with serre bi t enabled. software clears this bit by writing a ?1? to it. 0: no internal dma engine device port errors are signaled. 13 ro 0 rma: received master abort status this field is hardwired to 0 as there is no master abort for the dma operations 12 rwc 0 rta: received target abort status this field is hardwired to 0 as there is no target abort for the dma operations 11 rwc 0 sta: signalled target abort status : this field is hardwired to 0 10:9 ro 00 devselt: devsel# timing : this bit does not apply to the dma engine device. 8rwc0 mdierr: master data integrity error this bit is set by the dma engine device if the parity error enable bit (perre) is set and it receives error b1, f2, f6, m2 and m4 (u ncorrectable data error or address/control parity errors or an internal failure). if the perrrsp bit in the section 3.10.1 is cleared, this bit is never set. 7ro0 fb2b: fast back-to-back capable not applicable to dma engine. hardwired to 0. 6rv0 reserved 5ro0 66mhzcap: 66mhz capable . not applicable to dma engine. hardwired to 0. 4ro1 capl: capability list implemented : this bit indicated that the dma engine de vice implements a pci capability list. see capptr at offset 34h 3ro0 intxst: i ntx state this bit is set by the hardware when the dma engine device issues a legacy intx (pending) and is reset when the intx is deasserted. the intx status bit should be deasserted when all the relevant status bits/events viz dma errors/completions that require legacy interrupts are cleared by software. 2:0 rv 000 reserved
register description 256 intel ? 5000x chipset memory controller hub (mch) datasheet 3.10.3 ccr: class code register the bits in this register are writable once by bios in order to allow the device to be programmable either as an os-visible device [088000h](implementing a driver) or a chipset host bridge device [060000h] (relying on bios code and/or pure hardware control for programming the dma engine registers). the default value of the ccr is set to 088000h (corresponding to an integrated device in the root port). 3.10.4 cb_bar: dma engine base addr ess register this dma engine base address register marks the memory-mapped registers used for the dma functionality. device: 8 function: 0 offset: 09h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 23:16 rwo 08h base class code : a 08h code indicates that the dma engine device is a peripheral device 1 . a 06h code is used to indicate a host bridge device. default: 08h notes: 1. a peripheral device in this case denotes an integrated device in the root complex. 15:8 rwo 80h sub-class code : an 80h code indicates that the dma engine device is a non- specific peripheral device. a 00h code is used to indicate a host bridge device. default: 80h 7:0 rwo 0h register-level programming interface : this field identifies a default value for non-specific prog ramming requirements. device: 8 function: 0 offset: 10h version: intel 5000p chipset bit attr default description 63:40 ro 0h cb_base_win_upper: upper dmabase window : the upper bits of the 64-bit addressable space are initialized to 0 as default and is unusable in intel 5000 series chipset. 39:10 rw 003f9c00h cb_base_win: dmabase window this marks the 1kb memory-mapped registers used for the chipset dma and can be placed in any mmio region (low/h igh) within the physical limits of the system. for instance the intel 5000p chipset mch uses only 40-bit addressable space. hence bits 39:10 are assumed to be valid and also contains the default value of the cb_bar in the fe70_0000h to fe70_03ffh range. 9:4 rv 0h reserved 3ro0 pref: prefetchable the dma registers are not prefetchable. 2:1 ro 10 type: ty p e the dma registers is 64-bit address space and can be placed anywhere within the addressable region of the intel 5000 series chipset (up to 40-bits). 0ro0 mem_space: memory space this base address register indicates memory space.
intel ? 5000x chipset memory controller hub (mch) datasheet 257 register description 3.10.5 capptr: capabili ty pointer register 3.10.6 intl: interrupt line register the interrupt line register is used to co mmunicate interrupt lin e routing information between initialization code and the device dr iver. the intel 5000 series mch does not have a dedicated interrupt line and is not used. 3.10.7 intp: interrupt pin register the intp register identifies legacy inte rrupts for inta, intb, intc and intd as determined by bios/firmware. these are emulated over the esi port using the assert_intx commands as appropriate. 3.10.8 power management capability structure the dma engine integrated device within the mch incorporates power management capability with d0 (working) and a pseudo d3 hot/cold states (sleep) that can be controlled independently through software. from a software perspective, the d3 states convey information to the power controller that the device is in the sleep mode though the physical entity inside the chipset may be fully powered. during transition 1 from d0 to d3, it will ensure that all pendin g dma channels are completed in full. device: 8 function: 0 offset: 34h version: intel 5000p chipset bit attr default description 7:0 ro 50h capptr: capability pointer this register field points to the first ca pability. pm structur e in the dma engine device. device: 8 function: 0 offset: 3ch version: intel 5000p chipset bit attr default description 7:0 rwo 00h intl: interrupt line bios writes the interrupt rout ing information to this regist er to indicate which input of the interrupt controller this pci-express port is connected to. not used in the intel 5000 series mch since the pci-express port does not have an interrupt lines. device: 8 function: 0 offset: 3dh version: intel 5000p chipset bit attr default description 7:0 rwo 01h intp: interrupt pin this field defines the type of interrupt to generate for the pci express port. 001: generate inta 010: generate intb 011: generate intc 100: generate intd others: reserved
register description 258 intel ? 5000x chipset memory controller hub (mch) datasheet 3.10.8.1 pmcap - power management capabilities register the pm capabilities register defines the capability id, next pointer and other power management related support. the following pm registers /capabilities are added for software compliance. 1. when software initiates an s0 => s3 transition, it should make the dma engine device to enter d3 before completing the power ma nagement handshake with the mch. device: 8 function: 0 offset: 50h version: intel 5000p chipset bit attr default description 31:27 ro 11001 pmes: pme support identifies power states which assert pmeout. bits 31, 30 and 27 must be set to '1' for pci-pci bridge structures representing ports on root complexes. the definition of these bits is taken from the pci bus power management interface specification revision 1.1. xxxx1b - pmeout can be asserted from d0 xxx1xb - pmeout can be asserted from d1 (not supported by intel 5000p chipset mch) xx1xxb - pmeout can be asserted from d2 (not supported by intel 5000p chipset mch) x1xxxb - pmeout can be asserted from d3 hot 1xxxxb - pmeout can be asserted from d3 cold 26 ro 0 d2s: d2 support the intel 5000p chipset mch does not support power management state d2. 25 ro 0 d1s: d1 support the intel 5000p chipset mch does not support power management state d1. 24:22 ro 0h auxcur: aux current 21 ro 0 dsi: device specific initialization 20 rv 0 reserved. 19 ro 0 pmeclk: pme clock this field is hardwired to 0h. 18:16 ro 010 ver: version this field is set to 2h as versi on number from the pci express 1.0 specification. 15:8 ro 58h nxtcapptr: next capability pointer this field is set to offset 58h for the next capability structure (msi) in the pci 2.3 compatible space. 7:0 ro 01h capid: capability id provides the pm capabili ty id assigned by pci-sig.
intel ? 5000x chipset memory controller hub (mch) datasheet 259 register description 3.10.8.2 pmcsr - power management control and status register this register provides stat us and control information for pm even ts in the pci express port of the dma engine device. device: 8 function: 0 offset: 54h version: intel 5000p chipset bit attr default description 31:24 ro 0h data: data data read out based on data select (dsel). refer to section 3.2.6 of pci pm specification for details. this is not implemented in the e power management capability for intel 5000p chipset mch and is hardwired to 0h. 23 ro 0h bpccen: bus power/clock control enable this field is hardwired to 0h. 22 ro 0h b2b3s: b2/b3 support this field is hardwired to 0h. 21:16 rv 0h reserved. 15 rwcst 0h pmests: pme status this pme status is a sticky bit. when set, the device generates a pme internally independent of the pmeen bit defined below. software clears this bit by writing a ?1?. as an integrated device within the root complex, the intel 5000p chipset mch will never set this bit, because it never generates a pme internally independent of the pmeen bit. 14:13 ro 0h dscl: data scale this 2-bit field indicates the scaling fa ctor to be used while interpreting the ?data_scale? field. 12:9 ro 0h dsel: data select this 4-bit field is used to select which data is to reported through the ?data? and the ?data scale? fields. 8rwst 0h pmeen: pme enable this field is a st icky bit and when set enables pm es generated internally to appear at the intel 631xesb/632xesb i/o controller hub through the ?assert(deassert)_pmegpe?message. this has no effect on the intel 5000p chipset mch since it does not generate pme events internally. 7:2 rv 0h reserved. 1:0 rw 0h ps: power state this 2-bit field is used to determine the current power state of the function and to set a new power state as well. 00: d0 01: d1 (reserved) 10: d2 (reserved) 11: d3_hot
register description 260 intel ? 5000x chipset memory controller hub (mch) datasheet 3.10.9 msicapid - message signal led interrupt capability id register 3.10.10 msinxptr - message sign alled interrupt next pointer register 3.10.11 msictrl - message signa lled interrupt control register device: 8 function: 0 offset: 58h version: intel 5000p chipset bit attr default description 7:0 ro 05h capid: msi capability id this code denotes the standard msi capability assigned by pci-sig device: 8 function: 0 offset: 59h version: intel 5000p chipset bit attr default description 7:0 ro 6ch nxtptr: msi next pointer : the dma engine device is implemented as a pci express device and this points to the pci express capability structure. device: 8 function: 0 offset: 5ah version: intel 5000p chipset bit attr default description 15:8 ro 0h reserved 7ro0 ad64cap: 64-bit address capable all processors used with the gnc mch do not support 64-bit addressing, hence this is hardwired to 0 6:4 rw 000 mmen: multiple message enable software initializes this to indicate th e number of allocate messages which is aligned to a power of two. when msi is enabled, the software will allocate at least one message to the device. see section 3.10.13 below for discussion on how the interrupts are handled. 3:1 ro 0h mmcap: multiple message capable the intel 5000p chipset mch dma engine supports only one interrupt message (power of two) for handling ? dma errors ?dma completions 0rw0 msien: msi enable this bit enables msi as the interrupt mo de of operation instead of the legacy interrupt mechanism. 0: disables msi from being generated. 1: enables msi messages to be ge nerated for dma related interrupts. an extract of the flowchart of the dma engine error handling is given in figure 3-7
intel ? 5000x chipset memory controller hub (mch) datasheet 261 register description figure 3-7. intel 5000p chipset dma error/ channel completion in terrupt handling flow intel? 5000p chipset sends deassert_intx message via dmi per intp when intrctrl.intp is reset (wired-or) will send only 1 msi for both dma interrupts and channel completions msien msicben output 1 1 msi 1 0 -- 0 x assert_intx intx disable x x 0 0 x 1 -- dma errors/completion interrupts n n y y pexcmd[x].intx disable == 1? (msictrl[x]. msien == 1) intel? 5000p chipset sends assert_intx message via dmi per intp msidr (pexctrl[x] msicben == 1)? y n
register description 262 intel ? 5000x chipset memory controller hub (mch) datasheet 3.10.12 msiar: message signalle d interrupt ad dress register 3.10.13 msidr: message signal led interrupt data register device: 8 function: 0 offset: 5ch version: intel 5000p chipset bit attr default description 31:20 ro feeh amsb: address msb this field specifies the 12 most signi ficant bits of the 32-bit msi address. 19:12 rw 0h adstid: address destination id this field is initialized by software fo r routing the interrupts to the appropriate destination. 11:4 rw 0h aexdstid: address extended destination id this field is not used by ia32 processor. 3rw 0 ardhint: address redirection hint 0: directed 1: redirectable 2rw 0 adm: address destination mode 0: physical 1: logical 1:0 rv 00 reserved. not used since the memory write is d-word aligned device: 8 function: 0 offset: 60h version: intel 5000p chipset bit attr default description 31:16 rv 0000h reserved. 15 rw 0h tm: trigger mode this field specifies the ty pe of trigger operation 0: edge 1: level 14 rw 0h lvl: level if tm is 0h, then this field is a don?t care. edge triggered messages are consistently treated as assert messages. for level triggered interrupts, this bit re flects the state of the interrupt input if tm is 1h, then: 0: deassert messages 1: assert messages 13:11 rw 0h these bits are don?t care in ioxapic interrupt message data field specification.
intel ? 5000x chipset memory controller hub (mch) datasheet 263 register description 3.10.14 pexcapid: pci expres s capability id register 3.10.15 pexnptr: pci expres s next pointer register 10:8 rw 0h dm: delivery mode 000: fixed 001: lowest priority 010: smi/hmi 011: reserved 100: nmi 101: init 110: reserved 111: extint 7:0 rw 0h iv: interrupt vector the interrupt vector as programmed by bios/software will be used by the intel 5000p chipset mch to provide context sensit ive interrupt information for different events such as dma errors, dma completions that require attention from the processor. see ta b l e 3 - 5 0 for iv handling for dma. table 3-50. iv vector table for dma errors and interrupts number of messages enabled by software (mmen) events iv[7:0] 1all (dma completions/errors) xxxxxxxx 1 notes: 1. the term ?xxxxxx? in the interrupt vector denotes that software/bios initializes them and the mch will not modify any of the ?x? bits since it handles only 1 message vector that is common to all events device: 8 function: 0 offset: 6ch version: intel 5000p chipset bit attr default description 7:0 ro 10h capid: pci express capability id this code denotes the standard pci express capability. device: 8 function: 0 offset: 6dh version: intel 5000p chipset bit attr default description 7:0 ro 00h nxtptr: pci express next pointer the pci express capability structure is the last capability in the linked list and set to null. device: 8 function: 0 offset: 60h version: intel 5000p chipset bit attr default description
register description 264 intel ? 5000x chipset memory controller hub (mch) datasheet 3.10.16 pexcaps - pci expres s capabilities register 3.10.17 pexdevcap - device capabilities register device: 8 function: 0 offset: 6eh version: intel 5000p chipset bit attr default description 15:14 rv 0h reserved 13:9 ro 0h imn: interrupt message number: this field indicates the interrupt me ssage number that is generated from the dma engine device. when there are more than one msi interrupt number, this register field is required to contain the offset between the base message data and the msi message that is generated when the status bits in the slot status register or root port status registers are set. 8ro0 slot_impl: slot implemented: dma engine is an integrated device and therefore a slot is never implemented. 7:4 ro 0000 dpt: device/port type: dma engine device represents a pci express endpoint. 3:0 ro 0001 vers: capability version: dma engine supports revision 1 of the pci express specification. device: 8 function: 0 offset: 70h version: intel 5000p chipset bit attr default description 31:28 rv 0h reserved 27:26 ro 00 cspls: captured slot power limit scale this field applies only to upstream ports. hardwired to 0h 25:18 ro 00h csplv: captured slot power limit value this field applies only to upstream ports. hardwired to 0h 17:15 rv 0h reserved 14 ro 0 pipd: power indicator present the dma engine is an integrated device and therefore, an power indicator does not exist. hardwired to 0h 13 ro 0 aipd: attention indicator present the dma engine is an integrated device an d therefore, an attention indicator does not exist. hardwired to 0h 12 ro 0 abpd: attention button present the dma engine is an integrated device an d therefore, an attention button does not exist. hardwired to 0h 11:9 ro 000 epl1al: endpoint l1 acceptable latency the dma engine device is not implemented on a physical pci express link and therefore, this value is irrelevant. hardwired to 0h 8:6 ro 000 epl0al: endpoint l0s acceptable latency the dma engine device is not implemented on a physical pci express link and therefore, this value is irrelevant. hardwired to 0h 5ro0 etfs: extended tag field supported the dma engine device does not support extended tags. hardwired to 0h 4:3 ro 00 pfs: phantom functions supported the dma engine device does not support phantom functions. hardwired to 0h
intel ? 5000x chipset memory controller hub (mch) datasheet 265 register description 3.10.18 pexdevctrl - de vice control register 2:0 ro 000 mplss: max_payload_size supported this field indicates the maximum payload si ze that the cb integrated device can support. 000: 128b max payload size others- reserved device: 8 function: 0 offset: 74h version: intel 5000p chipset bit attr default description 15 rv 0 reserved 14:12 ro 000 mrrs: max_read_request_size since the dma engine device does not issue read requests on a pci express interface, this field is irrelevant. hardwired to 0h 11 rw 1 ennosnp: enable no snoop 1: setting this bit enables the dma engine device to issue requests with the no snoop attribute. 0: clearing this bit behaves as a global disable when the corresponding capability is enabled for source/destination snoop control in the dma?s descriptor?s desc_control field. 10 ro 0 appme: auxiliary power pm enable the dma engine device does not implement auxiliary power so setting this bit has no effect. hardwired to 0h 9ro0 pfen: phantom functions enable the dma engine device does not implemen t phantom functions so setting this bit has no effect. hardwired to 0h 8ro0 etfen: extended tag field enable : the dma engine device does not implement ex tended tags so setting this bit has no effect. 7:5 rw 000 mps: max_payload_size : the dma engine device must not generate packets on any pci express interface which exceeds the length allowed with this field. 000: 128b max payload size 001: 256b max payload size 010: 512b max payload size 011: 1024b max payload size 100: 2048b max payload size 101: 4096b max payload size note: this field has no impact internally to intel 5000p chipset mch and the maximum payload size of the tlps that appear on the pci express port is governed by the pexdevctrl.mps for that port defined in table 3.8.11.4 4ro0 enrord: enable relaxed ordering no relaxed ordering is supported by in tel 5000p chipset mch. hardwired to 0h. device: 8 function: 0 offset: 70h version: intel 5000p chipset bit attr default description
register description 266 intel ? 5000x chipset memory controller hub (mch) datasheet 3.10.19 pexdevsts - pci expres s device status register 3ro0 urren: unsupported request reporting enable for an integrated dma engine device, th is bit is irrelevant. hardwired to 0h 2rw0 fere: fatal error reporting enable : this bit controls the reporting of fatal errors internal to the dma engine device 0: fatal error reporting is disabled 1: fatal error reporting is enabled 1rw0 nfere: non-fatal error reporting enable this bit controls the reporting of non fata l errors internal to the dma engine device in the pci express port. 0: non fatal error reporting is disabled 1: non fatal error reporting is enabled this has no effect on the intel 5000p chipset mch dma engine device as it does not report any non-fatal errors. 0rw0 cere: correctable error reporting enable this bit controls the reporting of correct able errors internal to the dma engine device in the pci express port. 0: correctable error reporting is disabled 1: correctable fatal error reporting is enabled this has no effect on the intel 5000p chipset mch dma engine device as it does not report any correctable errors. device: 8 function: 0 offset: 76h version: intel 5000p chipset bit attr default description 15:6 rv 0h reserved 5ro0 tp: transactions pending this bit indicates that the dma engine device has issued non-posted pci express transactions which have not yet completed. note the intel 5000p chipset mch dma en gine device does not issue any np transactions and hence this is hardwired to zero. 4ro0 apd: aux power detected the dma engine device does not support aux power. hardwired to 0h. 3ro0 urd: unsupported request detected this does not apply to dma engine in intel 5000 series chipset as there are no messages for the dma engine. hardwired to 0h 2rwc0 fed: fatal error detected this bit gets set if a fatal uncorrectable error is detected. errors are logged in this register regardless of whether error reporting is enabled or not in the device control register (see fere in section 3.10.18 ) 1: fatal errors detected 0: no fatal errors detected device: 8 function: 0 offset: 74h version: intel 5000p chipset bit attr default description
intel ? 5000x chipset memory controller hub (mch) datasheet 267 register description 3.11 pci express intel ibist registers 3.11.1 dioibstr: pci ex press intel ibist global start/status register this register contains the global start for all the ports in the intel 5000p chipset mch component simultaneously. one start bit is pl aced in the register for each port. intel ibist will start at approximately the same ti me on all ports written to with a 1 in the same write access. 1rwc0 nfed: non-fatal error detected this bit gets set if a non-fatal uncorrectable error is detected. errors are logged in this register regardless of whether error reporting is enabled or not in the device control register. (see nfere in section 3.10.18 ) 1: non fatal errors detected 0: no non-fatal errors detected 0rwc0 ced: correctable error detected this bit gets set if a correctable error is detected. errors are logged in this register regardless of whether error reporting is enabled or not in the device control register. (see cere in section 3.10.18 ) 1: correctable errors detected 0: no correctable errors detected device: 8 function: 0 offset: 76h version: intel 5000p chipset bit attr default description device: 0 function: 0 offset: 398h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7rw 0 start7: writing a 1 starts intel ibist on port 7. 6rw 0 start6: writing a 1 starts intel ibist on port 6. 5rw 0 start5: writing a 1 starts intel ibist on port 5. 4rw 0 start4: writing a 1 starts intel ibist on port 4. 3rw 0 start3: writing a 1 starts intel ibist on port 3. 2rw 0 start2: writing a 1 starts intel ibist on port 2. 1rv 0 reserved 0rw 0 start0: writing a 1 starts intel ibist on port 0.
register description 268 intel ? 5000x chipset memory controller hub (mch) datasheet 3.11.2 dio0ibstat: pci express in tel ibist completion status register 3.11.3 dio0iberr: pci express intel ibist error register device: 0 function: 0 offset: 394h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset bit attr default description 7ro 0 ibstat7: intel ibist status port 7 0: intel ibist either has not started the first time or it is still running. 1: intel ibist is done. this bit will be cl eared by hardware when the start bit is asserted. 6ro 0 ibstat6: intel ibist status port 6 0: intel ibist either has not started the first time or it is still running. 1: intel ibist is done. this bit will be cl eared by hardware when the start bit is asserted. 5ro 0 ibstat5: intel ibist status port 5 0: intel ibist either has not started the first time or it is still running. 1: intel ibist is done. this bit will be cl eared by hardware when the start bit is asserted. 4ro 0 ibstat4: intel ibist status port 4 0: intel ibist either has not started the first time or it is still running. 1: intel ibist is done. this bit will be cl eared by hardware when the start bit is asserted. 3ro 0 ibstat3: intel ibist status port 3 0: intel ibist either has not started the first time or it is still running. 1: intel ibist is done. this bit will be cl eared by hardware when the start bit is asserted. 2ro 0 ibstat2: intel ibist status port 2 0: intel ibist either has not started the first time or it is still running. 1: intel ibist is done. this bit will be cl eared by hardware when the start bit is asserted. 1rv 0 reserved. 0ro 0 ibstat0: intel ibist status port 0 0: intel ibist either has not started the first time or it is still running. 1: intel ibist is done. this bit will be cl eared by hardware when the start bit is asserted. device: 0 function: 0 offset: 395h bit attr default description 7rwc 0 p7errdet: error detected on port 7 6rwc 0 p6errdet: error detected on port 6 5rwc 0 p5errdet: error detected on port 5 4rwc 0 p4errdet: error detected on port 4 3rwc 0 p3errdet: error detected on port 3 2rwc 0 p2errdet: error detected on port 2 1rv 0 reserved 0rwc 0 p0errdet: error detected on port 0
intel ? 5000x chipset memory controller hub (mch) datasheet 269 register description 3.11.4 pex[7:2,0]ibct l: pex intel ibist control register this register contains the control bits and status information necessary to operate the fixed and open modes of the intel ibist logi c. the default settings allow the cmm logic to operate with link width of a pex port. only valid pci express control characters/ symbols are allowed for intel ibist testing. device: 3-2, 0 function: 0 offset: 380h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 380h version: intel 5000z chipset device: 7-4 function: 0 offset: 380h version: intel 5000p chipset bit attr default description 31 rw 0 symtypsel3: symbol[3] type select 1: selects symbol [3] as a control character 0: selects symbol [3] to a data character 30 rw 1 symtypsel2: symbol[2] type select 1: selects symbol [2] as a control character 0: selects symbol [2] to a data character 29 rw 0 symtypsel1: symbol[1] type select 1: selects symbol [1] as a control character 0: selects symbol [1] to a data character 28 rw 1 symtypsel0: symbol[0] type select 1: selects symbol [0] as a control character 0: selects symbol [0] to a data character 27:23 rv 0 reserved 22:14 ro 0h errval: error value this is the raw 9-bit error value captured on the lane that asserted the error detected bit (errdet) or the global er ror status bit if this register is implemented. the value must be extrac ted in the datapath before the 10b/8b decoder in order to examine its contents for debugging potential link errors. 13:9 ro 0h errlnnum: error lane number this field indicates which lane report ed the error that was detected when errdet was asserted. note: when the number of lanes reporting exceeds 32, this field will show an aliased error lane number and cannot be used to indicate the errant lane. larger lane indications will require an extended register to display accurate information. 8rwcst 0 errdet: error detected a mis-compare between the transmitted symbol and the symb ol received on link indicates an error condition occurred. refer to error value, error symbol pointer and error symbol type bit fields for further information about fault locations. this bit is cleared by writin g a logic ?1? and it remains asserted through reset (sticky). 0: no error detected 1: error detected note: the error signal that causes this bit to be set should be made available externally to the intel ibist logic. it is implementation specific as to how this is accomplished. the purpose is for symb ol (bit) error rate testing. it is assumed that this signal is either sent to a performance counter or an external pin for signal assertion accumu lation. there is not any error counting resources available in this spec.
register description 270 intel ? 5000x chipset memory controller hub (mch) datasheet 3.11.5 pex[7:2,0]ibsymbuf: pe x intel ibist symbol buffer this register contains the character symbols that are transmitted on the link. only valid pci express control characters/symbols are allowed for intel ibist testing. 7rw 0 supskp: suppress skips 0: skips are still inserted in the intel ib ist data stream duri ng intel ibist test operations. 1: skip insertion is suppressed 6:4 rw 000 dsyminjlnum: delay symbol injection lane number this selects the lane number to inject the delay symbol pattern. all 8 values could be valid depending on the setting of the ibextctl.lnmoduen bit field. this is true regardless of whether this intel ibist engine is instantiated for a x4 or a x8 port. 3rw 1 autoseqen: automatic sequencing enable of delay symbol 0: disable delay symbol auto-sequence. intel ibist does not automatically sequence the delay symbol across the width of the link. 1: enable delay symb ol auto-sequencing. 2rv 0 reserved 1rw 0 initdisp: initial disparity this bit sets the disparity of the firs t intel ibist data pattern symbol. the default is negative meaning that the first symbol transmitted by tx will have a negative disparity regardless of what the running disparity is. this allows a deterministic pattern set to be transm itted on the link for every intel ibist run. if intel ibist causes a discontinuous disparity error in the receiver this error can be ignored in the reporting regist er. it will not affect the operation of the intel ibist since it is outside of its domain. higher levels of software management must be aware that side effects from running intel ibist could cause other errors and should they be ignored. 0: disparity starts as negative 1: disparity starts as positive 0rw 0 ibstr: intel ibist start this bit is or?ed with the global start bit. 0: stop intel ibist 1: start intel ibist device: 3-2, 0 function: 0 offset: 380h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 380h version: intel 5000z chipset device: 7-4 function: 0 offset: 380h version: intel 5000p chipset bit attr default description
intel ? 5000x chipset memory controller hub (mch) datasheet 271 register description 3.11.6 pex[7:2,0]ibex tctl: pex intel ibist extended control register this register extends the functionality of the intel ibist with pattern loop counting, skip character injection, and symbol manageme nt. a bit is provided to ignore the count value and loop continuously for port testing. only valid pci express control characters/ symbols are allowed for intel ibist testing. device: 3-2, 0 function: 0 offset: 384h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 384h version: intel 5000z chipset device: 7-4 function: 0 offset: 384h version: intel 5000p chipset bit attr default description 31:24 rw 4ah charsym3: character symbol [3] this character is symbol [3] of the four-s ymbol pattern buffer. the default value is the 8-bit encoding for d10.2. 23:16 rw bch charsym2: character symbol [2] this character is symbol [3] of the four-s ymbol pattern buffer. the default value is the 8-bit encoding for k28.5. 15:8 rw b5h charsym1: character symbol [1] this character is symbol [3] of the four-s ymbol pattern buffer. the default value is the 8-bit encoding for d21.5. 7:0 rw bch charsym0: character symbol [0] this character is symbol [3] of the four-s ymbol pattern buffer. the default value is the 8-bit encoding for k28.5.
register description 272 intel ? 5000x chipset memory controller hub (mch) datasheet device: 3-2, 0 function: 0 offset: 388h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 388h version: intel 5000z chipset device: 7-4 function: 0 offset: 388h version: intel 5000p chipset bit attr default description 31:29 rv 0h reserved 28 rw 0 frcent: forced entry: setting this bit forces entry into master intel ibist loopback state when the start bit is asserted. no ts1s are sent when en abled. the intel ibist is granted direct control of the transmitted path regardless of which state the ltssm is in. the intel ibist state machine sends the contents of the pattern buffer until the stop condition is reached. the receiver isn?t expected to perform any error checking and must ignore input symbols. note: for intel 5000p chipset mch the user must reset the component to stop this function. the receiver sets the done condition and the receiver is disabled with this function. 0: execute normally 1: force to loopback state as a ?master? condition. 27:26 rw 01 lnmoduen: lane modulo enable for delay symbol injection 00: no symbols sent on lanes 01: delay symbols sent on modulo 4 group of lanes across the width of the port. 10: delay symbols sent on modulo 8 group of lanes across the width of the port. 11: reserved 25 rw 0 disstop: disable stop on error 0: enable stop on error 1: disable stop on error. the intel ibist engine continues to run in its current mode in the presence of an error. if an error occurs overwrite the error status collected from a previous error event. 24 rw 0 lpcon: loop continuously 0: use loop counter. test terminates at the end of the global count. 1: loop symbols continuously. 23:12 rw 000h skpcntint: skip count interval this register indicates when a skip order sequence is sent on the transmitter. upon reaching this count the transmitter sends an sos then clears the skip counter and counting resumes until the next match on the skip count interval. 000: no skip ordered sets are sent on tx. nnn: the number of 8 symbol sets transmitted before a skip ordered set is sent. 11:0 rw 07fh loopcntlim: loop count limit this register indicates the number of time s the data symbol buffer is looped as a set of 8 symbol times. if loopcon is set then this count limit is ignored. 00: no symbols are sent from symbol bu ffer unless loopcon is set. if loopcon is cleared and this value is 000h then the transmitter immediately exits out of loopback state by sending eios without sending a pattern buffer payload. 01-fff: 1 to 4095 sets of symbols from the symbol buffer. one set of symbols is defined as either two copies of the contents of the buffer or the modified delayed symbol set.
intel ? 5000x chipset memory controller hub (mch) datasheet 273 register description 3.11.7 pex[7:2,0]ibdlysym: pe x intel ibist delay symbol this register stores the value of the delay symbol used in lane inversion cross-talk testing. only valid pci express control char acters/symbols are allowed for intel ibist testing. 3.11.8 pex[7:2,0]ibloopcnt: pe x intel ibist loop counter this register stores the current value of the loop counter. device: 3-2, 0 function: 0 offset: 38ch version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 38ch version: intel 5000z chipset device: 7-4 function: 0 offset: 38ch version: intel 5000p chipset bit attr default description 15:9 rv 0h reserved 8:0 rw 1bch dlysym: delay symbol this is the 9-bit delay symbol value used (default is k28.5). device: 3-2, 0 function: 0 offset: 38eh version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 38eh version: intel 5000z chipset device: 7-4 function: 0 offset: 38eh version: intel 5000p chipset bit attr default description 15:12 rv 0h reserved 11:0 ro 000h loopcntval: loop count value once the intel ibist is engaged, loop counts are incremented when a set of 8 symbols has been received. if an error occurs, this register reflects the loop count value of the errant rx lane. if there is no error then this register reads 00h. note: since each receiver is not deskewed with respect to the intel ibist pattern generator we cannot have a coherent loop count value with n number of receivers and only one loop counter. it would re quire additional logic to select which receiver indicates the count.
register description 274 intel ? 5000x chipset memory controller hub (mch) datasheet 3.11.9 pex[7:2,0]iblns[3:0]: pe x intel ibist lane status this register contains the control bits and status information necessary to perate the fixed and open modes of the intel ibist logi c. the default settings allow the cmm logic to operate with link width of a pex port. only valid pci express control characters/ symbols are allowed for intel ibist testing. device: 3-2, 0 function: 0 offset: 393h, 392h, 391h, 390h version: intel 5000p chipset, intel 5000v chipset, intel 5000z chipset device: 4-5 function: 0 offset: 393h, 392h, 391h, 390h version: intel 5000z chipset device: 4-7 function: 0 offset: 393h, 392h, 391h, 390h version: intel 5000p chipset bit attr default description 7ro 0 errptrtyp: error symbol pointer type this bit indicates whether or not the errant symbol pointer was a delay symbol set. if an intel ibist engine is impl emented with the misr compare method then this field is reserved. 0: errant symbol pointer was a data symbol set 1: errant symbol pointer was a delay symbol set 6:4 ro 0h errptr: error symbol pointer this value indicates which symbol of the 8 possible symbols sent on the lane, as a set of characters, failed. the value co rresponds to position of the set of 8 symbols. if an intel ibist engine is implemented with the misr compare method then this field is reserved. 3rwc 0 ibloopstat: intel ibist loopback state status: this bit is set when the rx received a ts1 with the loopback bit set. write a logic ?1? to clear. 0: intel ibist did not receive a ts1 with loopback bit set. 1: intel ibist received a ts1 with loopback bit set. 2rv 0 reserved. 1rwcst 0 errlnstat: error lane status error assertion for this lane. writing a logic ?1? will clear this bit. this bit is sticky. 0: no error on this lane 1: error has occurred on this lane 0rw 1 lnstren: lane start enable when the lane is disabled, no electrical transmissions may occur on the tx driver and the receiver?s (rx) intel ibist error reporting is suppressed. this allows the pattern generator and receiver checking logic to function normally if required for design simplicity. but it fo rces a quite tx lane for adjacent lane testing. 0: this lane is disabled from intel ib ist testing, no tx transmissions and rx error reporting is suppressed. 1: lane enabled. allows the port start bi t to begin intel ibist symbol operations on this lane.
intel ? 5000x chipset memory controller hub (mch) datasheet 275 register description 3.11.10 dio[1:0]squelch_cnt: pcie cluster squelch count device: 4, 0 function: 0 offset: 396h bit attr default description 15:12 rv 1h reserved 11 rwst 1h dis_rx_l1l0s_idle : disable automatic shutoff of receivers during l1.idle/ l0s.idle power states 1: disable automatic shut off of receivers during l1 or l0s idle power state entry. (default). 0: enables rx shut off. this bit when cl ear forces the hardware to shut off the receiver side in bnb during the l0s/l1 power states. note: this bit is functional in mch steppings b3 and newer. refer to erratum 19 (501621). 10 rwst 0h dis_lane_lane_deskew: disable lane to lane deskew 1: lane to lane deskew is disabled. should be set before intel ibist is started and cleared after intel ibist is stopped 0: normal link operation. i.e lane to lane deskew is enabled (default) 9:0 rv 164h reserved
register description 276 intel ? 5000x chipset memory controller hub (mch) datasheet
intel ? 5000x chipset memory controller hub (mch) datasheet 277 system address map 4 system address map the intel 5000x chipset mch supports 36 bits of memory address space. internally intel 5000p chipset carries 40 bits of address into various memory controller components. the processors designed for inte l 5000p chipset, support only 36 bits of memory addressing and 16 bits of addressable i/o space. however internally the mch supports 40 bits and several of the mch memory configuration registers require 40 bit address programming. there is a legacy (compatibility) memory ad dress space under the 1-mb region that is divided into regions that can be individually controlled with programmable attributes (for example, disable, read/write, write only , or read only). attribute programming is described in chapter 3. the intel 5000x ch ipset mch supports several fixed address ranges in addition to the compatibility range. these are: ? compatibility area below 1mb ? interrupt delivery region ? system region in 32mb just below 4gb there are several relocatable regions such as the memory mapped i/o region.these regions are controlled by various programmable registers covered in chapter 3. this chapter focuses on how the memory space is partitioned and the uses of the separate memory regions. in the following sections, it is assumed that all of the compatibility memory ranges reside on the esi/pci express/pci interfac es. vga address ranges are mapped to pci express address space as well. in the abse nce of more specific references, cycle descriptions referencing pci should be interpreted as the esi/pci interface. the intel 5000x chipset mch memory map includes a number of programmable ranges. all of these ranges must be un ique and non-overlapping as shown in figure 4-1 . there are no hardware interlocks to prevent problems in the case of overlapping ranges. accesses to overlapped ra nges may produce indeterminate results. for example, setting hecbase to all zero s will overlap the mmcfg region and the compatibility region resulting in unpredictable results.
system address map 278 intel ? 5000x chipset memory controller hub (mch) datasheet 4.1 system memory address ranges the intel 5000x chipset mch platform supports 36 bits (64 gb) of physical memory or maximum of 40-bit system address with up to 64 gb or physical memory support. other address spaces supported by the intel 5000p chipset are: ? 36-bit local address supported over the fb-dimm channels for physical memory space. ? 32 and 64 bit address bit formats su pported for pci express interfaces. the chipset treats accesses to various address ranges in different ways. there are fixed ranges like the compatibility region below 1 mb, and variable ranges like the memory mapped i/o range. the locations of these ra nges in the memory map are illustrated in figure 4-2 . 4.1.1 32/64-bit addressing for inbound and outbound writes and read s, the intel 5000p chipset mch supports 64-bit address format. if an outbound tran saction?s address is a 32-bit address, the intel 5000p chipset mch will issue the transact ion with a 32-bit addressing format on pci express. only when the address requires more than 32 bits will the intel 5000p chipset mch initiate transactions with 64-bit address format. it is the responsibility of the software to ensure that the relevant bi ts are programmed for 64-bits based on the os limits. (for example, 40-bit s for intel 5000p chipset mch). figure 4-1. system memory address map pci-e/pci-x/pci memory address range main memory address range top of the physical dram memory 0 64 gb graphics memory agp address range graphics (agp) aperture independently programmable non- overlapping memory windows
intel ? 5000x chipset memory controller hub (mch) datasheet 279 system address map figure 4-2. detailed memory system address map system memory high extended memory low/medium extended memory dos compatibility area 1mb 0 640 kb 768 kb 896 kb 960 kb expansion card bios c and d segments ( 128 kb ) vga memory std . pci / isa video memory (128 kb) dos region ( 640 kb ) lower bios area ( 64 kb ; 16 kb x 4) upper bios area ( 64 kb ) high mmio 64 gb 0 1mb 4gb 0000 0000 h 0009 ffffh 000 a 0000 h 000 b ffffh 000 c 0000 h 000 d ffffh 000 e 0000 h 000 e ffffh 000 f 0000 fh 000 f ffffh 0010 0000 h ffff ffffh system memory 1 0000 0000 h f ffff ffffh firmware interrupt / smm chipset cb _ bar amb _ mmio low mmio relocation mmcfg relocation extended smram space fe 70 0000 h hecbase tolm ffff ffffh fe 00 0000 h fe 00 7 fffh ambase fec 0 0000 h ffc 0 0000 h ff 00 0000 h 12 mb esmmtop - tseg _ sz 16 mb 4mb 1mb 256 mb esmmtop physical maximum memory is ~ 64 gb . physical maximum memory is the 1. maximum address validated by intel? 5000 p : 64 gb - 256 mb
system address map 280 intel ? 5000x chipset memory controller hub (mch) datasheet 4.2 compatibility area this is the range from 0 - 1 mb (0 0000h to f ffffh). requests to the compatibility area are directed to main memory, the comp atibility bus (esi), or the vga device. any physical dram addresses that would be addressed by requests in this region that are mapped to the compatibility bu s (esi) and are not recovered. dram that has a physical address between 0- 1 mb must not be recovered or relocated or reflected. this range must always be ava ilable to the os as dram, even if at times addresses in this range are sent to the compatibility bus or vga or other non-dram areas. addresses below 1 m that are mapped to memory are accessible by the processors and by any i/o bus. the address range below 1 m is divided into five address regions. these regions are: ? 0 - 640 kb ms-dos area. ? 640 ? 768 kb video buffer area. ? 768 ? 896 kb in 16-kb sections (total of eight sections) - expansion card bios, segments c and d. ? 896 - 960 kb in 16-kb sections (total of four sections) - lower extended system bios, segment e. ? 960 kb?1 mb memory (bios area) - upper system bios, segment f. there are fifteen memory segments in the co mpatibility area. thirteen of the memory ranges can be enabled or disabled independently for both read and write cycles. 4.2.1 ms-dos area (0 0000h?9 ffffh) the ms-dos area is 640 kb in size and is mapped to main memory controlled by the mch. table 4-1. memory segments and their attributes memory segments attributes comments 000000h?09ffffh fixed: mapped to main dram 0 to 640 kb ? dos region 0a0000h?0bffffh mapped to esi, x16 graphi cs port video buffer (physical dram configurable as smm space) 0c0000h?0c3fffh we re add-on bios 0c4000h?0c7fffh we re add-on bios 0c8000h?0cbfffh we re add-on bios 0cc000h?0cffffh we re add-on bios 0d0000h?0d3fffh we re add-on bios 0d4000h?0d7fffh we re add-on bios 0d8000h?0dbfffh we re add-on bios 0dc000h?0dffffh we re add-on bios 0e0000h?0e3fffh we re bios extension 0e4000h?0e7fffh we re bios extension 0e8000h?0ebfffh we re bios extension 0ec000h?0effffh we re bios extension 0f0000h?0fffffh we re bios area
intel ? 5000x chipset memory controller hub (mch) datasheet 281 system address map 4.2.2 legacy vga rang es (a 0000h?b ffffh) the 128 kb video graphics adapter memory range (a 0000h to b ffffh) can be mapped to the vga device which may be on any pci express or esi port, or optionally it can be mapped to main memory (it must be mapped to smm space). mapping of this region is controlled by the vga steering bits. at power on this space is mapped to the esi port. priority for vga mapping is constant in that the mch consistently decodes internally mapped devices first. the mch positively decodes internally mapped devices. this region can be redirected by bios to poin t to any bus which has a vga card. if the vgaen bit is set in one of the intel 5000p chipset mch.bctrl configuration registers associated with the pci express port, then transactions in this space are sent to that pci express port. the vgaen bit can only be set in one an d only one of the intel 5000p chipset mch.bctrl registers. if any vgaen bits are se t, all the isaen bits must be set. if the vgaen bit of a pci express port x in the intel 5000p chipset mch is set and bctrl[x].vga16bdecode is set to zero, then isaen bits of all peer pci express ports with valid i/o range (pcicmd.ioae = 1, iolimit >= iobase) in the mch must be set by software. otherwise, it is a programmin g error due to the resulting routing conflict. if the vgaen bit of a pci express port x in the mch is set, and bctrl[x].vga16bdecode is set to one, and if there is another pci express port y (x != y) with valid i/o range including the lowe st 4k i/o addresses (pcicmd[y].ioae = 1, iolimit[y] >= iobase[y] = 0000h), bctrl[y].isaen bit must be set to one by software. otherwise, it is a programming error. this region is non-cacheable. compatible smram address range (a 0000h?b ffffh) the legacy vga range may also be used for mapping smm space. the smm range (128 kb) can overlay the vga range in the a and b segments. if the smm range overlaps an enabled vga range then the state of the s mmem# signal determines where accesses to the smm range are directed. smmem# is a special fsb message bit that uses multiplexed address bit fsbxa[7] #. smmem# is valid during the second half of the fsb request phase clock. (the clock in which fsbxads# is driven asserted). smmem# asserted directs the accesses to the memory and smmem# deasserted directs the access to the pci express bus where vga has been mapped. when compatible smm space is enabled, s mm-mode processor accesses to this range are routed to physical system dram at this address. non-smm-mode processor accesses to this range are considered to be to the video buffer area as described above. graphics port and esi originated cycles to enabled smm space are not allowed and are considered to be to the video buffer area. monochrome adapter (mda) range (b 0000h?b 7fffh) the intel 5000x chipset does not support this range.
system address map 282 intel ? 5000x chipset memory controller hub (mch) datasheet 4.2.3 expansion card bi os area (c 0000h?d ffffh) this 128-kb isa expansion card bios covers segments c and d. this region is further divided into eight, 16-kb segments. each segment can be assigned one of four read/ write states: read only, write only, read/wri te, or disabled. typically, these blocks are mapped through the mch and are subtractively decoded to isa space. memory that is disabled is not remapped. read and write transactions may be directed to different destinations with in the range c 0000h to d ffffh. historically, these blocks were used to shadow isa device bios code. for the intel 5000p chipset, these regions are used to provide address space to pci devices requiring memory space below 1 mb. the range is divided into 8 sub- ranges. these ranges are defined by intel 5000p chipset mch.pam registers. there is a pam register for each sub-range that defines the routing of reads and writes. the power-on default for these segments is mapped read/write to the esi port (intel? 631xesb/632xesb i/o controller hub). software should not set cacheable memory attributes for any of these ranges, unless both reads and writes are mapped to main memory. chipset functionality is not guaranteed if this region is cached in any mode other than both reads and writes being mapped to main memory. for locks to this region, the intel 5000p chipset will complete, but does not guarantee the atomicity of locked access to this ra nge when writes and reads are mapped to separate destinations. if inbound accesses are expected, the c and d segments must be programmed to send accesses to dram. 4.2.4 lower system bios area (e 0000h?e ffffh) this 64-kb area, from e 0000h to e ffffh, is divided into four, 16-kb segments. each segment can be assigned independent read and write attributes through the intel 5000p chipset mch.pam registers. this area can be mapped either the esi port (intel 631xesb/632xesb i/o controller hub) or to main memory. historically this area was used for bios rom. memory segments that are disabled are not remapped elsewhere. the power-on default for these segments is to map them to the esi port (intel 631xesb/632xesb i/o controller hub). softwa re should not set cacheable memory attributes for any of these ranges unless bo th read and write transactions are mapped to main memory. chipset functionality is no t guaranteed if this region is cached. for locks to this region, the intel 5000p chipset will complete them, but does not guarantee the atomicity of locked access to this range when writes and reads are mapped to separate destinations. if inbound transactions are expected, the e segment must be programmed to send these transactions to dram. table 4-2. pam settings pam [5:4]/1:0] write destination read destination result 00 esi esi mapped to esi port 01 esi main memory memory write protect 10 main memory esi in-line shadowed 11 main memory main memory mapped to main memory
intel ? 5000x chipset memory controller hub (mch) datasheet 283 system address map 4.2.5 upper system bios area (f 0000h?f ffffh) this area is a single, 64-kb segment, fr om e 0000h - f ffffh. this segment can be assigned read and write attributes through the intel 5000p chipset mch.pam registers. the power-on default is set to read/write disabled with tr ansactions forwarded to the esi port (intel 631xesb/632xesb i/o controlle r hub). by manipulating the read/write attributes, the mch can ?shadow? bios into the main system memory. when disabled, this segment is not remapped. for locks to this region, the intel 5000p chipset will complete them, but does not guarantee the atomicity of locked access to this range when writes and reads are mapped to separate destinations. if inbound transactions are expected, the f segment must be programmed to send these transactions to dram. 4.3 system memory area the low/medium memory regions range from 1mb to 4 gb. it consists of sub-regions for firmware, processor memory mapped func tions, and intel 5000p chipset specific registers. the extended memory area covers from 10 0000h (1 mb) to ffff ffffh (4 gb-1) address range and it is divide d into the following regions: ? main system memory from 1 mb to the top of memory; 4-gb system memory. ? pci memory space from the top of memory to 4 gb with two specific ranges: ? apic configuration space from fec0 0000h (4 gb?20 mb) to fecf ffffh and fee0 0000h to feef ffffh ? high bios area is from 16mb to 4 gb - 1 main system dram address range (00 10 0000h to top of system memory) the address range from 1 mb to the top of system memory is mapped to system memory address range controlled by the mc h. the top of main memory (tolm) is limited to 4-gb dram. all accesses to addre sses within this range will be forwarded by the mch to the system memory. the mch provides a maximum system memo ry address decode space of 4 gb. the mch does not remap apic memory space. the mch does not limit system memory address space in hardware. 4.3.1 system memory see section 4.3.9 . 4.3.2 15 mb - 16 mb window (isa hole) the intel 5000p chipset does not support th e legacy isa hole between addresses f0 0000h - ff ffffh. all transactions to this address range are treated as system memory. 4.3.3 extended smram space (tseg) smm space allows system management software to partition a region in main memory to be used by system management software. this region is protected for access by software other than system management software. when the smm range is enabled, memory in this range is not exposed to th e operating system. the intel 5000p chipset
system address map 284 intel ? 5000x chipset memory controller hub (mch) datasheet allows accesses to this range only when the smmem# signal on the processor bus is asserted with the request. if smmem# is deasserted, accesses to the smm range are master aborted. if smmem# is asserted th e access is routed to main memory. intel 5000p chipset uses the smm enable and range registers to determine where to route the access. extended smram space is different than the smm space defined with in the vga address space, a 0000h - b ffffh. this region is controlled by the intel 5000p chipset registers intel 5000p chipset mch.exsmrc.tseg_sz and intel 5000p chipset mch.exsmrtop.esmmtop. the tseg smm space starts at esmmtop - tseg_sz and ends at esmmtop. this region may be 512 kb, 1 mb, 2 mb, or 4 mb in size, depending on the tseg_sz field. esmmtop is relocatable to accommodate software that wishes to configure the tseg smm space before mmio space is known. the esmmtop will default to the same default value as top of low me mory (tolm), defined by the tolm register. intel 5000p chipset will not support a lock ed access that crosses an smm boundary. firmware should not create data structures that span this boundary. smm main memory is protected from inbound accesses. in order to make cacheable smm possible, the chipset must accept ewb?s and must absorb iwb data regardless of the condit ion of the smmem# pin. the intel 5000x chipset mch will not set the error bit exsm ramc.e_smerr in this case. because of this, care must be used when attempting to cache smm space. the chipset/platform cannot protect against processors who attempt to illegally access smm space that is modified in another processor?s cache. any software that creates such a condition (for example, by corrupting the page table) will jeopardize the protective properties of smm. 4.3.4 memory mapped config uration (mmcfg) region there is one relocatable memory mapped configuration region in the intel 5000x chipset mch. the processor bus address define s the particular configuration register to be accessed. this configuration mechanism is atomic. the memory mapped configuration region is compatible with the pci express enhanced configuration mechanism. the mmcfg region is a 256 mb window that maps to pci express registers on both the intel 5000p chipset and the south bridge. the location of this mmcfg window is defined by the intel 5000p chipset mch.hecbase register. the hecbase register could also be accessed through a fixed location. the default value of intel 5000p ch ipset mch.hecbase maps this region such that there will be no wasted memory that is lost behind it. the default value for the pci express registers is the same as the default value of tolm. if this range is moved, the following recommendations will enable reclaiming the memory that is lost to mmcfg accesses. 1. mmcfg range is mapped to a legal loca tion within the rang e between tolm and 4gb. since ranges must not overlap other legal ranges, it is safest to put this range between tolm and the lowest real mmio ra nge. (the current default is in these ranges) or 2. put the region above 4gb low/medium memory limit and not overlapping above 4 gb mmio space. bios/software must ensure there are no outstanding configuration accesses or memory accesses to the old and new mmcfg range addresses when relocating this range.
intel ? 5000x chipset memory controller hub (mch) datasheet 285 system address map note: an smm program can address up to 4 gb of memory. smm is similar to read-address mode in that there are no privileges or ad dress mapping. the intel 5000p chipset mch allows the relocation of hecbase abov e 4 gb. however, smm code cannot access extended configuration space if hecbase is relocated above 4 gb. this is a cpu limitation. page size extension (pse) is su pported in smm but page address extension (pae) support in smm is currently not in intel ? xeon ? processors. refer to the ia-32 intel ? architecture software developer?s manual, vol. 3, sect. 13.1. for more information on the memory mapped configuration mechanism described here, please see the configuration map and access chapter. 4.3.5 low memory mapped i/o (mmio) this is the first of two intel 5000x chipset memory mapped i/o ranges. the low memory mapped i/o range is defined to be between top of low memory, (tolm) and fe00 0000h. this low mmio region is furthe r subdivided between the pci express and esi ports. the following table shows the registers used to define the mmio ranges for each pci express/esi device. these registers are compatible with pci express and the pci to pci bridge specifications. note that all subranges must be contained in the low memory mapped i/o range (between tolm an d fe00 0000). in other words, the lowest base address must be above tolm and the highest limit register must be below fe00_0000. subranges must also not overlap each other. notes: 1. this table assumes intel 5000p chip set mch.pmlu and intel 5000p chipse t mch.pmbu are 0?s. otherwise, the prefetchable memory space w ill be located in high mmio space. 2. mch does not need base/limit for intel 631xesb/632xes b i/o controller hub because subtractive decoding will send the accesses to the intel 631xesb/632xesb i/o controller hub. this is ok for software also, since the intel 631xesb/632xesb i/o controller hub is considered part of the same bus as the mch. the intel 5000x chipset mch will decode addre sses in this range and route them to the appropriate esi or pci express port. if the address is in the low mmio range, but is not contained in any of the pci express base and limit ranges, it will be routed to the esi. if the intel 5000p chipset mch.pmlu and in tel 5000p chipset mch.pmbu registers are greater than 0, then the corresponding prefetchable region will be located in the high mmio range instead. table 4-3. low memory mapped i/o 1 i/o port mch base mch limit esi n/a 2 n/a 2 pex2 memory mbase2 mlimit2 pex2 prefetchable me mory pmbase2 pmlimit2 pex3 memory mbase3 mlimit3 pex3 prefetchable me mory pmbase3 pmlimit3 pex4 memory mbase4 mlimit4 pex4 prefetchable me mory pmbase4 pmlimit4 pex5 memory mbase5 mlimit5 pex5 prefetchable me mory pmbase5 pmlimit5 pex6 memory mbase6 mlimit6 pex6 prefetchable me mory pmbase6 pmlimit6 pex7 memory mbase7 mlimit7 pex7 prefetchable me mory pmbase7 pmlimit7
system address map 286 intel ? 5000x chipset memory controller hub (mch) datasheet 4.3.6 chipset specific range the address range fe00 0000h - febf ffffh region is reserved for chipset specific functions. fe00 0000h - fe00 8000h: this range (with size of 128 kb for four fb-dimm channels; 16 advanced memory buffer (amb) per channel, 2 kb per amb), is used for accessing amb registers. these registers can only be accessed through memory mapped register access mechanism as mmio. notice that they are not accessible through cf8/cfc or mmcfg which are used for pci/pci express configuration space registers. this range could be relocated by programming ambase register. the ambase register could also be accessed through a fixed location. fe60 0000h - fe6f ffffh: this range is used for fixed memory mapped intel 5000p chipset registers. they are accessible only from the processor bus. these registers are fixed since they are needed early during the boot process. the registers include: ? four scratch pad registers ? four sticky scratch pad registers ? four boot flag registers ? hecbase register for mmcfg ? ambase register for amb memory mapped registers these registers are described in the intel 5000x chipset mch configuration register, chapter 3, ?register description.? the intel 5000x chipset mch will master abort requests to the remainder of this region un less they map into one of the relocatable regions such as mmcfg. the mechanism for this range can be the same as it is for the memory mapped configuration accesses. 4.3.7 interrupt/smm region this 4 mb range is used for processor spec ific applications. this region lies between fec0 0000h and feff ffffh and is split into four 1 mb segments. figure 4-3. interrupt /smm region fe 00 0000 h fec 8 ffffh fdea 0000 h feef ffffh feff ffffh fec 9 0000 h fed 2 0000 h fed 3 ffffh fdeb ffffh fee 0 0000 h r oute to intel? 631 xe s b / 632 xesb i / o controller hub ( mmt = fed 0 000 h - fed 0 3 fffh ) i/ o apic reserved route to intel? 631 xesb / 632 xesb i / o controller hub high smm route to intel? 631 xesb / 632 xesb i / o controller hub interrupt r oute to intel? 631 xe s b / 632 xesb i / o controller hub
intel ? 5000x chipset memory controller hub (mch) datasheet 287 system address map this region is used to support various proc essor and system functions. these functions include i/o apic control range which is used to communicate with i/o apic controllers located on intel 6700pxh 64 bit pci hub and intel 631xesb/632xesb i/o controller hub devices. the high smm range is enabled under register control. transactions directed to this range are redirected to physical memory located in the compatible (legacy) smm space; 0a 0000h - 0b ffffh. the interrupt range is used to deliver interrupts. memory read or write tran sactions from the processor are illegal. 4.3.7.1 i/o apic controller range this address range fec0 0000h to fec8 ffff is used to communicate with the ioapic controllers in the intel ? 6700pxh 64 bit pci hub or intel 631xesb/632xesb i/o controller hub devices. the apic ranges are hard coded. reads and writes to each ioapic region should be sent to the appropriate esi or pci express port as indicated below. for hot-plug i/o apic support, it is recomme nded that software use the standard mmio range to communicate with the intel 6700pxh 64 bit pci hub. to accomplish this, the intel 6700pxh 64 bit pci hub.mbar and/or intel 6700pxh 64 bit pci hub.xapic_base_address_reg must be pr ogrammed within the pci express device mmio region. inbound accesses to this memory range should also be routed to the i/o apic controllers. this could happen if software configures msi devices to send msis to an i/ o apic controller. 4.3.7.2 high smm range if high smm space is enabled by exsmrc.h _smrame, then requests to the address range from feda 0000h to fedb ffffh will be aliased down to the physical address of a 0000h to b ffffh. the highsmm space allo ws cacheable accesses to the compatible (legacy) smm space. in this range, the ch ipset will accept ewbs (bwls) regardless of the smmem# pin. also, if there is an implic it write back (hitm with data), the chipset will update memory with the new data (regardl ess of the smmem# pin). note that if the highsmm space is enabled, the aliased s mm space of 0a 0000h - 0b ffffh will be disabled. note: in order to make cacheable smm possible, the chipset must accept ewbs (bwls) and must absorb iwb (hitm) data regardle ss of the condition of the smmem# pin. because of this, care must be used when attempting to cache s mm space. the chipset/ platform cannot protect against processors who attempt to illegally access smm space table 4-4. i/o apic address mapping ioapic0 (esi) fec0 0000h to fec7 ffffh ioapic1 (pex2) fec8 0000h to fec8 0fffh ioapic2 (pex3) fec8 1000h to fec8 1fffh ioapic3 (pex4) fec8 2000h to fec8 2fffh ioapic4 (pex5) fec8 3000h to fec8 3fffh ioapic5 (pex6) fec8 4000h to fec8 4fffh ioapic6 (pex7) fec8 5000h to fec8 5fffh reserved (intel? 631xesb/632xesb i/o controller hub for master abort) fec0 6000h to fec8 ffffh
system address map 288 intel ? 5000x chipset memory controller hub (mch) datasheet that is modified in another processor?s cache. any software that creates such a condition (for example, by corrupting the pa ge table) will jeopardize the protective properties of smm. 4.3.7.3 interrupt range requests to the address range fee0 0000h to feef ffffh are used to deliver interrupts. memory reads or write transactions to this range are illegal from the processor. the processor issues interrupt transactions to this range. inbound interrupt requests from the pci express devices in th e form of memory writes are converted by the mch to processor bus interrupt requests. 4.3.7.4 reserved ranges the intel 5000x chipset mch will master abort requests to the addresses in the interrupt/reserved range (fec0 0000h - feff ffffh) which are not specified. this can be done by sending the request to the compatibility bus (esi) to be master aborted. 4.3.7.5 firmware range the intel 5000x chipset platform allocates 16 mb of firmware space from ff00 0000h to ffff ffffh. requests in this range are di rected to the compatibility bus. the intel 631xesb/632xesb i/o controller hub will route these to its fwh interface. this range is accessible from any processor bus. 4.3.8 high extended memory this is the range above 4 gb. the range from 4 gb to intel 5000p chipset mch.mir[2].limit is mapped to system memo ry. there can also be a memory mapped i/o region that is located at the top of the address space. (just below 1 tb). 4.3.8.1 system memory see section 4.3.9 4.3.8.2 high mmio the high memory mapped i/o region is locate d above the top of memory as defined by intel 5000p chipset mch.mir[2].limit. these intel 5000p chipset mch.pmbu and intel 5000p chipset mch.pmlu registers in each pci express configuration device determine whether there is memory mapped i/o space ab ove the top of memory. if an access is above mir[2].limit and it falls within the intel 5000p chipset mch.pmbu+pmbase and intel 5000p chipset mch.pmlu+pmlimit range, it should be routed to the appropriate pci express port. for accesses above mir[2].l imit (and above 4 gb) that are not in a high mmio region, they sh ould be master aborted. 4.3.8.3 extended memory the range of memory just below 4 gb from tolm to 4 gb (low mmio, chipset, interrupt/smm/lt) does not map to memory. if the dram memory, behind the tolm to 4 gb range, is not relocated, it will be unused. the intel 5000x chipset mch uses mir[2].limit to indicate the top of usable memory. note that esmmtop cannot be greater than tolm.
intel ? 5000x chipset memory controller hub (mch) datasheet 289 system address map 4.3.9 main memory region 4.3.9.1 application of coherency protocol the intel 5000x chipset mch applies the coherency protocol to all accesses to main memory. application of the coherency protocol includes snooping the other processor bus. two exceptions to this rule are the expans ion card bios area, 0c 0000h - 0f ffffh and the legacy smm, 0a 0000h - 0b ffffh, range. the expansion card bios area 0c 0000h - 0f ffffh may not necessarily route both reads and writes to memory, the legacy smm range, 0a 0000h - 0b ffffh, ma y target non-memory when not in smm mode. the coherency protocol is not applied to these two exceptions. 4.3.9.2 routing memory requests when a request appears on the processor bus, esi port, or pci express link, and it does not fall in any of the previously ment ioned regions, it is compared against the mir.limit registers in the mch. the intel 5000p chipset mch.mir.limit registers will decode an access into a specific interleaving range. within the interl eaving range, the intel 5000p chipset mch.mir.limit register indicates which fb-dimm memory branch the address is associated with. in the event that a mirroring event is occurring, memory writes are associated with both fb-dimm branches. 4.4 memory address disposition the following section presents a summary of address dispositions for the intel 5000x chipset mch. 4.4.1 registers used for address routing ta b l e 4 - 5 is a summary of the registers used to control memory address disposition. these registers are described in detail in section 3 . table 4-5. intel 5000x chipset mch memory mapping registers (sheet 1 of 2) name function mir[2:0] memory interleaving regist ers (fb-dimm branch interleaving) amir[2:0] scratch pad register for software to use related to memory interleaving. for example, software can write mmio gap adju sted limits here to aid in subsequent memory ras operations. pam[6:0] defines attributes for ranges in the c and d segments. supports shadowing by routing reads and writes to memory of i/o. smramc smm control exsmrc, exsmramc extended smm control exsmrtop top of extended smm memory bctrl contains vgaen and isaen for each pci express. tolm top of low memory. everything betwee n tolm and 4 gb will not be sent to memory. hecbase base of the memory ma pped configuration region th at maps to all pci express registers. mbase (dev 2-7) base address for memory mapped i/o to pci express ports 2 - 7.
system address map 290 intel ? 5000x chipset memory controller hub (mch) datasheet 4.4.2 address disposition for processor the following tables define the address disposition for the intel 5000x chipset mch. ta b l e 4 - 6 defines the disposition of outbound requests enteri ng the intel 5000x chipset mch on the processor bus. ta b l e 4 - 1 0 defines the disposition of inbound requests entering the intel 5000x chipset mch on an i/o bus. for address dispositions of pci express/esi devices, please refer to the respective product specifications for the intel 6700pxh 64 bit pci hub or inte l 631xesb/632xesb i/o controller hub. mlimit (dev 2-7) limit addr ess for memory mapped i/o to pci express ports 2 - 7. pmbase (dev 2-7) base address fo r memory mapped i/o to prefetchable memory of pci express ports 2-7 1 pmlimit (dev 2-7) limit address fo r memory mapped i/o to prefetchable memory of pci express ports 2-7. pmbu (dev 2-7) prefetchable memory base (uppe r 32 bits) - upper address bits to the base address of prefetchable memory space. if the prefetchable me mory is below 4 gb, this register will be set to all 0?s. pmlu (dev 2-7) prefetchable memory limit (upper 32 bits) - upper address bits to the limit address of prefetchable memory space. if the pr efetchable memory is below 4 gb, this register will be set to all 0?s. pcicmd (dev 2-7) mse (memory space enable) bit enables the memory and prefetchable ranges. notes: 1. the chipset treats memory and prefetchable memory the same. these are just considered 2 apertures to the pci express port. table 4-5. intel 5000x chipset mch memory mapping registers (sheet 2 of 2) name function table 4-6. address disposition for processor (sheet 1 of 2) address range conditions intel 5000p chipset behavior dos 0 to 09ffffh coherent request to main memory. route to main memory according to intel 5000p chipset mch.mir registers. apply coherence protocol. smm/vga 0a0000h to 0bffffh see ta b l e 4 - 8 and ta b l e 4 - 9 . c and d bios segments 0c0000h to 0dffffh and pam=11 non-coherent request to main memory. rout to appropriate fb-dimm device according to intel 5000p chipset mch.mir registers. write to 0c0000h to 0dffffh and pam=10 read to 0c0000h to 0dffffh and pam=01 read to 0c0000h to 0dffffh and pam=10 issue request to esi. write to 0c0000h to 0dffffh and pam=01 0c0000h to 0dffffh and pam=00
intel ? 5000x chipset memory controller hub (mch) datasheet 291 system address map e and f bios segments 0e0000h to 0fffffh and pam=11 non-coherent request to main memory. rout to appropriate fb-dimm device according to intel 5000p chipset mch.mir registers. write to 0e0000h to 0fffffh and pam=10 read to 0e0000h to 0fffffh and pam=01 read to 0e0000h to 0fffffh and pam=10 issue request to esi. write to 0e0000h to 0fffffh and pam=01 0e0000h to 0fffffh and pam=00 low/medium memory 10_0000 <= addr < tolm coherent request to main memory. route to main memory according to intel 5000p chipset mch.mir registers. coherence protocol is applied. note: the extended smram sp ace is within this range. extended smram space esmmtop-tseg_sz <= addr < esmmtop see ta b l e 4 - 8 and ta b l e 4 - 9 . low mmio tolm <= addr < fe00_0000 and falls into a legal base/limit range request to pci express based on registers. tolm <= addr < fe00_0000 and not in a legal base/limit range send to esi to be master aborted. pci express mmcfg hecbase <= addr < hecbase+256mb convert to a configuration access and route according to the configuration access disposition. intel 5000x chipset specific fe00_0000h to febf_ffffh and valid intel 5000p chipset memory mapped register address plus amb targeted addresses issue configuration access to memory mapped register inside intel 5000p chipset or to the fb-dimm based on the context. fe00_0000h to febf_ffffh and (not a valid intel 5000p chipset memory mapped register address or not a valid amb targeted address) send to esi to be master aborted. i/o apic registers fec0_0000 to fec8_ffffh non-coherent request to pci express or esi based on ta b l e 4 - 4 . intel? 631xesb/ 632xesb i/o controller hub / intel? 631xesb/ 632xesb i/o controller hub timers fec9_0000h to fed1_ffff issue request to esi. high smm feda_0000h to fedb_ffff see ta b l e 4 - 8 and ta b l e 4 - 9 . interrupt interrupt transaction to fee0_0000h to feef_ffffh (not really memory space) route to appropriate fsb(s). memory transaction to fee0_0000h to feef_ffffh send to esi to be master aborted. firmware ff00_0000h to ffff_ffffh issue request to esi. high memory 1_0000_0000 to mir[2].limit (max ff_ffff_ffff) coherent request to main memory. route to main memory according to intel 5000p chipset mch.mir registers. coherence protocol is applied. high mmio pmbu+pmbase <= addr <= pmlu+pmlimit route request to appropriate pci express port. all others all others (subtractive decoding) issue request to esi. table 4-6. address disposition for processor (sheet 2 of 2) address range conditions intel 5000p chipset behavior
system address map 292 intel ? 5000x chipset memory controller hub (mch) datasheet 4.4.2.1 access to smm space (processor only) accesses to smm space are restricted to processors, inbound transactions are prohibited. inbound transactions to enabled smm space are not allowed and intel 5000x chipset mch will set intel 5 000p chipset mch.exsmramc.e_smerr bit. the following table defines when a smm ra nge is enabled. all the enable bits: g_smrame, h_smram_en, and tseg_en are located in the intel 5000p chipset mch.exsmrc register. the processor bus has a smmem# signal that qualifies the request asserted as having access to a system management memory. th e smm register defines smm space that may fall in one of three ranges: legacy smram, extended smram space (tseg), or high smram space (h_smm). ta b l e 4 - 8 defines the access control of smm memory regions from processors. table 4-7. enabled smm ranges global enable g_smrame high smm enable h_smram_en tseg enable tseg_en legacy smm enabled? high smm enabled? extended smram space (tseg) enabled? 0xxnonono 100yesnono 101yesnoyes 110noyesno 111noyesyes table 4-8. smm memory region access control from processor g_smrame d_lck d_cls d_open smmem# code access to smm memory 1 notes: 1. brlc data access to smm memory 2 2. data access transaction other than brlc 0 3 3. for access to tseg region (address range between esmmtop - tseg_sz and esmm top), intel 5000p chipset mch will route to identical system memory by definition (as tseg is not enabled). x x x x no no 10x00 no no 10001 yes yes 1001x yes yes 10101 yesno (legacy smm) yes (h_smm, tseg) 1 4 4. it is a programming error if d_cls and d_open are both set to 1, intel 5000p chipset mch?s behavior is undefined. intel 5000p chipset mch could master abort smm access. x 1 1 x illegal settings illegal settings 110x0 no no 11100 no no 110x1 yes yes 11101 yesno (legacy smm) yes (h_smm, tseg)
intel ? 5000x chipset memory controller hub (mch) datasheet 293 system address map the intel 5000p chipset prevents illegal processor access to smm memory. this is accomplished by routing memory requests from processors as a function of transaction request address, code or data access, th e smmem# signal accompanying request and the settings of the intel 5000p chip set mch.smramc, intel 5000p chipset mch.exsmrc, and intel 5000p chipset mch.bctrl registers. ta b l e 4 - 9 defines intel 5000p chipset mch?s routing for each case. ille gal accesses are either routed to the esi bus where they are master aborted or are blocked with error flagging. smmem# only affects intel 5000p chipset behavior if it fa lls in an enabled smm space. note that the d_cls only applies to the legacy (a_000 0-b_ffff) smm region. the bold values indicate the reason smm access was granted or denied. note: if a spurious inbound access targets the en abled smm range (viz., legacy, high smm memory and extended smram (t-segment)), then it will be master-aborted. the exsmramc.e_smerr register field (invalid smram) is set for accesses to the high smm memory and extended smram (t-segment)). refer to ta b l e 4 - 1 0 . 4.4.3 inbound transactions in general, inbound i/o transactions ar e decoded and dispositioned similarly to processor transactions. the key differenc es are in smm space, memory mapped configuration space, and interrupts. inboun d transaction targeting at itself will be master aborted. note that inbound accesses to the smm region must be handled in such a way that fsb snooping and associated potential implicit writ ebacks are avoided. this is necessary to prevent compromising smm data by returning real content to the i/o subsystem. note also that dma engine is treated as an i/o device, thus accesses initiated by the dma engine are considered as inbound accesses. table 4-9. decoding processor re quests to smm and vga spaces smm region transaction address range smm memory address range smm access control 1 notes: 1. smm memory access control, see table 4-8 . g_smrame h_smrame t_en ewb/iwb routing legacy vga/smm 2 2. software must not cache this region. a_0000h to b_ffffh a_0000h to b_ffffh x 0xxxto the vga-enabled port (in bctrl); otherwise, esi 3 3. one and only one bctrl can set the vgaen; otherwise, send to esi. yes 1 1 x x no 1xxx yes 10xxto smm memory extended smram (tseg) esmmtop -tseg_sz to esmmtop esmmtop -tseg_sz to esmmtop x 0xxxto identical system memory by definition x1x0x yes 1x1xto smm memory no 1 x 1 1 no 1 x 1 0 block access: master abort set exsmramc.e_smerr high smm feda_0000h to fedb_ffffh a_0000h to b_ffffh x 0xxxto esi (where access will be master aborted) x10xx yes 11xxto smm memory 4 4. notice this range is mapped into legacy smm range (a_0000h to b_ffffh). no 1 1 x 1 no 1 1 x 0 block access: master abort set exsmramc.e_smerr
system address map 294 intel ? 5000x chipset memory controller hub (mch) datasheet for all table entries where an access is forwarded to esi to be master aborted, if an access comes from esi, the intel 5000x chipset mchesi may master abort a transaction without forwarding it back to the esi. table 4-10. address disposition for inbound transactions (sheet 1 of 2) address range conditions intel 5000p chipset behavior dos 0 to 09ffffh coherent request to main memory. route to main memory according to intel 5000p chipset mch.mir registers. apply coherence protocol. smm/vga 0a0000h to 0bffffh, and vgaen=0 send to esi to be master aborted. set exsmramc.e_smerr 0a0000h to 0bffffh and vgaen=1 non-coherent read/write request to the decoded pci express or to esi based on bctrl 1 c, d, e, and f bios segments 0c0000h to 0fffffh and pam=11 2 non-coherent request to main memory. (coherency does not need to be guaranteed. coherency protocol can be followed if it simplifies implementation.) route to appropriate fb-dimm according to intel 5000p chipset mch.mir registers. low/medium memory 10_0000 <= addr < esmmtop - tseg_sz coherent request to main memory. route to main memory according to intel 5000p chipset mch.mir registers. apply coherence protocol. extended smram space esmmtop -tseg_sz <= addr < esmmtop send to system memory if g_smrame = 0 or (g_smrame = 1 and t_en = 0); otherwise send to esi to be master aborted. set exsmramc.e_smerr bit low mmio tolm <= addr < fe00_0000 and falls into a legal base/limit range request to pci express based on registers. tolm <= addr < fe00_0000 and not in a legal base/limit range send to esi to be master aborted. pci express mmcfg hecbase <= addr < hecbase+256mb inbound mmcfg access is not allowed and will be aborted. intel 5000x chipset specific fe00_0000h to febf_ffffh and valid intel 5000p chipset memory mapped register address inbound mmcfg access is not allowed and will be aborted. fe00_0000h to febf_ffffh and not a valid intel 5000p chipset memory mapped register address send to esi to be master aborted. i/o apic registers fec0_0000 to fec8_ffffh non-coherent request to pci express or esi based on ta b l e 4 - 4 intel 631xesb/ 632xesb i/o controller hub / intel 631xesb/ 632xesb i/o controller hub timers fec9_0000h to fed1_ffff issue request to esi. high smm feda_0000h to fedb_ffff send to esi to be master aborted. set exsmramc.e_smerr bit interrupt inbound write to fee0_0000h - feef_ffffh route to appropriate fsb(s). see interrupt chapter for details on interrupt routing. memory transaction (other than write) to fee0_0000h - feef_ffffh send to esi to be master aborted. firmware ff00_0000h to ffff_ffffh master abort
intel ? 5000x chipset memory controller hub (mch) datasheet 295 system address map 4.5 i/o address map the i/o address map is separate from the memory map and is primarily used to support legacy code/drivers that use i/o mapped accesses rather than memory mapped i/o accesses. except for the special addresses listed in section 4.5.1 , i/o accesses are decoded by range and sent to the appropriate esi/pci express port, which will route the i/o access to the appropriate device. 4.5.1 special i/o addresses there are two classes of i/o addresses that are specifically decoded by the intel 5000x chipset mch: ? i/o addresses used for vga controllers. ? i/o addresses used for the pci configurat ion space enable (cse) protocol. the i/o addresses 0cf8h and 0cfch are specifically decoded as part of the cse protocol. historically, the 64 k i/o space actually wa s 64 k+3 bytes. for the extra three bytes, a#[16] is asserted on fsb. the product name decodes only a#[15:3] when the request encoding indicates an i/o cycle. th erefore first three byte i/o accesses with a#[16] asserted are decoded as if they were accesses to the first three bytes starting from i/o addresses 0 (wrap-around the 64 kb line). a[16] is not forwarded by intel 5000x chipset mch. at power-on, all i/o accesses are mapped to the esi. 4.5.2 outbound i/o access the intel 5000p chipset mch chipset allows i/o addresses to be mapped to resources supported on the i/o buses underneath the intel 5000p chipset. this i/o space is partitioned into 16 4 kb segments. each of pci express port can have from 1 to 16 consecutive segments mapped to it by programming its iobase and iolim registers. each pci express port must be assigned contiguous segments. the lowest segment, from 0 to 0fffh, should be programmed to send to the esi for compatibility. high memory 1_0000_0000 to mir[2].limit (max ff_ffff_ffff) coherent request to main memory. route to main memory according to intel 5000p chipset mch.mir registers. apply coherence protocol. high mmio pmbu+pmbase <= addr <= pmlu+pmlimit route request to appropriate pci express port all others all others (subtractive decoding) issue request to esi. notes: 1. one and only one bctrl can set the vgaen; otherwise, send to esi for master abort. 2. other combinations of pam?s are not allowed if inbound access es to this region can occur. just like cayuse, chipset functionality is not guaranteed. table 4-10. address disposition for inbound transactions (sheet 2 of 2) address range conditions intel 5000p chipset behavior
system address map 296 intel ? 5000x chipset memory controller hub (mch) datasheet 4.5.2.1 outbound i/o accesses routing the intel 5000p chipset applies these routing rules in the following order : (a[2:0] for the following is not physically present on the processor bus, but are calculated from be[7:0]). 1. i/o addresses used for vga controllers on pci express: if pcicmd[y].ioae and bctr l[y].vgaen of pci express port y are set to 1 and bctrl[y].vga16bdecode = 0 , then i/o accesses with the following vga addresses will be forwarded to pci express port y: a[9:0] (a[15:10] are ignored for this decode since bctrl[y].vga16bdecode is set to 0) = 3b0h - 3bbh, 3c0h - 3dfh if every addressed byte is within these two ranges. for example, a two byte read starting at x3bbh includes x3bb -x 3bch. (x can be any hex number since a[15:10] are ignored) since the second byte with a[9:0] = 3bch is not within these ranges, the access is not routed to port y. if pcicmd[y].ioae and bctrl[y].vgaen of port y are set to 1 and bctrl[y].vga16bdecode = 1 , then i/o accesses with the following vga addresses will be forwarded to pci express port y: a[ 15 :0] = 0 3b0h - 0 3bbh, 0 3c0h - 0 3dfh if every addressed byte is within these two ranges. for example, a four byte i/o read starting at f3b0h includes f3b0 - f3b3h are not within these ranges, the access is not routed to port y. note that software should program pexcmds and bctrls to ensure that at most only one port is allowed to forward these accesses with vga addresses. it is a programming error if more than one port are programmed to forward accesses with vga addresses. 2. configuration accesses: if a request is a dw accesses to 0cf8h (see cfgadr register) or 1-4 b accesses to 0cfch (see cfgdat register) with configuration space enabled (see cfge bit, bit 31, of cfgadr register), the request is considered a figure 4-4. system i/o address space 0000 ffff 1000 2000 segment 0 segment 15 f000 +3 bytes 1_0003 (decoded as 0_000x) segment 1 segment f
intel ? 5000x chipset memory controller hub (mch) datasheet 297 system address map configuration access. configuration accesses are routed based on the bus and device numbers as programmed by software. 3. isa aliases: if the pcicmd[y].ioae an d bctrl[y].isaen are set to 1 for a pci express port y and the i/o address falls within (iobase[y], iolimit[y]) and if the addresses are x100-x3ffh, x500-x7ffh, x900-xbff, and xd00-xfffh (x can be any hex number) will result in the access being sent out to the esi (intel 631xesb/ 632xesb i/o controller hub). this is the top 768 b in each 1 kb block. 4. i/o defined by iobase/iolimit: if pcicmd [y].ioae is set for a given pci express port and the i/o address falls in this range: (iobase[y] <= address <= iolimit[y]) for that port, then the access will be routed to the pci express port y. 5. otherwise, the i/o read/write is sent to esi (intel 631xesb/632xesb i/o controller hub). 4.6 configuration space all chipset registers are represented in the memory address map. in addition, some registers are also mapped as pci registers in pci configuration space.these adhere to the pci local bus specification , revision 2.2 . the memory mapped configuration space is described in section 4.3.4 . individual register maps are in the registers chapte rs of the intel 5000x chipset mch component specifications. if a cpu issues a zero length configurat ion cycle accessing the intel 5000p chipset mch?s internal configuration space register s or the cb_bar/amb memory mapped area, then it will be completed on the fsb ?in order? with no data. 4.7 i/o address map the i/o address map is separate from the memory map and is primarily used to support legacy code/drivers that use i/o mapped accesses rather than memory mapped i/o accesses. except for the special addresses listed in ?special i/o addresses? on page 246, i/o accesses are decoded by range and sent to the appropriate esi/pci express port, which will route the i/o access to the appropriate device. 4.7.1 special i/o addresses there are two classes of i/o addresses that are specifically decoded by the intel 5000x chipset mch: ? i/o addresses used for vga controllers. ? i/o addresses used for the pci configurat ion space enable (cse) protocol. the i/o addresses 0cf8h and 0cfch are specifically decoded as part of the cse protocol. historically, the 64 k i/o space actually was 64 k+3 bytes. for the extra 3 bytes, a#[16] is asserted. the intel 5000p chipse t decodes only a#[15:3] when the request encoding indicates an i/o cycle. therefore accesses with a#[16] asserted are decoded as if they were accesses to address 0 and are forwarded to the compatibility bus. at power-on, all i/o accesses are mapped to the compatibility bus.
system address map 298 intel ? 5000x chipset memory controller hub (mch) datasheet 4.7.2 outbound i/o access the intel 5000x chipset allows i/o addresse s to be mapped to resources supported on the i/o buses underneath the mch. this i/o space is partitioned into 16 4 kb segments. each of the i/o buses can have from 1 to 15 segments mapped to it by programming its iobase and iolim registers. each pci bus must be assigned contiguous segments. the lowest segment, from 0 to 0-+fffh, is sent to the esi. 4.8 configuration space all chipset registers are represented in th e memory address map. in addition, some registers are also mapped as pci registers in pci configuration space.these adhere to the pci local bus specification , revision 2.2. figure 4-5. system i/o address space segment 0 compatability bus only segment 1 segment f segment 2 through segment e +3 bytes (decoded as 0 000xh) 0000h 1000h 2000h f000h ffffh 1 0003h
intel ? 5000x chipset memory controller hub (mch) datasheet 299 functional description 5 functional description this chapter describes each of the mch inte rfaces and functional units including the dual independent bus (dib), processor fron tside bus (fsb) interface, the pci express ports, system memory controller, power management, and clocking. 5.1 processor front side buses the mch supports two dual-core intel ? xeon ? 5000 sequence processors on a 65 nanometer process in a 771-land, fc-lga4 package. dual-core intel xeon 5000 sequence is a fourth generation 32-bit intel ? xeon processor supporting intel ? extended memory 64 technology (intel ? em64t) based on intel netburst ? microarchitecture. the mch supports 1066/1333 mhz fsb which is a quad-pumped bus running off a 266/333 mhz system clock, and a point to po int dib processor system bus interface. each processor fsb supports peak address generation rates of 533 million addresses/ second. both fsb data buses are quad pumped 64-bits which allows peak bandwidths of 8.5 gb/s (1066 mt/s) and 10.5 gb/s (1 333 mt/s). the mch supports 36-bit host addressing, decoding up to 64 gb of the processor?s memory address space. host- initiated i/o cycles are decoded to agp/ pci, pci express, esi interface or mch configuration space. host-initiated memo ry cycles are decoded to agp/pci, pci express, esi or system memory. 5.1.1 fsb overview the mch is the only priority agent for two point to point, independent, processor front side buses (fsb). these two buses are refe rred to as dual independent buses (dib). the mch maintains coherency across thes e two buses. the mch may complete deferrable transactions with either defer-replies or in-order responses. intel 5000x chipset contains an internal snoop-filter to remove unnecessary snoops on the remote fsb, and to be able to complete transactions in-order without deferring for transactions that do not need to have a remote snoop. data transactions on the fsbs are optimized to support 64 byte cache lines. each processor fsb contains a 36 bit address bus, a 64 bit data bus, and associated control signals. the fsb utilizes a split-transaction, deferred reply protocol. the fsb uses source-synchronous transfer of addr ess and data to improve performance. the fsb address bus is double pumped (2x) with ads being sourced every other clock. the address bus generates a maximum bandwidth of 133 million addresses/second (ma/s). the fsb data bus is quad pumped (4x) an d supports peak bandwidths of 8.5 gb/s (1066 mt/s) and 10.5 gb/s (1333 mt/s). parity protection is applied to the data bus. this yields a combined bandwidth of 17 gb/s (1066 mt/s) and 21 gb/s (1333 mt/s) for both fsbs. interrupts are also delivered via the fsb.
functional description 300 intel ? 5000x chipset memory controller hub (mch) datasheet 5.1.2 fsb dynamic bus inversion the mch supports dynamic bus inversion (dbi) when driving and when receiving data from the processor. dbi limits the number of data signals that are driven to a low voltage on each quad pumped data phas e. this decreases the worst-case power consumption of the mch. the dbi[3:0]# signal s indicate if the corresponding 16 bits of data are inverted on the bus for each quad pumped data phase. when the processor or the mch drives data, each 16-bit segment is analyzed. if more than 8 of the 16 signals would normally be driven low on the bus, the corresponding dbi# signal will be asserted and the data w ill be inverted prior to being driven on the bus. when the processor or the mch receives data, it monitors dbi[3:0]# to determine if the corresponding data segment should be inverted. 5.1.3 fsb interrupt overview the dual-core intel xeon 5000 sequence processor supports fsb interrupt delivery. the legacy apic serial bus interrupt deliv ery mechanism is not supported. interrupt- related messages are encoded on the fsb as ?interrupt message transactions.? in the intel 5000x chipset platform, fsb interrupts may originate from the processor on the system bus, or from a downstream device on the enterprise south bridge interface (esi) or agp. in the later case, the mch drives the interrupt message transaction onto the system bus. in the intel 5000x chipset the intel 631xesb/632xesb i/o controller hub contains ioxapics, and its interrupts are generated as upstream esi memory writes. furthermore, pci 2.3 defines message signaled interrupts (msi) that are also in the form of memory writes. a pci 2.3 device may generate an interrupt as an msi cycle on its pci bus instead of asserting a hardware signal to the ioxapic. the msi may be directed to the ioxapic which in turn ge nerates an interrupt as an upstream esi memory write. alternatively, th e msi may be directed directly to the fsb. the target of an msi is dependent on the address of the interrupt memory write. the mch forwards inbound esi and agp/pci (pci semantic only ) memory writes to address 0feex_xxxxh to the fsb as interrupt message transactions. 5.1.3.1 upstream interrupt messages the mch accepts message-based interrupts fr om pci (pci semantics only) or esi and forwards them to the fsb as interrupt me ssage transactions. the interrupt messages presented to the mch are in the form of me mory writes to address 0feex xxxxh. at the esi or pci interface, the memory write in terrupt message is treated like any other memory write; it is either posted into the inbound data buffer (if space is available) or retried (if data buffer space is not immediately available). once posted, the memory write from pci or esi to address 0feex xxxxh is decoded as a cycle that needs to be propagated by the mch to the fsb as an interrupt message transaction. table 5-1. dbi[3:0]# / data bit correspondence dbi[3:0]# data bits dbi0# d[15:0]# dbi1# d[31:16]# dbi2# d[47:32]# dbi3# d[63:48]#
intel ? 5000x chipset memory controller hub (mch) datasheet 301 functional description 5.2 snoop filter the snoop filter (sf) offers significant performance enhancements on several workstation benchmarks by eliminating traffic on the snooped frontside bus of the processor being snooped. by removing snoops from the snooped bus, the full bandwidth is available for other transactions. supporting concurrent snoops effectively reduces performance degradation attribut able to multiple snoop stalls. see figure 5-1, ?snoop filter? on page 302 . the sf is composed of two affinity groups each containing 8k sets of x16-way associative entries. the overall sf size is 16 mb in size. each affinity group supports a pseudo-lru replacement algorithm. lookups are done on a full 32-way per set for hit/ miss checks. as shown in figure 5-1 the snoop filter is organized in two halves referred to as the affinity group 1 and affinity group 0 or the odd and even snoop filters respectively. as shown in figure 5-1 affinity group 1 is associated with processor 1 and affinity group 0 is associated with processor 0. under normal conditions a snoop is competed with a 1 snoop stall penalty. when the processors request simultaneous snoops the first snoop is completed with a one snoop stall penalty, the second snoop requires a 2 snoop stall penalty. for the purposes of simultaneous sf access arbitration, processor 0 is given priority over processor 1. thus simultaneous snoops are resolved with a 1 snoop stall penalty for processor 0 and a 2 snoop stall penalty for processor 2.
functional description 302 intel ? 5000x chipset memory controller hub (mch) datasheet the sf stores the tags and coherency state information for all cache lines in the system. the sf is used to determine if a cache line associated with an address is cached in the system and where. the cohere ncy protocol engine (ce) accesses the sf to look-up an entry, update/add an entry, or invalidate an entry in the snoop filter. the sf has the following features: figure 5-1. snoop filter fsb0 fsb1 fsb0 fsb1 fsb0 fsb1 proc 0 proc 1 proc 0 proc 1 cdm cdm mem io mem io coherency engine coherency engine 8k sets 16 - way 16 - way affinity group 0 affinity group 1
intel ? 5000x chipset memory controller hub (mch) datasheet 303 functional description ? snoop filter tracks total of 16 mb of cachelines (2 18 l2 lines). ? 8k sets organized as one interleave via a 2 x 16 affinity set-associativity array. there are a total of 8k x 2 x 16 = 256k lines (2 18 ). ? 2 x 16 affinity set-associativity will allocate/evict entries within the 16-way corresponding to the assigned affinity grou p if the sf look up is a miss. each sf look up will be based on 32-way (2x16 ways) look up. ? the array size of the snoop filter ram is equivalent to 1mb plus 0.03mb of pseudo- least-recently-used (plru) ram. tag array size = 8192 sets * 4 bytes/set/group * (2 groups* 16 ways) = 1048576b =1mb plru array size = 8192 sets * 15 bits/set/group * (2 groups) = 30720b = ~0.03mb ? the snoop filter is operated at 2x of in tel 5000x chipset mch core frequency, i.e. 533mhz to provide 267 mluu/s (where a look-up-update operation is a read followed by a write operation to the tag and plru arrays). ? the maximum lookup and update bandwidth of the snoop filter is equal to the max request bandwidth from both fsb?s. the lookup and update bandwidth from i/o coherent transactions have to share the bandwidth with both fsbs per request weighted-round-robin arbitration. ? the sf lookup latency is four sf-clo cks or two intel 5000x chipset mch core clocks to support single snoop stall in id le condition (single request issued from either bus). if both bus are making re quests simultaneously, the snoop-filter will always select bus 0 first. in such scenario, bus 0 request will have one snoop-stall and bus 1 request will have two snoop-stalls. ? pseudo-least-recently-used (plru) repl acement algorithm, with updates on lookups, and invalidates. ? tag entries supporting a 40-bit internal physical address space. the mch external address space is 36 bits. ? stores coherency state (em) and bus[1:0] for each valid cache line in the system. the tracking algorithm utilizes conservative tracking (super-set tracking). the processor can silently down grade a line state from e to s/i or s to i without any action appearing on the fsb. therefore, a line appearing in the sf as e states may actually missed in the corresponding proc essor caches. conversely a sf s-line will never be found in e/m state in a processors l2 cache, or a sf miss will never be found in m/e/s state in a processors l2 cache. the following is the summery of the snoop-filter state definitions: ? coherency state: the cache line is in e/m state if the bit is set; else, the line is in share state ? if bus[1:0]=00, the entry is invalid. ? if bus[1:0]=01, the fsb0 processor(s) has ownership of the line. ? if bus[1:0]=10, the fsb1 processor(s) has ownership of the line. ? if bus[1:0]=11, both buses have owne rship and the line must be shared by both fsb processors (em must be 0). ? em||bus[1:0] =111 is a reserved definition. ? ecc coverage, with correction of single bi t errors, detection of double bit errors (sec-ded). ? plru array does not need ecc protection. bit failure will result in selecting different entry than the plru selection and may affect the performance. there are no correctness issue.
functional description 304 intel ? 5000x chipset memory controller hub (mch) datasheet ? snoop-filter fast array initialization and/or self test through configuration register access. 5.2.1 snoop filter address bit mapping the sf supports a 40-bit physical address. ta b l e 5 - 1 shows the partitioning of the address for indexing into the sf array. 5.2.2 operations and interfaces the following table shows the snoop-filter look up qualifier for coherent transaction issued from processors, i.e. ads# assertion driven from processors. table 5-1, ?snoop filter? on page 302 shows the organization of each snoop filter entry, and interpretation of the contents. table 5-1. snoop filter physical address partitioning tag (21b) set (13b) byte offset (6b) a[39:19] a[18:6] a[5:0] table 5-2. fsb transaction encodi ng qualification for sf look up sf look up transactions from fsb: the following reqa[2:0] encoding with ads# assertion from processor qualification. request names reqa[2:0] reqa[2] reqa[1] reqa[0] bril/bil 010 brlc 100 brld/blr 110 bwl 101 bwil/blw 111 table 5-3. snoop filter entry bits value [31] redundant bit. [30:24 ] ecc check bits
intel ? 5000x chipset memory controller hub (mch) datasheet 305 functional description the snoop filter supports the following key op erations during normal operation. due to timing constraints, these lookup and update commands have been removed for the sf configuration access. ? sf_lookup with plru status update by mru operation on a lookup, the sf uses the tag and set portion of the input address to determine if the entry is in the sf. the sf asserts a hit if there is a match and provides the contents, and way information for the matched entry. if the lookup is a miss, the sf provides the contents of the victim entry, set and way information of the victim. the plru vector is updated according to a most-recently-used (mru) algorithm. the sf indicates if a single or double bit error was detected. single-bit errors are corrected (but the array is not updated). hit/miss calculation is performed after the ecc logic. all fsb request to memory will use this command for sf lookup. ? sf_lookup with no plru status update operation the sf uses the tag and set portion of the input address to determine if the entry is in the sf. the sf asserts a hit if there is a match and provides the contents, and way information for the matched entry. if the lookup is a miss, the sf provides the contents of the victim entry, set and way information of the victim. the plru vector is not updated. the sf indicates if a single or double bit error was detected. single- bit errors are corrected (but the array is not updated). hit/miss calculation is performed after the ecc logic. inbound memory accesses will use this command for sf lookup. ? sf_update with plru status update by lru operation set and way are provided for write operations. writes can either be updates or invalidates. on sf-invalidations, the plru array is updated using a least-recently- used (lru) entry tracking algorithm. the sf update during inbound write will also use the ?sf_update with plru status update by lru op? if there is a hit during sf lookup. ? sf_update with no plru status update operation set and way are provided for write operations. the plru array is not updated. this command is used during non-sf-entry-invalidation operations. 5.3 system memory controller the mch masters four fully-buffered dimm (f b-dimm) memory channels. up to four dimms can be connected to each fb-dimm ch annel (up to sixteen dimms for the entire array). fb-dimm memory utilizes a narrow hi gh speed frame oriented interface referred to as a channel. [23] state of the cache line 1 the cache line is in e/m state, i.e. the line is ei ther exclusive (but clean) or modified (dirty) state. 0 the cache line is in non-e/m state, i.e. s state if bus presence vector is non-zero or i state if bus presence vector is zero. [22:21 ] bus presence vector [00] the entry is invalid [xx] the entry is present in any of the processo r l2 in the corresponding fsb. bus0 is the least significant bit. bus0 corresponds to fsb0 on the intel 5000 series chipset mc h. bus1 corresponding to fsb1 [20:0] tag portion of the address table 5-3. snoop filter entry bits value
functional description 306 intel ? 5000x chipset memory controller hub (mch) datasheet the four fb-dimm channels are organized into two branches of two channels per branch. each branch is supported by a separate memory controller (mc). the two channels on each branch operate in lock st ep to increase fb-dimm bandwidth. a branch transfers 16 bytes of payload/frame on southbound lanes and 32 bytes of payload/ frame on northbound lanes. the two branches may be operated in mirr ored (raid 1) or non-mirrored mode. when operating in mirrored mode, 64 gb of memory will produce an effective 32 gb memory space. the key features of the fb-dimm memory in terface are summarized in the following list. ? four fully buffered ddr (fb-dimm) memory channels. ? branch channels are paired together in lock step to match fsb bandwidth requirement. ? each fb-dimm channel can link up to four fully buffered - ddr dimms (fb-dimm). ? supports up to 16 dual-ranked fb-ddr2 4gb dimms, that is, 64gb 1 of physical memory in non-mirrored configuration or 32gb of physical memory in mirrored configuration. ? the fb-dimm link speed is at 6x the ddr data transfer speed. a 3.2 ghz fb-dimm link supports ddr2-533 (fsb@1067 mt/s). ? the mch will comply with the fb-dimm specif ication definition of a host and will be compatible with any fb-dimm-compliant dimm. ? special single channel, single dimm oper ation mode (branch 0, channel 0, slot 0 position only). ? all memory devices must be ddr2. ta b l e 5 - 2 and figure 5-4 present system memory capacity as a function of dram device capacity and mch operating mode. the smallest system configuration - one dimm column represents the smallest possible single dimm capacity for a given tec hnology (mch operating in single channel, single dimm mode with x8 single rank (x8sr) dimm populated). the smallest upgrade increment - two dimms column represents the smallest possible memory upgrade capacity for a given technology using two x8 single rank dimms. 1. user can only access up to 63.5 gb of memory due to minimum 256 mb mmio/tolm and limited address decoding above 64 gb. table 5-2. minimum system memory co nfigurations & up grade increments dram technology smallest system configuration - one dimm smallest upgrade increment - two dimm 256 mb 256 mb 512 mb 512 mb 512 mb 1024 mb 1024 mb 1024 mb 2048 mb 2048 mb 2048 mb 4096 mb
intel ? 5000x chipset memory controller hub (mch) datasheet 307 functional description note: the maximum capacity mirrored mode and maximum capacity non-mirrored mode columns represent the system memory available when all dimm slots ar e populated with identical x8 single rank (x8dr) dimms using the dram technology indicated. note: the maximum capacity mirrored mode and maximum capacity non-mirrored mode columns represent the system memory available when all dimm slots ar e populated with identical x4 double rank (x4dr) dimms using the dram technology indicated. 5.3.1 memory population rules dimm population rules depend on the oper ating mode of the mc. when operating in non-mirrored mode the minimum memory u pgrade increment is two identical dimms per branch (dimms must be identical with respect to size, speed, and organization). non-mirrored mode has an exceptional mode th at operates with a single dimm which is discussed in the following section. when operating in mirrored mode the minimum upgrade increment is four identical dimms 5.3.1.1 non-mirrored mode memory upgrades the minimum memory upgrade increment is two dimms per branch. the dimms must cover the same slot position on both channels. dimms that cover a slot position must be identical with respect to size, speed, and organization. dimms that cover adjacent slot positions need not be identical. within a branch memory dimms must be popu lated in slot order; slot 0 is populated first, slot 1 second, slot 2 third, and slot 3 last. slot 0 is closest to the mch. section 5-2 depicts the minimum two dimm configuration. the populated dimms are depicted in gray (slot 0 of branch 0 populated). table 5-3. maximum 16 dimm sy stem memory configurations dram technology x8 single rank maximum capacity mirrored mode maximum capacity non-mirrored mode 256 mb 2 gb 4 gb 512 mb 4 gb 8 gb 1024 mb 8 gb 16 gb 2048 mb 16 gb 32 gb table 5-4. maximum 16 dimm sy stem memory configurations dram technology x4 dual rank maximum capacity mirrored mode maximum capacity non-mirrored mode 256 mb 8 gb 16 gb 512 mb 16 gb 32 gb 1024 mb 32 gb 64 gb 2048 mb 32 gb 64 gb
functional description 308 intel ? 5000x chipset memory controller hub (mch) datasheet figure 5-3 depicts the next two positions where dimms may be added. these positions are depicted in dark gray. the two upgrade po sitions are branch 0, slot 1 and branch 1, slot 0. of these branch 1, slot 0 is the preferred upgrade because it allows both branches to operate independently and simu ltaneously. fb-dimm memory bandwidth is doubled when both branches operate in parallel. while it is possible to completely populate one branch before populating the second branch, it is not desirable to do so from a performance standpoint. in general memory upgrades should be balanced with respec t to both branches to optimize fb-dimm performance. figure 5-4 depicts a special single dimm non-mirrored operation mode. this mode requires that the dimm be placed in branch 0, channel 0, slot 0. when upgrading from this mode the normal two dimm memory upgrade rules are followed. figure 5-2. minimum two dimm configuration channel 2 channel 3 memory controller channel 0 channel 1 slot 3 slot 2 slot 1 slot 0 slot 0 slot 1 slot 2 slot 3 branch 0 branch 1 figure 5-3. next two dimm upgrade positions channel 2 channel 3 memory controller channel 0 channel 1 slot 3 slot 2 slot 1 slot 0 slot 0 slot 1 slot 2 slot 3 branch 0 branch 1
intel ? 5000x chipset memory controller hub (mch) datasheet 309 functional description 5.3.1.2 mirrored mode memory upgrades when operating in mirrored mode both bran ches operate in lock step. in mirrored mode branch 1 contains a replicate copy of the data in branch 0. for this reason the minimum memory upgrade increment, for mirrored mode, is four dimms across all branches. the dimms must cover the same slot position on both branches. dimms that cover a slot position must be identical with respect to size, speed, and organization. dimms within a slot position must match each other, but aren?t required to match adjacent slot positions. figure 5-5 shows the minimum memory configuration required to operate in mirrored mode. figure 5-4. single dimm operation mode channel 2 channel 3 memory controller channel 0 channel 1 slot 3 slot 2 slot 1 slot 0 slot 0 slot 1 slot 2 slot 3 branch 0 branch 1 figure 5-5. minimum mirrored mode memory configuration channel 2 channel 3 memory controller channel 0 channel 1 slot 3 slot 2 slot 1 slot 0 slot 0 slot 1 slot 2 slot 3 branch 0 branch 1
functional description 310 intel ? 5000x chipset memory controller hub (mch) datasheet figure 5-6 shows the positions of the next four dimm upgrade. like non-mirrored mode upgrade dimms must be added in slot order, starting from the slot closest to the mch. dimms in a slot position must be identical with respect to size, and organization. speed should be matched but is not required. the mch will adjust to th e lowest speed dimm. dimms in adjacent slots need not be identical. 5.3.2 fully buffered dimm technology and organization fully buffered dimm technology was developed to address the higher performance needs of server and workstation platform s. fb-dimm addresses the dual needs for higher bandwidth and larger memory sizes. fb-dimm memory dimms contain an advanced memory buffer (amb) device that serves as an interface between the point to point fb-dimm channel links and the ddr2 dram devices. each amb is capable of bufferi ng up to two ranks of dram devices. each amb supports two complete fb-dimm channel in terfaces. the first fb-dimm interface is the incoming interface between the amb and its proceeding device. the second interface is the outgoing interface and is between the amb and its succeeding device. the point to point fb-dimm links are termin ated by the last amb in a chain. the outgoing interface of the last amb requires no external termination. there are three major components of the fb-dimm channel interface: ? 14 differential northbound signal pairs ? 10 differential southbound signal pairs ? 1 differential clock signal pair figure 5-7 depicts a single fb-dimm channel with these three signal groups. figure 5-6. mirrored mode next upgrade channel 2 channel 3 memory controller channel 0 channel 1 slot 3 slot 2 slot 1 slot 0 slot 0 slot 1 slot 2 slot 3 branch 0 branch 1
intel ? 5000x chipset memory controller hub (mch) datasheet 311 functional description a fb-dimm channel consists of 14 unidirectional differential signal pairs referred to as the northbound path, 10 unidirectional diffe rential signal pairs referred to as the southbound path, and a differential reference clock. note: the northbound signal pairs are enumerated from 0 to 13. signal pair 13 is not active but must be connected to proper ly terminate the fb-dimm channel. see sections, figure 2.2.1, ?fb-dimm branch 0? on page 29 and figure 2.2.2, ?fb-dimm branch 1? on page 30 . the southbound path is used to convey dimm commands and write data to the addressed dimms. the northbound path returns read data and status from the addressed dimm. the northbound and southbound paths are used to convey fb-dimm frames that are synchronized to the reference clock. each frame consists of 12 data transfers. southbound frames contain a payload of 8 bytes per frame per channel. northbound frames contain a payload of 16 bytes per frame per channel. figure 5-7. fb-dimm channel schematic northbound slot 3 slot 2 slot 1 slot 0 dram amb dram dram dram dram dram dram amb dram dram dram dram dram southbound northbound southbound memory controller branch 0 channel 0 channel 1 10 14 14 10 dram amb dram dram dram dram dram dram amb dram dram dram dram dram clock generator
functional description 312 intel ? 5000x chipset memory controller hub (mch) datasheet 5.3.3 fb-dimm memory operating modes the mch supports two majo r modes of operation, mirrored and non-mirrored. 5.3.3.1 non-mirrored mode operation when operating in non-mirrored mode the mch operates the two branches independently. in non-mirrored mode the full mch address space of 64gb is available. normally when operating in non-mirrored mode both channels on a branch are operated in lock step, referred to as dual-c hannel mode. there is a single dimm, single channel mode of operation referred to as single-channel mode. 5.3.3.1.1 non-mirrored mode ecc ecc is supported differently for each of these single- and dual-channel modes: dual-channel mode: when branches operate in dual-channel mode , the mch supports the 18 device dram failure correction code option for fb-dimm. as applied by intel 5000x chipset mch, this code has the following properties: ? correction of any x4 or x8 dram device failure ? detection of 99.986% of all single bit failu res that occur in addition to a x8 dram failure. the mch will detect a series of failures on a specific dram and use this information in addition to the informatio n provided by the code to achieve 100% detection of these cases. ? detection of all two wire faults on the di mms. this includes any pair of single bit errors. ? detection of all permutations of two x4 dram failures. single-channel mode: when the branch operates in single-channel/single-dimm mode, the mch employs x8 sddc as in the dual channel case. however, in this case, the ecc ras feature set is limited for the single dimm memory subs ystem. in the single dimm mode (for example, nine x8 devices), the sddc cannot correct single wire fault (stuck-at) errors or permanent full device errors. this is because the error correction capability in the sddc is limited to adjacent symbol errors on a 16-bit boundary and in the single dimm mode with a burst length of 8, there are 4 transfers of 8b to form a 32b codeword. hence a single wire failure in the same device is replicated across all 4 symbols hampering the error correction. the sddc ca n detect most x4/x8 dram failures but it can only correct adjacent symbol errors th at occur within a 16-bit boundary of each codeword 5.3.3.2 mirrored mode operation memory mirroring mch is a user-selectable feature. mirrored mode provides for complete recovery from a dimm device failu re. the mirroring feature is fundamentally a way for hardware to maintain two copies of all data in the memory subsystem, such that a hardware failure or uncorrectable error is no longer fatal to the system. when an uncorrectable error is encountered during no rmal operation, hardware simply retrieves the ?mirror? copy of the corrupted data, and no system failure will occur unless both primary and mirror copies of the same data are corrupt simultaneously (statistically very unlikely).
intel ? 5000x chipset memory controller hub (mch) datasheet 313 functional description when operating in mirrored mode fb-dimm branch 0 (channels 0/1) and branch 1 (channels 2/3) contain replicate copies of data (are mirrored images). since branch 1 contains a replicate copy of branch 0?s data, the maximum addressable memory is reduced to 32 gb. mirrored mode must be selected at configuration time by enabling mirrored operation. the general flows for mirroring are as follows: ? the same write (in the non-failed case) is issued to both branches in the same cycle (which is complete when both branches acknowledge). ? different reads (in the non-failed case) are issued to each branch in the same cycle. read returns from branch 1 are de layed two cycles from read returns from branch 0. ? corrected data will be forwarded to the requester. ? uncorrectable errors will be retried from the other image. if the other image is off- line, uncorrectable errors will be retried from the same image. ? software can temporarily degrade operat ion to one memory branch and then resume operation with both memory branches. ? to recover from a failed dimm: ? dimm failure is detected ? the defective branch is shut down ? the system is gracefully shut down by operator and the defective dimm is replaced ? the system is repowered up ? normal processing is restored 5.3.3.3 mirrored mode ecc when operating in non-mirrored mode the mch operates the two branches in lock step (one branch mirroring the contents of the other). in mirrored mode the maximum address space is reduced to 32gb because th e two channels are mirroring each other. when operating in mirrored mode both channels on a branch are operated in lock step, referred to as dual-channel mode. ecc is calculated using the dual-channel method defined in section 5.3.3.1.1. 5.3.3.4 memory sparing at configuration time, a dimm rank is set aside to replace a defective dimm rank. when the error rate for a failing dimm rank re aches a pre-determined threshold, the spcps.lbthrconfiguration bit will issue an interrupt and initiate a spare copy. while the copy engine is automatically reading locations from the failing dimm rank and writing them to the spare (see section 3.9.23.4 and section 3.9.23.5 , ?spare copy status & spare copy control?, system read s will be serviced from the failing dimm rank, and system writes will be written to both the failing dimm rank and the spare dimm rank. at the completion of the copy, the failing dimm rank is disabled and the ?spared? dimm rank will be used in its plac e. the mch will change the rank numbers in the dmirs from the failing rank to the sp are rank. dmir.limit?s are not updated. this mechanism requires no software support once it has been enabled by designating the spare rank through the spcpc.sprank configuration register field and enabling sparing by setting the spcp c.sparen configuration bit. hardware will detect the threshold-initiated fail, accomplish the copy , and off-line the ?failed? dimm rank once
functional description 314 intel ? 5000x chipset memory controller hub (mch) datasheet the copy has completed. this is accomplis hed autonomously by the memory control subsystem. the spcps.sfo configuration bit is set and an interrupt is issued indicating that a sparing event has completed. sparing cannot be invoked while operating a mirrored memory configuration. sparing to a smaller dimm is not supported. note: dimm sparing is not validated in the single channel mode when intel 5000p chipset.mca.schdimm is set. 5.3.4 data poisoning in memory data poisoning in memory is defined as all zeroes in the code word (32b0 except for the least significant bytes being 0xff00f f. the intel 5000p chipset mch poisons a memory location based on the events described in table 5.5, ?memory poisoned table? 5.3.5 patrol scrubbing to enable this function, the mc.scrben configuration bit must be set. the scrub unit starts at dimm rank 0 / address 0 upon reset. every 16k core cycles the uni t will scrub one cache line and then increment the address one cache line provided that ba ck pressure or other internal depe ndencies (queueing, conflicts etc) do not prolong the issuing of these transactions to fb-d imm. using this method, roughly 64gbytes of memory behind the intel 5000p chipset mch can be completely scrubbed every day (estimat e). error logs include ras/cas/bank/rank. patrol scrub writes hit both branches in mirrored mode (when mc.mirror is set). normally, one branch is scrubbed in entirety before proceeding to the other branch. in the instance of a fail-down to non-redundant operation that off-lines the branch that was being scrubbed, the scrub pointer merely migrates to the other branch without being cleared. in this unique instance, the scrub cycles for that branch is incomplete. table 5-5. memory poisoning table event correctable error uncorrectable error normal memory read correct data to be given register intel 5000p chipset mch logs m17 error. (correctable non-mirrored demand data ecc error) correct data to be written back to memory detects an uncorrectable and logs a m9 error (non-aliased uncorrectable non- mirrored demand data ecc error) re-issue read to memory if error persistent 1. poison the response to requester and log. 2. leave data untouched in memory location patrol scrub correct data to be written back to memory and log m20 error. (correctable patrolled data ecc error) 1. log and signal m12 error (non-aliased uncorrectable patrol data ecc error). 2: leave data untouched in memory location. dimm spare copy correct data to be written back to memory and log m19 error. (correctable re-silver or spare copy data ecc error) if error persistent 1. log and signal m11 error (non aliased uncorrectable re-silver or spare copy data ecc error). 2: poison location in dimm spare mirror copy correct data to be written to new memory and log m19 error. (correctable re-silver or spare copy data ecc error) re-use read to memory and signal a m11 error. (non-aliased unco rrectable re-silver or spare copy data ecc error). if error persistent 1. poison the new memory image.
intel ? 5000x chipset memory controller hub (mch) datasheet 315 functional description 5.3.6 demand scrubbing to enable this function, the mc.demsen config uration bit must be set. correctable read data will be corrected to the requestor and scrubbed in memory. this adds an extra cycle of latency to accomplish the correction. error logs include ras/cas/bank/rank. demand scrubbing is not available in mirrored mode (when mc.mirror is set) to simplify the design. if a correctable error is encountered, the data is corrected and sent to the requestor at the cost of one extra cycl e of latency. the probability of soft errors due to alpha rays affecting multiple x4/x8 devices is low. however, patrol scrubbing when enabled in the intel 5000p chipset mc h for the mirrored mode will clean up all correctable errors in the memory running in the background and runs twice as fast. there is no incurred ras benefit by enforcin g demand scrubbing in mirrored mode with the exception of the error logging. demand scrubbing does not help in failed ecc case (uncorrectable errors). that is, if the data read is uncorrectable from the bad branch, then the golden data needs to be retrieved from the other mirrored branch (copy) at the cost of additional fb-dimm reset, link tr aining and ddr protocol rules. the failed branch is offlined and needs to be replaced for mirroring to continue. 5.3.7 x8 correction 5.3.7.1 normal this correction mode is in effect when th e mc.scrbalgo configuration bit is cleared. an erroneous read will be logged. if the ecc was correctable, it is corrected (scrubbed) in memory. a conflicting read or write reques t pending issue will be held until the scrub is either completed or aborted because it was uncorrectable. 5.3.7.2 enhanced this correction mode is in effect when th e mc.scrbalgo configuration bit is set and software has initialized the mc .badramth to a non-zero value. ? maintain 4-bit saturating counters per ra nk in the badcnt configuration registers. floor at zero. saturate at the value of th e mc.badramth configuration register field. increment on correctable errors on both symbols of a x8 device and northbound crc ok. decrement upon completion of the num ber of patrol scrub cycles through the entire memory specified by the mc.badramth configuration register field. a sufficient resolution of this period is three patrol scrub cycles through all memory. ? maintain five-bit bad-device marks per rank in the badram(a/b) configuration registers. upon incrementing badcnt to saturati on, then mark the bad devices in the badram(a/b) configuration registers. ? a correctable ecc in a symbol other than that marked in the badram(a/b) configuration registers is an aliased uncorrectable read. an erroneous read will be logged. if the read was correctable, it is corrected (scrubbed) in memory. a conflicting read or write request remains pend ing until the scrub succeeds or is dropped. a failed scrub is replayed once, resulting in success or a drop.
functional description 316 intel ? 5000x chipset memory controller hub (mch) datasheet 5.3.8 single device data correction (sddc) support the intel 5000x chipset mch employs a single device data correction (sddc) algorithm for the memory subsystem that w ill recover from a x4/x8 component failure. the chip disable is a 32-byte two-phase code . sddc is also suppor ted for x4 devices. in addition the mch supports demand and patrol scrubbing. a scrub corrects a correctable error in memory. a four-byte ecc is attached to each 32- byte ?payload?. an error is detected wh en the ecc calculated from the payload mismatches the ecc read from memory. the error is corrected by modifying either the ecc or the payload or both and writing bo th the ecc and payload back to memory. only one demand or patrol scrub can be in process at a time. the attributes of the sddc code are as follows: ? two phase code over 32 bytes of data. ? 100% correction for all single x4 or x8 component failures. ? 100% detection of all double x4 component failures. ? detection characteristics for x8 double device errors are provided in the ta b l e 5 - 6 to increase the detection coverage of a (x8 device failure + sbe), that is, to avoid silent data corruption in the event of a particle induced error while correcting for a failed device, the intel 5000x chipset mch mc h provides the following features: ? each rank will have an encoded value of the ?failed? x8 component or pair of x4 components. ? if for any given rank, the intel 5000x ch ipset mch mch detects a correctable error with a weight >1 and the ?corrected? symbol does not match the ?failed? component then the intel 5000x chipset mch mch will assume that the error is multi-bit uncorrectable error and signal a ?fatal error?. 5.3.9 fb-dimm memory co nfiguration mechanism before any cycles to the memory interface can be supported, the mch dram registers must be initialized. the mch must be conf igured for operation with the installed memory types. detection of memory type and size is accomplished via the 4 serial presents detect (system management bus) in terfaces on the mch (smbus 1, 2, 3 and 4). the smbus interfaces are two-wire buse s are used to extract the dram type and size information from the serial presence detect port on the dimms. fb-dimms contain a 6-pin serial presence de tect interface, which includes scl (serial clock), sda (serial data), and sa[3:0] (serial address). devices on the smbus bus have a 7-bit address. for the dimms, the upper three bits are fixed at 101. the lower four bits are strapped via the sa[3:0] pins. scl and sda are connected to the respective spdxsmbdata, spdxsmbclk pins on the mch, see figure 5-8 . table 5-6. x8 double device detection characteristics overall coverage - 99.986% device plus single - 99.99999% double bit errors - 100% device plus wire - 99.99998% double wire faults - 100% devi ce plus equal/phase - 99.9998% wire plus single bit - 100% equal/phase plus equal/phase - 100%
intel ? 5000x chipset memory controller hub (mch) datasheet 317 functional description the intel 5000x chipset mch mch integrates a 100khz spd controller to access the dimm spd eeprom?s. there are four spd po rts. spd0smbdata, and spd0smbclk are defined for channel 0; spd1smbdata, and spd1smbclk are defined for channel 1; spd2smbdata, and spd2smbclk are defined for channel 2; and spd3smbdata, and spd3smbclk are defined for channel 3. there can be a maximum of eight spd eeprom?s associated with each spd bus. therefore, the spd interface is wired as indicated in figure 5-8 . board layout must map chip selects to spd slave addresses as shown in ta b l e 5 - 7 . the slave address is written to the spdcmd configuration register (see section 3.9.26.2 ). figure 5-8. connection of dimm serial i/o signals scl1/ sda1 intel? 5000p chipset slot 3 slot 2 slot 1 slot 0 channel 0 channel 1 scl2/ sda2 channel 2 channel 3 sda3 scl3/ sda0 scl0/ sa0 sa2 sa1 sa0 sa2 sa1 sa0 sa2 sa1 sa0 sa2 sa1 sa0 sa2 sa1 sa0 sa2 sa1 sa0 sa2 sa1 sa0 sa2 sa1 sa0 sa2 sa1 sa0 sa2 sa1 sa0 sa2 sa1 sa0 sa2 sa1 sa0 sa2 sa1 sa0 sa2 sa1 sa0 sa2 sa1 sa0 sa2 sa1 dimm dimm dimm dimm dimm dimm dimm dimm dimm dimm dimm dimm dimm dimm dimm dimm table 5-7. spd addressing spd bus fb-dimm channel slot slave address 0000 11 22 33 1100 11 22 33 2200 11 22 33 3300 11 22 33
functional description 318 intel ? 5000x chipset memory controller hub (mch) datasheet 5.3.10 fb-dimm memory fail ure isolation mechanisms since the intel 5000x chipset mch does no t operate fb-dimm in fail-over mode, crc accompanies northbound data. successful transaction completion is signalled by the absence of alerts within a read round-trip. bad crc accompanies alerts. alerts preempt read data. detection of corrupted crc or corrupted write acknowledge (idle) will initiate an fb-dimm fast reset followed by a retry of all commands since completion of the last successful transaction. a consecutive crc/ack failure on the same transaction is fatal. 5.3.10.1 fb-dimm configuration read error an erroneous configuration read return will be master aborted and return all 1?s. it will not be retried. 5.3.10.2 dimm failure isolation the failing dimm may be isolated using inform ation contained in several registers. ecc error flag bits are recorded in register ferr_nf_fbd, section 3.9.22.3 . this register records various error sources related to fb-dimm memory transactions. when an error occurs the channel/branch information is recorded in the fbdchan_indx field. the fbdchan_indx is a two bit field that records branch ecc errors. ecc errors are reported on a per branch basis (the lsb of this field has no relevance for ecc errors). for ecc errors the possible values for this field are: fbdchan_indx = 0 branch 0 ecc error fbdchan_indx = 2 branch 1 ecc error once the branch is determined the failing dimm is determined, the rank and dimm is determined from the recmema.rank and redmemb.ecc_locator fields. the ecc_locator indicates which x8 sdram device (or pair of adjacent x4 devices) caused the error. if any of the bits [8:0] is set, a dimm on the even channel caused the error. if any of the bits [17:9] is set, a dimm on the odd channel caused the error. see ta b l e 3 - 4 9 . for uncorrectable errors the nrecmema.rank register is used to identify the failing dimm pair (lockstep channels). after a mirrored branch is taken off line, bios can execute membist routines on the suspect dimm-pair to reproduce failures. th is can be performed out-of-band using the spd (sm bus) interface. 5.3.10.3 ecc code when branches operate in dual-channel mode , the mch supports the 18 device dram failure correction code (sddc aka secc) op tion for fb-dimm. as applied by intel 5000p chipset, this code has the following properties: ? correction of any x4 or x8 dram device failure ? detection of 99.986% of all single bit failu res that occur in addition to a x8 dram failure. the intel 5000x chipset mch will detect a series of failures on a specific dram and use this information in addition to the information provided by the code to achieve 100% detection of these cases. ? detection of all 2 wire faults on the dimms. this includes any pair of single bit errors.
intel ? 5000x chipset memory controller hub (mch) datasheet 319 functional description ? detection of all permutations of 2 x4 dram failures. when the branch operates in single-c hannel/single-dimm mode, the intel 5000p chipset mch employs x8 sddc as in the dual channel case. however, in this case, the ecc ras feature set is limited for the single dimm memory subsystem. in the single dimm mode (for example, nine x8 devices) , the sddc cannot correct single wire fault (stuck-at) errors or permanent full device errors. this is because the error correction capability in the sddc is limited to adjacent symbol errors on a 16-bit boundary and in the single dimm mode with a burst length of 8, there are 4 transfers of 8b to form a 32bcode word. hence a single wire failure in the same device is replicated across all 4 symbols hampering the error correction. the sddc can detect most x4/x8 dram failures but it can only correct adjacent symbol errors that occur within a 16-bit boundary of each code word. 5.3.10.4 inbound ecc code layout for dual-channel branches the code is systematic: that is, the data is separated from the check-bits rather than all being encoded together. it consists of 32 eight-bit data symbols (ds31-ds0) and four eight-bit check-bit symbols (cs3-cs0). the code corrects any two adjacent symbols in error. the symbols are arranged so that the data from every x8 dram is mapped to two adjacent symbols, so any failure of the dram can be corrected. figure 5-9 illustrates the ecc code layout for branch 0. the figure shows how the symbols are mapped on the fb-dimm branch and to dram bits by the dimm for a transfer in which the critical 16 b is in the lower half of the code-word (a[4]=0). if the upper portion of the code-word were transfe rred first, bits[7:4] of each symbol would be transferred first on the dram interface an d in the first six transfers on the fb-dimm channel. the layout for branch 1 is the same. the bits of data symbol 0 (ds0) are trac ed from dram to fb-dimm northbound. the same mapping of symbols to data and code bits applies to southb ound data. the lower nibble (ds0a) consists of ds0[3:0] the upper nibble (ds0b) consists of ds0[7:4]. on the dram interface, ds0 is expanded to show that it occupies 4 dram lines for two transfers. ds0[3:0] appears in the first transfer. ds0[7:4] appear in the second transfer. ds0 and ds1 are the adjacent symbols that protect the eight lines from the first dram on dimm0. the same ds0 is sh own expanded on the northbound fb-dimm interface where it occupies the fd0nb[p:n ][0] signal. ds0 and ds1 cover all transfers on fd0nb[p:n][0] (even though fd0nb[p:n][0] does not cover all of ds1).
functional description 320 intel ? 5000x chipset memory controller hub (mch) datasheet figure 5-9. code layout fo r single-channel branches transfer 0 transfer 1 c s 3 b c s 2 b d s 2 0 b d s 1 9 b d s 2 1 b d s 1 8 b d s 2 4 b d s 2 3 b d s 2 5 b d s 2 2 b d s 2 8 b d s 2 7 b d s 2 9 b d s 2 6 b d s 3 1 b d s 3 0 b d s 1 7 b d s 1 6 b dram pi ns fd0nby[ 0] dram s fbd channel 0 packet 0 dq [1] dq [2] dq [3] x8 x8 x8 x8 x8 x8 x8 x8 x8 f d 0 n b y 0 di m m channel 0 dat a bi t s dq [71:0] cb [7:0] f d 0 n b y 0 f d 0 n b y 1 f d 0 n b y 2 f d 0 n b y 3 f d 0 n b y 4 f d 0 n b y 5 f d 0 n b y 6 f d 0 n b y 7 f d 0 n b y 8 f d 0 n b y 9 f d 0 n b y 1 0 d s 0 a d s 1 a d s d s d s d s c s 4 a 7 a 1 0 a 1 3 a c s 1 a 0 a d s 3 a d s 6 a d s 9 a d s 1 2 a d s 1 5 a d s 1 1 a d s 1 4 a d s 8 a d s 5 a d s 2 a d[ 3] d[ 2] d[ 1] d[ 0] d[ n] d[n+1] d[ n+2] d[ n+3] ds0 [0] ds0 [1] ds0 [2] ds0 [3] ds0 [4] ds0 [5] ds0 [6] ds0 [7] d[131] d[130] d[129] d[128] f d 0 n b y 1 1 d[131] d[130] d[129] d[128] d s 0 b d s 1 b d s d s d s d s c s 4 b 7 b 1 0 b 1 3 b c s 1 b 0 b d s 3 b d s 6 b d s 9 b d s 1 2 b d s 1 5 b d s 1 1 b d s 1 4 b d s 8 b d s 5 b d s 2 b ds0 [6] ds0 [7] ds1 [4] ds1 [5] ds0 [0] ds0 [1] ds0 [2] ds0 [3] ds1 [0] ds1 [1] ds0 [4] ds0 [5] fbd si gnal y=[p:n] 0 1 2 3 4 5 6 7 8 9 1 0 1 1 transfer d s 2 a d s 1 a d s 3 a d s 0 a d s 6 a d s 5 a d s 7 a d s 4 a d s 1 0 a d s 9 a d s 1 1 a d s 8 a d s 1 4 a d s 1 3 a d s 1 5 a d s 1 2 a c s 1 a c s 0 a d s 2 b d s 1 b d s 3 b d s 0 b d s 6 b d s 5 b d s 7 b d s 4 b d s 1 0 b d s 9 b d s 1 1 b d s 8 b d s 1 4 b d s 1 3 b d s 1 5 b d s 1 2 b c s 1 b c s 0 b transfer 0 transfer 1 c s 2 a d s 2 0 a d s 1 9 a d s 2 1 a d s 1 8 a d s 2 4 a d s 2 3 a d s 2 5 a d s 2 2 a d s 2 8 a d s 2 7 a d s 2 9 a d s 2 6 a d s 3 1 a d s 3 0 a d s 1 7 a d s 1 6 a c s 3 a packet 1 fbd si gnal s d s d s d s d s d s c s 1 7 a 2 0 a 2 3 a 2 6 a 2 9 a c s 3 a 2 a d s 1 6 a d s 1 9 a d s 2 2 a d s 2 5 a d s 2 8 a d s 3 1 a d s 1 8 a d s 2 1 a d s 2 4 a d s 2 7 a d s 3 0 a d s d s d s d s d s c s 1 7 b 2 0 b 2 3 b 2 6 b 2 9 b c s 3 b 2 b d s 1 6 b d s 1 9 b d s 2 2 b d s 2 5 b d s 2 8 b d s 3 1 b d s 1 8 b d s 2 1 b d s 2 4 b d s 2 7 b d s 3 0 b 0 1 2 3 4 5 6 7 8 9 1 0 1 1 dq [0]
intel ? 5000x chipset memory controller hub (mch) datasheet 321 functional description figure 5-10. code layout for dual-channel branches transf er 0 transf er 1 d s 2 a d s 1 a d s 3 a d s 0 a d s 6 a d s 5 a d s 7 a d s 4 a d s 1 0 a d s 9 a d s 1 1 a d s 8 a d s 1 4 a d s 1 3 a d s 1 5 a d s 1 2 a c s 1 a c s 0 a d s 2 b d s 1 b d s 3 b d s 0 b d s 6 b d s 5 b d s 7 b d s 4 b d s 1 0 b d s 9 b d s 1 1 b d s 8 b d s 1 4 b d s 1 3 b d s 1 5 b d s 1 2 b c s 1 b c s 0 b c s 3 a c s 2 a d s 2 0 a d s 1 9 a d s 2 1 a d s 1 8 a d s 2 4 a d s 2 3 a d s 2 5 a d s 2 2 a d s 2 8 a d s 2 7 a d s 2 9 a d s 2 6 a d s 3 1 a d s 3 0 a d s 1 7 a d s 1 6 a c s 3 b c s 2 b d s 2 0 b d s 1 9 b d s 2 1 b d s 1 8 b d s 2 4 b d s 2 3 b d s 2 5 b d s 2 2 b d s 2 8 b d s 2 7 b d s 2 9 b d s 2 6 b d s 3 1 b d s 3 0 b d s 1 7 b d s 1 6 b d r am pi ns fd 0n by[ 0] d r a m s fbd br anch 0 packet d q [0] d im m c hannel 0 d q [1] d q [2] d q [3] x8 x8 x8 x8 x8 x8 x8 x8 x8 x8 x8 x8 x8 x8 x8 x8 x8 x8 f d 0 n b y 0 fbd si gnal s d im m c hannel 1 d at a bi t s d q [ 71: 0] c b [7:0] d q [ 71: 0] c b [7:0] f d 0 n b y 0 f d 0 n b y 1 f d 0 n b y 2 f d 0 n b y 3 f d 0 n b y 4 f d 0 n b y 5 f d 0 n b y 6 f d 0 n b y 7 f d 0 n b y 8 f d 0 n b y 9 f d 0 n b y 1 0 f d 1 n b y 1 f d 1 n b y 2 f d 1 n b y 3 f d 1 n b y 4 f d 1 n b y 5 f d 1 n b y 6 f d 1 n b y 7 f d 1 n b y 8 f d 1 n b y 9 f d 1 n b y 1 0 f d 1 n b y 1 1 d s 0 a d s 1 a d s d s d s d s c s d s d s d s d s d s c s 4 a 7 a 1 0 a 1 3 a 1 7 a 2 0 a 2 3 a 2 6 a 2 9 a c s 1 a 0 a c s 3 a 2 a d s 3 a d s 6 a d s 9 a d s 1 2 a d s 1 5 a d s 1 6 a d s 1 9 a d s 2 2 a d s 2 5 a d s 2 8 a d s 3 1 a d s 1 1 a d s 1 4 a d s 1 8 a d s 2 1 a d s 2 4 a d s 2 7 a d s 3 0 a d s 8 a d s 5 a d s 2 a d [3] d [2] d [1] d [0] d [n] d [n+1] d [n+2] d [n+3] d s0 [0] d s0 [1] d s0 [2] d s0 [3] d [3] d [2] d [1] d [0] d s0 [4] d s0 [5] d s0 [6] d s0 [7] d [ 131] d [130] d [129] d [128] f d 0 n b y 1 1 f d 1 n b y 0 d [131] d [130] d [129] d [128] d s 0 b d s 1 b d s d s d s d s c s d s d s d s d s d s c s 4 b 7 b 1 0 b 1 3 b 1 7 b 2 0 b 2 3 b 2 6 b 2 9 b c s 1 b 0 b c s 3 b 2 b d s 3 b d s 6 b d s 9 b d s 1 2 b d s 1 5 b d s 1 6 b d s 1 9 b d s 2 2 b d s 2 5 b d s 2 8 b d s 3 1 b d s 1 1 b d s 1 4 b d s 1 8 b d s 2 1 b d s 2 4 b d s 2 7 b d s 3 0 b d s 8 b d s 5 b d s 2 b d s0 [6] d s0 [7] d s1 [4] d s1 [5] d s0 [0] d s0 [1] d s0 [2] d s0 [3] d s1 [0] d s1 [1] d s0 [4] d s0 [5] fbd si gnal y=[p:n ] 0 1 2 3 4 5 6 7 8 9 1 0 1 1 t r a n s f e r
functional description 322 intel ? 5000x chipset memory controller hub (mch) datasheet 5.3.10.5 ecc code layout for a single-channel branch the ninth byte of each burst on each dimm contains the ecc bits for 8 bytes of data. these nine bytes comprise a code word. there are eight code words in a cache line. 5.3.11 ddr2 protocol 5.3.11.1 posted cas posted cas timing is used. 5.3.11.2 refresh regardless of the number of dimms installe d, each rank will get a minimum of one refresh every eight periods defined by the drt.tref configuration register field. the refreshes cycle through all eight dimm ranks. the dimm enters self-refresh mode during an fb-dimm fast reset. 5.3.11.3 access size all memory accesses are 64b. 5.3.11.4 transfer mode each dimm is programmed to use a burst-le ngth of 32 bytes (4 transfers) across the channel. the mode register of each dimm mu st be programmed for a burst length of 4, and interleave mode. 5.3.11.5 invalid and unsu pported ddr transactions the memory controller prevents cycle combinations leading to data interruption or early termination. the memory controller prevents combinations of ddr commands that create bus contention (that is, where multiple ranks would be required to drive data simultaneously on a dimm). the memory controller does not interrupt writes for reads. a precharge command is provided, bu t early read or write termination due to precharge is not supported. 5.3.12 memory thermal management the intel 5000x chipset mch supports fb -dimm throttling and power management through several mechanisms. the first mechanism forces power down of unused or failed channels by setting the fb-dimmhpc.s tate to reset. this corresponds to the disable state in the fb-dimm specification which holds the fb-dimm channel in reset. when in reset, the channel receivers and drivers are disabled. the second method of power management ut ilizes an adaptive methodology to control the number of activations (memory requests) sent to a fb-dimm. this methodology is composed of two components: 1. activation throttling: this is compos ed of closed and open loop throttling mechanisms to control the number of activations sent to fb-dimm devices. a. closed loop thermal activation control is based on the temperature of the fb- dimm device. this mechanism becomes active when the fb-dimm device temperature exceeds programmed thresholds.
intel ? 5000x chipset memory controller hub (mch) datasheet 323 functional description b. open loop global activate control becomes active when the number of activates exceeds a programmed number with in a long window period. 2. electrical throttling is used to prevent silent data corruption by limiting the number of activates per rank with in a short sliding window period. 5.3.12.1 closed loop thermal activate throttle control closed loop thermal activate throttling co ntrol uses the temperature of the fb-dimm temperature sensor located in the amb to determine when to throttle. fb-dimm (amb temperature) is returned each sync packet. a thermal throttle period is defined as window consisting of 1,344 cycles (42*3 2). the throttling logic in the memory controller uses this information to limit the number of activates to any dimm within a throttling window based on temperature thre shold crossing algorithm described later. every 42 frames the host controller is required to send a sync 1 packet, which returns a status packet from the ambs along with temperature information. the amb component has two temperature threshold points, t low (programmed into the gb.templo register, a.k.a. t1) and t mid (programmed into the gb.tempmid register, a.k.a. t2), and the current temperature of the gb with respect to these thresholds are returned in the status packet. in addition, the sync and status packets guarantees that enough transitions occur on each lane to maintain proper bit lock. 1. the sync packet may be dispatched by th e mch at an interval less than 42 frames depending on the gear ratios, timing, circuit and other parameters. for example, in the case of the core running at 266 mhz and the ddr2 clock at 333 mhz (4:5), the mch can send a sync every 32@266 mhz=40 ddr2 333 mhz clocks. this meets the minimum 42 clock requirement of the fb-dimm protocol for sync packet generation frequency. in each 42 frame period: frames 1-40 are used for normal dram tr affic: the a slot for dram commands and b/c for write data, as necessary. frame 41 is used for configuration commands: if a configuration read, it will appear in the a slot. if a configuration write it w ill appear in b/c (which is the only choice). frame 42 is used by the sync packet and occupies the a, b, and c slots. fb-dimm thermal information is returned in the sync packet as an encoded 2 bit field. the encoding of this field described in the following table. this data is a duplication of the contents of the amb.fbds0 register discussed in the gold bridge component external design specification . these 2 bits are returned for each amb during in the status packet. table 5-8. amb thermal status bit definitions s[2:1] thermal trip: this field indicates various thermal conditions of the amb as follows: 00 below templo 01 above templo 10 above tempmid and falling 11 above tempmid and rising
functional description 324 intel ? 5000x chipset memory controller hub (mch) datasheet the templo threshold is generally used to in form the host to accelerate refresh events. the tempmid threshold is generally used to inform the host that a thermal limit has been exceeded and that thermal throttling is needed. there are separate counters associated with each of the 2 lockstep fb-dimm pairs in a given branch (one counter per fb-dimm pair per branch). when any of the counters reaches its limit (as specified by the thrtsts.thrmthrt register field for a given branch), the entire branch is throttled until the end of the throttle window. no new dram commands are issued to any of the di mms on the branch until the end of the throttle window. if an activate has been issu ed to a bank, the follow on read or write may be issued, including an additional page hit access if applicable, to allow the page to close. 5.3.12.2 sequence of ac tions during throttling when throttling begins during a given throttling window, the following actions take place: 1. stop new dram commands 2. wait ?x? clocks for dram commands to complete. where ?x? is the worst case delay as defined below 3. assert cke low 4. wait for throttling window to expire 5. just before end of activation throttle window (about 3 clocks before for the cke setup), assert cke high once the branch has been throttled, the memory controller sends a broadcast cke for each dimm command to take the cke low on all dimms of the branch. this command is sent after the proper time has elapsed so that the outstanding transfers complete properly on the drams. when activation throttling starts, cke must not go low on the drams until the last command has completed in the drams. the worst case is an activate immediately followed by a posted cas. a fixed time from the last command is used by the intel 5000x chipset mch corresponding to the worst case delay (x) defined by with a suitable guard band 1 to protect any data loss. the trfc parameter (refresh to activate command delay) is factored into the equation since a refresh could be just underway when the last activate was about to be issued. the ?1.25? scaling factor is to account for the 5:4 gearing ratio required for a fsb frequency of (333 mhz) and fbd/ ddr clock frequency of (266mhz). the default scale factor used on platforms is 1 (fsb (266 mhz) and fbd/ddr clocks (266 mhz)). during the time that cke is low, no dram commands should be sent on the channel. however, non-dram commands such as conf iguration register and sync are required to be sent during this period. when the throttle window is about to expire, a cke command is sent to take all ckes high. this must be done at least 3 clocks before the first command. 1. the worst case round trip delay is expected to be in the 10-20 clock range for a posted cas command and the intel 5000x chipset mch rtl can be microarchitected appropriately. x max worst_case_round_trip_delay m trfc , () = m 1.25 if core to fbd clock ratio is 5:4 1 otherwise ? ? ? =
intel ? 5000x chipset memory controller hub (mch) datasheet 325 functional description 5.3.12.3 cke state near end of activation throttling window if the throttling begins very close to the end of the window, then the assertion of cke low command would be delayed beyond the end of the throttle window. to prevent this occurrence, the memory controller logic does not observe a throttle event in the last few clocks of the window, or assert a cke low command. if the activation throttle is set to begin within y clocks before the end of the window, the memory controller skips the asserting cke low step, where y is x + 6 1 (and the number ?6? is derived from 3 clocks for the cke low to high minimum, plus another 3 clocks for the cke high until first command after the throttling window. 5.3.12.4 refresh handling during throttling the intel 5000x chipset memory controller ensures that refreshes, which are lost during the activation throttle period (possibly up to 2), are made up at the end of the period. double refresh rates to the dimms should be carried out when needed regardless of the setting of the mc.thrmhunt bit. this is particularly important for open loop throttling when the temperature could rise beyond 85?c. 5.3.12.5 throttling parameters for activation throttling. the current throttling parameters for each br anch are stored in the thrmthrt register field defined in section 3.9.3 . all activation throttling pa rameters in the thrmthrt registers are 8-bits wide, an d provide increments of 4 activations per throttle window (1344 clocks). three levels of throttling limits are defined. ? thrtlow: a base throttling level that is applied when the temperature is in the low range (below t low ) and the thrtsts.gblthrt* 2 bit is not set by the global throttling window logic. see section 3.9.4 ? thrtmid: a mid level throttling level that is applied when the temperature is in the middle range (above t low but below t mid ) or the thrsts.gblthrt* bit is set by the global throttling window logic. see section 3.9.5 ? thrthi: the highest level of throttling. when mc.thrmode=1, this level is applied whenever the temperature is above t mid . when mc.thrmode=0, this level is the ceiling of the hunting algorithm of the closed loop throttling. the temperature being above t mid has priority over the global throttling window throttling (the higher throttling level takes precedence). see section 3.9.6 the mc.thrmhunt bit must be enabled for the temperature to have any influence on the throttle parameters. if mc.thrmhunt=0, only the gblthrt bit from the global throttle window, when enabled can change the thrmthrt register field. refer to figure 5-11 and figure 5-12 for the thermal envelopes. 1. intel 5000x chipset mc design needs to adjust the value based on the latest jedec recommendation for cke low to high transition. 2. gblthrt* is an internal combinatorial signal befo re it is latched in the thrsts.gblthrt register field to enable the open loop throttling lo gic to use the latest value of the signal.
functional description 326 intel ? 5000x chipset memory controller hub (mch) datasheet 5.3.12.6 closed loop activation throttling policy individual dimms flag their thermal state in the fb-dimm status return. when the mc.thrmhunt configuration bit is set, me mory reads and writes (summed together) will be regulated on a per-dimm-pair basis according to the following algorithm described in figure 5-13 . note that the intel 5000x chipset mch provides a greater degree of thermal throttling if there is a sudden temperature spike between from t low to t mid by setting the thrmthrt register to thrtmid as a starting point when mc.thrmode=0. once this point is reached, if temperature increased further during the next global window, then thrmthrt re gister will be adjusted by the equation thrmthrt= max(thrmthrt -2, thrt hi). see staircase effect in figure 5-11 . if temperature decreased but is still greater than t mid , then the thrmthrt will retain its figure 5-11. thermal th rottling with thrmhunt=1 figure 5-12. thermal th rottling with thrmhunt=0 temperature thrmthrt thrtlow thrtmid thrthi tlow tmid gblthrt=0 gblthrt=1 thrmode=1 thrmode=0 thrmhunt = 1 temp. increasing temp. decreasing temperature thrmthrt thrtlow thrtmid thrthi tlow tmid gblthrt=0 gblthrt=1 thrmhunt = 0
intel ? 5000x chipset memory controller hub (mch) datasheet 327 functional description last value. this provides some degree of hy steresis control to allow the dimms to cool further before thrmthrt jumps back to a larger number (i.e less throttling) at the junction when the temperature reached t mid . refer to the dotted line in figure 5-11 . this scheme helps in reducing the thermal power by limiting the number of activates. see figure 5-13 for further details. 1. staircase conditioning [thrtctrl.thrmode=0]: this method is employed when thrtctrl.thrmode=0 and temperature crosses above tmid . the thrmthrt registries capped to thrtmid (starting point) and it uses a linearly increasing (less aggressive) throttling algorithm to reduce activations and balance performance and power envelope when temperature rises and falls around tmid point. once thrtmid is reached, if temperature increases further during the next global window, then thrmthrt register will be adjusted by the equation thrmthrt= max(thrmthrt -2, thrthi). this produces the staircase effect as shown in figure 5-10, ?thermal throttling with thrmhunt=1? on page 387. if temperature decreases subsequently but is still grea ter than tmid, then the thrmthrt will retain its last value. this provides some degree of hysteresis control to allow the dimms to cool further before thrmthrt ju mps back to a larger number (i.e less throttling) at the junction when the temperature reached tmid. refer to the dotted line in figure 5-10, ?thermal throttling with thrmhunt=1? on page 387. this scheme helps in reducing the thermal powe r by limiting the number of activates. see figure 5-12, ?thermal throttling activation algorithm? on page 389 for further details. 2. step conditioning (brute force) [t hrtctrl.thrmode=1]: this method is employed when thrtctrl.thrmode=1 and temperature crosses tmid . the thrmthrt register is capped to thrthi and it provides a greater degree of throttling by allowing fewer activates to the memory allowing the dimm to cool down quicker but at the expense of performance. this can be used to control sudden temperature surges that moves th e envelope from below tlow to above tmid. and stays there for a long period. during the global window, the intel 5000p chipset mch will broadcast one configuration write to the dimms amb.update d registers. this write will not be re- played or re-sent. note: a channel fault could drop an amb.updated wr ite. if the temperature increased during the previous global window, but had not actually increased during the current global window, then thrmthrt will un-necessarily decrease. if the temperature had not increased during the previous global window, but had actually increased during the current global window, then thrmtrht will remain unresponsive to the temperature increase for one global throttling window. th e situation will rectify itself in the next global throttling window. 1. if there is a sudden temperature spike be tween from below tlow to above tmid by setting the thrmthrt register to thrtmid as a starting point when thrtctrl.thrmode=0. if temperature rose from above tlow to above tmid, then the thrmthrt will use thrtmid value if thrtctrl.thrmode=0; otherwise it will use thrthi if thrtctrl.thrmode=1. see the right side of table 5-8 on page 390 for the various modes.
functional description 328 intel ? 5000x chipset memory controller hub (mch) datasheet figure 5-13. thermal throttling activation algorithm t h r m t h r t = t h r t l o w (in itialize to b ase-level a ctivations) if (g lo b a l_ t im er e xp ire s) { if (m c .g t w _ m o d e = = 1 ) // c h o o se w in d o w siz e b a sed o n m o d e se ttin g { g lo b a l_ t im e r = 4 * 1 3 4 4 // v a lid a tio n & d e b u g m o d e } e lse { g lobal_tim er = 0.65625*2^25 = 16384*1344 // m ake global throttling w indow an integral m ultiple of the closed loop w indow } if (t h r t c t r l .t h r m h u n t = = 1 ) { fo r (ea c h d im m -p a ir [m ] o n e a ch b ra n ch [n ]) /* m = 0 ..3 , n = 0 ..1 * / { if (te m p er a tu r e o f a n y d im m [i] > = t m id ) /* 0 < = i < = 3 * / { if (t h r t c t r l .t h r m o d e = = 0 ) if (t h r m t h r t > t h r t m id ) { /* t h is w ill ca p th e sta rt p o in t to t h r t m id if th ere is a */ /* sp ik e in th e g b t e m p er a tu r e fro m t lo w to t m id & b e y o n d * / /* p r o v id es b ette r th ro ttlin g a n d co n tr o l * / t h r m t h r t = t h r t m id } e lse /* s ta ir ca se ro ll d o w n m a y h a p p e n fo r su b se q u e n t sa m p lin g s { if (th e te m p era tu re o f a n y d im m w h ich is a b o v e t m id , in cr ea se d ) { t h r m t h r t = m a x (t h r m t h r t - 2 , t h r t h i) } /* o th erw ise r eta in la st t h r m t h r t v a lu e * / } /* en d o f t h r m t h r t > t h r t m id ch eck * / } else { t h r m t h r t = t h r t h i } /* e n d o f t h r m o d e = = 0 ch e c k * / } else if ((te m p e ra tu re o f a n y d im m [i] > = t lo w [i]) & & (te m p er a tu r e o f a ll d im m ?s[i] < t m id [i])) { t h r m t h r t = t h r t m id } else if (tem p er a tu r e o f a ll d im m ?s[i] < t lo w [i])) { if (g b l t h r t = = 1 ) { t h r m t h r t = t h r t m id } else { t h r m t h r t = t h r t l o w } } } } e lse { if (g b l t h r t = = 1 ) { t h r m t h r t = t h r t m id } else { t h r m t h r t = t h r t l o w } } }
intel ? 5000x chipset memory controller hub (mch) datasheet 329 functional description table 5-9. fb_dimm bandwidth as a functi on of closed loop thermal throttling 5.3.12.7 open loop global throttling in the open loop global window throttlin g scheme, the number of activates per dimm pair per branch is counted for a larger time period called the ?global throttling window?. the global throttling window is chos en as an integral multiple of the thermal throttling window of 1344 clocks for main taining a simpler implementation. under normal operating conditions, the gl obal throttling window is 0.65625*2 25 clocks in duration and this translates to 16384*1344 clocks (~66.06 ms) for ddr2667. however, for purposes of validation and debug, the global throttling window can be reduced to a smaller duration, 4*1344 cycles 1 (16.128 s ) for ddr2667 and this is controlled through the gtw_mode register bit defined in section 3.9.1. the global throttling window prevents shorts peaks in bandwidth from causing closed loop activation throttling when there has not been sufficient dram activity over a long period of time to warrant throttling. it is in effect a low pass filter on the closed loop activation throttling. thrmthrt reg value activates % bw allowed bw per dimm gb/s sys bw, 1 dimm/ch sys bw 2 dimm/ch sys bw 4 dimm/ch 0 unlimited 1 4 0.60% 0.03 0.13 0.25 0.51 2 8 1.19% 0.06 0.25 0.51 1.02 3 12 1.79% 0.10 0.38 0.76 1.52 4 16 2.38% 0.13 0.51 1.02 2.03 5 20 2.98% 0.16 0.63 1.27 2.54 6 24 3.57% 0.19 0.76 1.52 3.05 7 28 4.17% 0.22 0.89 1.78 3.56 8 32 4.76% 0.25 1.02 2.03 4.06 12 48 7.14% 0.38 1.52 3.05 6.10 16 64 9.52% 0.51 2.03 4.06 8.13 20 80 11.90% 0.63 2.54 5.08 10.16 24 96 14.29% 0.76 3.05 6.10 12.19 28 112 16.67% 0.89 3.56 7.11 14.22 32 128 19.05% 1.02 4.06 8.13 16.25 36 144 21.43% 1.14 4.57 9.14 18.29 40 160 23.81% 1.27 5.08 10.16 20.32 44 176 26.19% 1.40 5.59 11.17 48 192 28.57% 1.52 6.10 12.19 64 256 38.10% 2.03 8.13 16.25 72 288 42.86% 2.29 9.14 18.29 80 320 47.62% 2.54 10.16 20.32 96 384 57.14% 3.05 12.19 128 512 76.19% 4.06 16.25 144 576 85.71% 4.57 18.29 160 640 95.24% 5.08 20.32 168 672 100.00% 5.33 21.33 1. if mc.gtw_mode=1, the intel 5000x chipset mch will use the 4*1344 cycle duration for the global throttling window.
functional description 330 intel ? 5000x chipset memory controller hub (mch) datasheet during this global throttling window, the numb er of activates is counted for each dimm pair per branch (24-bit counters are requ ired). if the number exceeds the number indicated by the gblact.gblactlm register defined in section 3.9.2 , then the thrtsts[1:0].gblthrt bit is set for the respective branch, causing the activation throttling logic to use the thrtmid register. the thrtsts[1:0].gblthrt will remain active until 16 (or 2) global throttling windows in a row have gone by without any dimm exceeding the gblact. at the end of the 16 (or 2) global throttling windows, if no dimm pair activates exceed the gblact.gblactlm value, then the mc indi cates the end of the period by clearing the thrtsts[1:0].gblthrt register field. if part way through the count of 16 (or 2) global throttling windows, the gblact.gblactlm is again exceeded within one global throttle window, the counter gets reset and it will once again count 16 (or 2) global throttle windows throttling at the thrtmid level. 5.3.12.8 global activation throttling software usage in practice, the throttle settings for thrtmid are likely to be set by software such that the memory controller throttle logic will actu ally prevent the gblact limit from being exceeded and the result will often be that such that thrtlow is used for a global throttle window, at which time, the gblact .gblactlm is exceeded, causing the mc s to use a larger throttling period thrtmid for 16 (or 2) global 1 windows. during each of those global windows, gblact limit is not exceeded, because the throttling will prevent it from being exceeded. after 16 (or 2) global 2 throttling windows, it switches back to thrtlow, and on the next global window gblact is again exceeded, causing another 16 (or 2) windows 2 . hence, we can get a cumulative pattern of 16,1,16,1 (or 2,1,2,1) global 2 throttling windows and this prevents excessive heat dissipation in the fb- dimms by prolonging the throttle period. note: it should be mentioned that the open an d closed loop throttling control policies implemented on the intel 5000x chipset mc h uses the internal core clocks for the calculating the windows and not the ddr clocks. thus any software/bios should take this into account for manipulating the thrmthrt registers when dealing with different fb-dimm technologies and speeds. 5.3.12.9 dynamic update of thermal throttling registers in general, the intel 5000p chipset regist ers should not updated dynamically during runtime as it may interfere with the internal state machines not designed exclusively for such changes and could result in a system hang/lock up. this requirement is relaxed (subject to validation) for the intel 5000p chipset thermal throttling registers where it is desirable for bios or special oem software in bmc to exercise dynamic control on throttling for open/closed loop algorithm implementation. the following examples are some of the potential areas of this usage model where dynamic change is needed to balance performance and acoustic levels in the system fan control for cpu temperature related system acoustics or other bmc related operations. limit hacker activity by increasing memory throttling via throttle register updates to condition the system based on some event (excessive bandwidth or cpu activity) ? fan failure/breakdown. when this occurs, temperature conditioning can be provided by reducing the activity level in the dimms to a certain threshold until the failed fan can be repaired by the techni cian and service restored to normalcy. 1. the 2 window global throttling count will be chosen if mc.gtw_mode=1.
intel ? 5000x chipset memory controller hub (mch) datasheet 331 functional description 5.3.12.10 general software usage assumptions under normal circumstances, it is expected th at there is no change of throttling values once it is configured by bios during bo ot. the external fan control and the bios settings of the oem via bmc would ensure adequate cooling and maintain the dimms within the prescribed tolerance limits of the tdp. however, situations such as thermal virus or fan fail down condition might warrant the bios/sw to take preemptive action in adjusting the throttling to say 40-70% of th e normal mode before it is cleared. this means that changes to throttling registers can happen at random intervals (infrequent) and the platform should be able to tolerate any transients changes that may result when the intel 5000p chipset is updated with the new throttle values. these requirements are captured below. 5.3.12.11 dynamic change operation re quirements for open loop thermal thottling (oltt) the intel 5000p chipset memory throttle control register affected by oltt include thrtmid (t2), thrtlow (t1), gblact, and the thrtctrl.thrmhunt field. (thrmhunt=0 selects the open loop mode). each update to the above mentioned throttle register takes approximately 40 core clocks in the configuration ring to complete. configuration register updates for throttling should be spaced out at approximately 80 core cycles apart. (2x guard band) only one cfc/cf8 or mmcfg configuration transaction is allowed at a time in the system. when the number of activates exceed the gblact.gblactlm in a global throttling window, oltt is entered and gblthrt is set by the intel 5000p chipset for 16 consecutive global throttling windows (irrespective of the new parameters) as described in section 5.3.12.7 . note that oltt is not history-based algorithm. hence if software assigns new values to thrtlow or thrmid values at some point in time, the mc cluster will update the registers and use the new values for limiting the activates immediately via thrmthrt register for 16 co nsecutive global throttling windows. see also figure 5-13 . software can update the throttling registers as frequently as it desires provided it maintains the minimum spacing for the conf iguration writes and follows the other guidelines as described above. it is also software?s responsibility for the fallout/ transient effect of the thermal cont rol algorithm during such updates. 5.3.12.12 dynamic change operation re quirements for closed loop thermal thottling (cltt) in addition to all the conditions /requirements as stipulated in section 5.3.12.11 , the closed loop throttling which uses gb temperature feedback to adjust the throttling levels requires the following: ? intel 5000p chipset registers that ar e affected by dynamic updated include thrtmid (t2), thrtlow (t1), thrthi and thrtctrl.thrmhunt. (thrmhunt=1 selects the closed loop mode) ? ?when temperature crosses t mid , the cltt switched to either the staircase function (if thrmctrl.thrtmode=0) or the single step function (thrmctrl.thrmode=1) as depicted in the right side of figure 5-11 . see also figure 5-13 . note that cltt is not history-based algorithm except in the staircase mode which uses the old value. in this case, the staircase function that always decrements the old value of
functional description 332 intel ? 5000x chipset memory controller hub (mch) datasheet thrmthrt by 2. by design thrmthrt can never be below thrthi. if the new thrthi is greater than thrmthrt, then the algorithm will reset thrmthrt to thrthi & the staircase function can no longer be used since the bottom (aka ceiling) of thrthi has already been reached as defined by the following equation extracted from figure 5-13 . thrmthrt = max(thrm thrt - 2, thrthi) 5.3.12.13 disabling closed /open loop throttling the following registers in the intel 5000p chip set can be initialized to disable throttling (open/closed) if software desires to turn off throttling. ? thrtctrl.thrmhiunt = 0 /* this forces the intel 5000p chipset to ignore temperature for closed loop */ ? thrthi.thrhilm = 0 (or 168d) ? thrthi.thrmidlm = 0 (or 168d) ? thrtlow.thrlowlm = 0 (or 168d) ? gblact.blactlm = 0 (or 168d) /*above changes force open loop throttling to be off */ table 5-10. global activation throttling bw allocation as a function of gblactlm for a 16384**1344 window with mc.gtw_mode=0 (normal) gblact. gblactlm # of activates % bw allowed bw per dimm gb/s sys bw, 1 dimm/ch sys bw 2 dimm/ch sys bw 4 dimm/ch 0 unlimited 1 65536 0.60% 0.03 0.13 0.25 0.51 2 131072 1.19% 0.06 0.25 0.51 1.02 3 196608 1.79% 0.10 0.38 0.76 1.52 4 262144 2.38% 0.13 0.51 1.02 2.03 5 327680 2.98% 0.16 0.63 1.27 2.54 6 393216 3.57% 0.19 0.76 1.52 3.05 7 458752 4.17% 0.22 0.89 1.78 3.56 8 524288 4.76% 0.25 1.02 2.03 4.06 12 786432 7.14% 0.38 1.52 3.05 6.10 16 1048576 9.52% 0.51 2.03 4.06 8.13 20 1310720 11.90% 0.63 2.54 5.08 10.16 24 1572864 14.29% 0.76 3.05 6.10 12.19 28 1835008 16.67% 0.89 3.56 7.11 14.22 32 2097152 19.05% 1.02 4.06 8.13 16.25 36 2359296 21.43% 1.14 4.57 9.14 18.29 40 2621440 23.81% 1.27 5.08 10.16 20.32 44 2883584 26.19% 1.40 5.59 11.17 48 3145728 28.57% 1.52 6.10 12.19 64 4194304 38.10% 2.03 8.13 16.25 72 4718592 42.86% 2.29 9.14 18.29 80 5242880 47.62% 2.54 10.16 20.32 96 6291456 57.14% 3.05 12.19 128 8388608 76.19% 4.06 16.25 144 9437184 85.71% 4.57 18.29 160 10485760 95.24% 5.08 20.32 168 11010048 100.00% 5.33 21.33
intel ? 5000x chipset memory controller hub (mch) datasheet 333 functional description 5.3.13 electrical throttling electrical throttling is a mechanism that limits the number of activates (burstiness) within a very short time interval that would otherwise cause silent data corruption on the dimms. electrical throttling is enabled by setting the mtr.ethr ottle bit defined in section 3.9.23.7 . these bits occur on a per dimm pair basis per branch as to whether electrical throttling should be used. it is assumed that both ranks within a dimm would be the same technology, and therefore does need not separate enable bits. the per rank electrical throttling for fb-dimm is 4 activates per 37.5ns window (jedec consensus) and is summarized in ta b l e 5 - 1 1 for various dimm technologies. the mc.ethrot configuration register field limits the number of activations per sliding electrical throttle window. the memory co ntroller logic can implement the sliding electrical throttle window with a 20-bit shift register per rank in each dimm pair per branch. this register records for the last 20 clocks, whether an activate was issued or not to that rank. the number of activates can then be summed up from the state of the shift register and compared with the respective limit as shown in figure 5-11 . if the limit is reached, then further activates to the rank are blocked until the count falls below the limit. the electrical throttling logic in the mc masks off the end bits for the dimm technologies that requ ire fewer clocks. as an example, if the dimm technology used is ddr667, then it can allow 4 activates within the last 13 clocks, the remaining 7 bits are masked (forced to 0) so they do not prevent activates. 5.4 behavior on overtemp state in amb overtemperature occurring in an amb may lead to data corruption in the . ? if ei is received by due to overtemp detection in one of the ambs, will capture random data that most likely will be inte rpreted as having a crc or uncorrectable ecc error causing the link to go into a fast reset loop without data corruption. ? if the ei is interpreted as having both good crc and good ecc, this could cause data corruption until a bad crc/ecc frame is detected and the link enters the fast reset loop. note: an all 0 frame fits this case of good crc and ecc. this is just as unlikely as any other random frame contents when interpreting ei. table 5-11. electrical throttle windo w as a function of dimm technology dimm modes intel 5000p chipset mch core: fb-dimm clock ratio electrical throttle window 1 (in core clocks per rank per dimm pair per branch) notes: 1. maximum 4 activates per rank is allowed within the window. b. this is not a supported tech nology/nor a por for intel 5000p ch ipset mch and is tabulated for information/illustrative purposes only. ddr533 1:1 10 5:4 13 ddr667 1:1 13 4:5 13 (conservative) ddr800 b all 15 conservative (safe mode) all 20
functional description 334 intel ? 5000x chipset memory controller hub (mch) datasheet 5.5 interrupts the intel 5000x chipset supports both th e xapic and traditional 8259 methods of interrupt delivery. i/o interrupts and inter processor interrupts (ipis) appear as write or interrupt transactions in the system and are delivered to the target processor via the processor bus. this chipset does not support the three-wire sideband bus (the apic bus) that is used by pentium ? and pentium ? pro processors. xapic interrupts that are generated from i/ o will need to go through an i/o(x)apic device unless they support message signalle d interrupts (msi). in this document, i/ o(x)apic is an interrupt controller that is found in the intel 631xesb/632xesb i/o controller hub component of the chipset. the legacy 8259 functionality is embedde d in the intel 631xesb/632xesb i/o controller hub component. the intel 5000x ch ipset will support inband 8259 interrupt messages from pci express devices for boot. the chipset also supports the processor generated ?interrupt acknowledge? (for lega cy 8259 interrupts), and ?end-of-interrupt? transactions (xapic). routing and delivery of interrupt messages and special transactions are described in this section. 5.6 xapic interrupt message delivery the xapic interrupt architectures deliver interrupts to the target processor core via interrupt messages presented on the front side bus. this section describes how messages are routed and delivered in a inte l 5000x chipset system, this description includes interrupt redirection. interrupts can originate from i/o(x)apic devices or processors in the system. interrupts generated by i/o(x)apic devices occu r in the form of writes with a specific address encoding. interrupts generated by th e processor appear on the processor bus as transactions with a similar address encoding, and a specific encoding on the reqa/ reqb signals (reqa=01001, reqb=11100). the xapic architecture provides for lowest priority delivery, through interrupt redirection by the chipset. if the redirectab le hint bit is set in the xapic message, the chipset may redirect the interrupt to anot her processor. note that redirection of interrupts can be to any processor on either processor bus id and can be applied to both i/o interrupts and ipis. the redirection can be performed in logical and physical destination modes. for more details on the interrupt redirection algorithm, see section 5.6.3 . 5.6.1 xapic interrupt message format interrupt messages have an address of 0x000_feez_zzzy. the 16-bit ?zzzz? field (destination field) determines the target to which the interrupt is being sent. the y field is mapped to a3 (redirectable interrupt) an d a2 (destination mode). figure 5-18 shows the address definition in ia32 systems (xapic). for each interrupt there is only one data transfer. the data associated with the inte rrupt message specifies the interrupt vector, destination mode, delivery status, and tr igger mode. the transaction type on the processor bus is a request type of, interrupt transaction. the transaction type on the pci express and esi buses is a write. the ad dress definition of figure 5-18 applies to both the pci express bus and processor bus. note that the current assumption is that we can?t make any conclusions about which fsb an interrupt id is associated with. at power-up, there is an association for certain types of interrupts, but the current
intel ? 5000x chipset memory controller hub (mch) datasheet 335 functional description assumption is that the os can reprogram the interrupt id?s. therefore, for directed interrupts, the intel 5000x chipset mch will en sure that each interrupt is seen on both fsbs. the data fields of an interrupt transact ion are defined by the processor and xapic specifications. it is included here for reference. 5.6.2 xapic destination modes the destination mode refers to how the proce ssor interprets the destination field of the interrupt message. there are two types of destination modes; physical destination mode, and logical destination mode. the destination mode is selected by a[2] in pci express and ab[5] on the processor bus. 5.6.2.1 physical destination mode (xapic) in physical mode, the apic id is 8 bits, supporting up to 255 agents. each processor has a local apic id register where the lower 5 bits are initialized by hardware (cluster id=id[4:3], bus agent id=id[2:1], thread id=id[0]). the upper 3 bits default to 0?s at system reset. these values can be modified by software. the cluster id is set by address bits a[12:11] during reset. by de fault, the intel 5000p chipset will drive a[12:11] to ?00 for fsb0, and ?01 for fsb1. the value driven on bit a[12] during reset can be modified through the poc register on the intel 5000x chipset mch. the intel 5000p chipset will not rely on the clus ter id or any other fields in the apic id to route interrupts. the intel 5000p chipset w ill ensure the interrupt is seen on both busses and the processor with the matchi ng apic id will claim the interrupt. physical destination mode interrupts can be directed, broadcast, or redirected. an xapic message with a destination field of all 1?s denotes a broadcast to all. in a directed physical mode message the agen t claims the interrupt if the upper 8 bits of the destination field (did field) matches the local apic id of the processor or the interrupt is a broadcast interrupt. redirected interrupts are redirected and co nverted to a directed interrupt by the chipset as described in section 5.6.3.2. figure 5-14. xapic address encoding 0xfee did edid (not used) did : 8-bit destination id. software may assign each id to any value . edid: not used, is a reserved field in the processor ehs. rh : redirection bit (0=dir ected, 1=redirectable) dm : destination mode (0=physical, 1=logical) * : pci/pci express transaction encoding. copied to ab5 on processor bus 31 20 19 12 11 2* 0 3 4 rh dm rsvd table 5-12. xapic data encoding d[63:16] d[15] d[14] d[13:11] d[10:8] d[7:0] x trigger mode delivery status x delivery mode vector
functional description 336 intel ? 5000x chipset memory controller hub (mch) datasheet 5.6.2.2 logical destination mode (xapic) in logical destination mode, destinations are specified using an 8 bit logical id field. each processor contains a register called the logical destination register (ldr) that holds this 8-bit logical id. interpretation of the ldr is determined by the contents of the processor?s destination format register (dfr). processors used with the intel 5000x chipset mch operate in flat mode. logical destination mode interrupts can be directed (fixed delivery), redirectable (lowes t priority delivery), or broadcast. the ldr is initialized to flat mode (0) at reset an d is programmed by firmware. the intel 5000p chipset also has an equivalent bit in the ex ternal task priority register (xtpr0) to indicate flat or cluster mode. this is set to flat mode by reset and must not be changed, since the processors used with intel 5000x chipset operate in flat mode only. the 8-bit logical id is compared to the 8-bit destination field of the incoming interrupt message. if there is a bit-wise match, then the local xapic is selected as a destination of the interrupt. each bit position in the destination field corresponds to an individual local xapic unit. the flat model supports up to 8 agents in the system. an xapic message where the did (destination field) is all 1?s is a broadcast interrupt. 5.6.2.3 xapic interrupt routing interrupt messages that originate from i/o(x)apic devices or from processing nodes must be routed and delivered to the target agents in the system. in general xapic messages are delivered to both processor busses because there is no reliable way to determine the destination processor of th e message from the destination field. interrupts originating from i/o can be generated from a pci agent using msi interrupts, or by an interrupt controller on a bridge chip such as the intel 631xesb/ 632xesb i/o controller hub. table 5-13 shows the routing rules used for routing xapic messages in an intel 5000x chipset-based platform. this table is valid for both broadcast and non-broadcast interrupts. 5.6.3 interrupt redirection the xapic architecture provides for lowest priority delivery through interrupt redirection by the intel 5000p chipset. if the redirectable ?hint bit? is set in the xapic message, the chipset may redirect the inte rrupt to another agent. redirection of interrupts can be applied to both i/o interrupts and ipis. 5.6.3.1 xtpr registers to accomplish redirection, the intel 5000x chipset mch implements a set of external task priority registers (xtprs), one for each logical processor (a thread is considered a logical processor). each register contains the following fields: 1. agent priority (task priority) 2. apic enable bit (tpr enable) table 5-13. intel 5000x chipset xapic interrupt message routing and delivery source type routing i/o physical or logical directed deliver to all processor busses as an interrupt transaction. processor physical or logical directed deliver to other processor bus as an interrupt transaction. any source logical, redirectable physical, redirectable redirection (see ?interrupt redirection? on page 352) is performed by the intel 5000x chipset mch and is de livered to both fsbs.
intel ? 5000x chipset memory controller hub (mch) datasheet 337 functional description 3. logical apic id (logid) 4. processor physical apic id (physid) the xtpr registers are modified by a front side bus xtpr_update transaction. in addition, the xtpr registers can be modified by software. in addition, xtpr0 also contains a bit for global cluster mode bit used in redirection of logical destination mode messages. this bit indicates to the intel 5000x chipset mch that destination field of the message is ?flat? or physical (note that the xapic message indicates whether the destination mode is physical or logical). the default logical mode at reset is ?flat? and must not be changed to ?cluster? mode. cluster mode is not supported by the intel ? 5000x chipset. more details on the intel 5000p chipset xtpr registers are described in the xtpr register definition in section 3.8.6.3 . the xtpr special cycle must guarantee that the xtpr register is updated for interrupt redirection in a consistent manner. for reproducibility, there needs to be an internal serialization point after whic h subsequent interrupts will be redirected based on the updated xtpr value. 5.6.3.2 redirection algorithm redirection is performed if an interrupt redirection hint bit (a[3]) is set. this is the algorithm used in determining the processor that the interrupt will be redirected to. 1. if a[3] =1, then this is a redirection (also known as ?lowest priority?) interrupt request. proceed to the next step. 2. flat: if destination mode = 1 (a2 for i/o, ab5 for ipis) is disabled (0) in the xtpr, then this is flat-logical destination mode. (otherwise, proceed to the next step). to select the arbitration pool, for each xtpr register: note: cluster mode is not supported and should always be disabled. if (a[19:12] (did) and xtpr[n].logid[7:0]) > 0h and xtpr[n].tpren =1 then xtpr[n] is included in the arbitration pool. 3. physical: if destination mode = 0 (a2 for i/o, ab5 for ipis), then this is physical destination mode. all enabled xtpr?s are included in the arbitration pool. 4. if there are no xtpr?s in the arbitration pool, then forward to fsb with a[3]=0, but otherwise ?without modification?. otherwise, continue to the next step. 5. xtprs in the pool are categorized into 4 priority buckets depending on the priority. the priority bucket levels are defined by register bits bucket(0-2)_lim in the redirctl register. if (0 <= xtpr.priority < bucket0_ lim) then priority bucket = 0 if (bucket0_lim <= xtpr .priority < bucket1_lim) then priority bucket = 1 if (bucket1_lim <= xtpr .priority < bucket2_lim) then priority bucket = 2 if (bucket2_lim <= xt pr.priority < 16) then priority bucket = 3 6. all xtpr?s in the arbitration pool are compared. the xtpr register with the lowest priority bucket value (0=lowest, 3=highest) is the ?winner?. 7. if more than one xtpr register in the ar bitration pool has the same lowest priority bucket value, then lru arbitration logic will pick an xtpr that was not recently picked.
functional description 338 intel ? 5000x chipset memory controller hub (mch) datasheet 8. the ?winning? xtpr register provides the values to be substituted in the aa[19:12]# field of the fsb interrupt me ssage transaction driven by the intel 5000p chipset. a[19:12]# is replaced by the logical or physical id, depending on the type of interrupt. the interrupt is dr iven onto both processor buses with the redirection hint bit disabled (a3). 5.6.4 eoi for xpf platforms using xapic, the eoi is a specially encoded processor bus transaction with the interrupt vector attached. since the eoi is not directed, the intel 5000p chipset will broadcast the eoi transact ion to all i/o(x)apic?s. the intel 5000x chipset mch.pexctrl.dis_apic_eoi bit per pci express port can be used to determine whether an eoi needs to be sent to a specific pci express port. eoi usage is further described in section 5.6.4 . note: the intel 5000x chipset mch will translat e the eoi on the fsb into an eoi tlp message type on the pci express/esi ports. 5.7 i/o interrupts for i/o interrupts from the intel 631xesb/632xesb i/o controller hub components receive interrupts with either dedicated interru pt pins or with writes to the integrated redirection table. the i/oxapic controller integrated within these components turns these interrupts into writes destined for the processor bus with a specific address. interrupts triggered from an i/o device can be triggered with either a dedicated interrupt pin or through an inbound write message from the pci express bus (msi). note that if the interrupt is triggered by a dedicated pin, the i/oxapic controller in the i/o bridge (intel? 6700pxh 64 bit pci hub or ich6 or esb) turns this into an inbound write. on the processor bus, the interrupt is converted to an inte rrupt request. other than a special interrupt encoding, the proce ssor bus interrupt follows the same format as discussed in section 5.6.1 . therefore, to all components other than the intel? 6700pxh 64 bit pci hub, ich6 or esb, and the processor, an interrupt is an inbound write following the format mentioned in section 5.6.1 . intel 5000x chipset will not write combine or cache the apic address space. i/o(x)apic?s can be configured through tw o mechanisms. the traditional mechanism is the hard coded fec0_0000 to fecf_ffff range is used to communicate with the ioapic controllers in the intel? 6 700pxh 64 bit pci hub, ich6 or esb. the second method is to use the standard mmio range to communicate to the intel 6700pxh 64 bit pci hub. to accomplish this, the intel? 6700pxh 64 bit pci hub.mbar and/or intel 6700pxh 64 bit pci hub.xapic_base_address_reg must be programmed within the pci express device mmio region. 5.7.1 ordering handling interrupts as inbound writes has inhe rent advantages. first, there is no need for the additional apic bus resulting in extra pins and board routing concerns. second, with an out-of-band apic bus, there are or dering concerns. any interrupt needs to be ordered correctly and all prior inbound writes must get flushed ahead of the interrupt. the pci local bus specification , revision 2.2attempts to address this by requiring all interrupt routines to first read the pci interrupt register. since pci read completions are required to push all writes ahead of it, then all writes prior to the interrupt are guaranteed to be flushed. however, this assumes that all drivers perform this read.
intel ? 5000x chipset memory controller hub (mch) datasheet 339 functional description 5.7.2 hardware irq ioxapic interrupts dedicated pin interrupts may be edge or level triggered. they are routed to irq pins on ioxapic device such as the intel 6700pxh 64 bit pci hub, or intel 631xesb/632xesb i/o controller hub. the ioxapic device will convert the interrupt into either an xapic or 8259 interrupt. for level-triggered interrupts, the i/oxapic will generate an interrupt message when any of the interrupt lines coming into it be come asserted. the processor will handle the interrupt and eventually write to the initiating device that the inte rrupt is complete. the device will deassert the interrupt line to the i/oxapic. after the interrupt has been serviced, the processor sends an eoi command to inform the i/oxapic that the interrupt has been serviced. since the eoi is not directed, the intel 5000p chipset will broadcast the eoi transaction to all i/o(x)apic?s. if the original i/o(x)apic sees the interrupt is still asserted, it knows there?s another interrupt (shared interrupts) and will send another interrupt message. for edge-triggered interrupts, the flow is th e same except that there is no eoi message indicating that the interrupt is complete. since the interrupt is issued whenever an edge is detected, eois are not necessary. while not recommended, agents can share in terrupts to better utilize each interrupt (implying level-triggered inte rrupts). due to ordering constraints, agents can not use an interrupt controller that resides on a diff erent pci bus. therefore either only agents on the same pci bus can share interrupts, or the driver must follow the pci requirement that interrupt routines must first read the pci interrupt register the intel 5000x chipset mch supports the in ta (interrupt acknowledge) special bus cycle for legacy 8259 support. these are rout ed to the compatibility ich6 or esb in the system. the inta will return data that provides the interrupt vector. 5.7.3 message signalled interrupts a second mechanism for devices to send interrupts is to issue the message signalled interrupt (msi) introduced in the pci local bus specification , revision 2.2. this appears as a 1 dword write on the pci/pci-x/pci express bus. with pci devices, there are tw o types of msis. one type is where a pci device issues the inbound write to the interrupt range. th e other type of msi is where a pci device issues an inbound write to the upstream ap ic controller (for example, in the intel 6700pxh 64 bit pci hub) where the apic contro ller converts it into an inbound write to the interrupt range. the second type of ms i can be used in the event the os doesn?t support msis, but the bios does. in either wa y, the interrupt will appear as an inbound write to the intel 5000p chipset over the pci express ports. msi is expected to be supported by th e operating systems when the intel 5000x chipset mch is available. an intel 5000x ch ipset platform will also feature a backup interrupt mechanism in the event that there is a short period of time when msi is not available. this is described in the next section. 5.7.4 non-msi interrupts - ?fake msi? for interrupts coming through the intel 6700pxh 64 bit pci hub, and intel 631xesb/ 632xesb i/o controller hub components, thei r apic controller will convert interrupts into inbound writes, so inbo und interrupts will ap pear in the same format as an msi.
functional description 340 intel ? 5000x chipset memory controller hub (mch) datasheet for interrupts that are not coming through an ap ic controller, it is still required that the interrupt appear as an msi-like interrupt. if the os does not yet support msi, the pci express device can be programmed by the bi os to issue inbound msi interrupts to an ioxapic in the system. the safest ioxapi c to choose would be the intel 631xesb/ 632xesb i/o controller hub since it is alwa ys present in a system. although the intel 5000x chipset supports the pci express ?assert_int? and ?deassert_int? packets for boot, the performance is not optimal and is not recommended for run time interrupts. in this method, pci express devices are programmed to enable msi functionality, and given a write path directly to the pin assertion register in a selected ioxapic already present in the platform. the ioxapic will ge nerate an interrupt message in response, thus providing equivalent functionality to a virtual (edge-triggered) wire between the pci express endpoint and the i/oxapic. this mechanism is the same as is used in longhorn* (xyzzy). all pci express devices are strictly required to support msi. when msi is enabled, pci express devices generate a memory transaction with an address equal to the i/ oxapic_mem_bar + 20 and a 32-bit data equal to the interrupt vector number corresponding to the device. this information is stored in the device's msi address and data registers, and would be initialized by the system firmware (bios) prior to booting a non-msi aware operating system. (with the theory that an msi aware o/s would then over-write the registers to provide in terrupt message delivery directly from the endpoint to the cpu complex.) the pci express memory write transaction propagates to the intel 5000p chipset and is redirected down the appropriate pci express port following the intel 5000p chipset ioapic address mapping definition. the ioapic memory space ranges are fixed and cannot be relocated by the os. the assert message is indistinguishable from a memory write transaction, and is forwarded to the destination i/oxapic, which will then create an upstream apic interrupt message in the form of an inbound memory write. the write nature of the message ?pushes? all app licable pre-interrupt traffic through to the intel 5000p chipset core, and the intel 5000p chipset core architecture guarantees that the subsequent apic message cannot pass any posted data already within the intel 5000p chipset. 5.8 interprocessor interrupts (ipis) ? previous ia-32 processors use ipis after reset to select the boot strap processor (bsp). recent xpf processors do not us e ipis to select the bsp. a hardware arbitration mechanism is used instead. ? ia32 processors use startup ipis (sipis) to wake up sleeping application processors (non boot strap processors) that are in ?wait for sipi state?. these are broadcast interrupts. ? interrupts transactions are claimed with trdy# and no-data response. ? for directed xapic (a[3] = 0) interrupt s, the intel 5000p chipset completes the interrupt normally and forwards the interrupt to the other bus. ? for redirectable xapic interrupts, th e intel 5000p chipset will generate an interrupt message to both processor buses intel 5000p chipset with a[3] (redirectable hint bit) set to 0. this message will contain a processor id based on the redirection algorithm. ? for directed xapic broadcast interrupts (destination id = 0xff), the intel 5000p chipset will forward the broadcast interrupt to the other processor bus. ? interrupts are not deferred.
intel ? 5000x chipset memory controller hub (mch) datasheet 341 functional description ? since xapic directed interrupts (a[3] = 0) cannot be retried, they must be accepted. if the intel 5000p chipset canno t accept the interrupt, then it must assert bpri# until resources are available. 5.8.0.1 ipi ordering in a system, there are ordering requirem ents between ipis and other previous coherent and non-coherent accesses. the way the ordering is maintained is that it is expected that the chipset will defer the pr evious ordered access. the chipset will not complete the transaction until the write is ?p osted? or the read data is delivered. since the processor will not issue an ordered ip i until the previous transaction has been completed, ordering is automatically maintained. an example where the ordering must be maintained is if a processor writes data to memory and issues an ipi to indicate the data has been written, subsequent reads to the data (after the ipi) must be the upda ted values. (producer consumer). for this example, assuming cacheable memory, the chipset defers the bil/bril (read for ownership). only after all other processor caches have been invalidated, and the deferred reply is returned (where the cache will be written) will the subsequent ipi be issued. there are no ordering requirements between ipis. there are no ordering requirements between ipis and subsequent request. the ipis are claimed on the fsb (front side bus) and are not deferred. therefore, software must not rely on the ordered delivery between the ipi and subsequent transactions. if ordering is needed, it must protect any subsequent coherent and non-coherent accesses from the effects of a previous ipi using synchronization primitives. also, software must not rely on ordered delivery of an ipi with respect to other ipi from the same processor to any target processor.
functional description 342 intel ? 5000x chipset memory controller hub (mch) datasheet 5.9 chipset generated interrupts the intel 5000x chipset mch can trigger interrupts for chipset errors and for pci express. for these events, the chipset can be programmed to assert pins that the system can route to an apic controller. the interrupts generated by the chipset are still being defined. the following is a preliminary list of interrupts that can be generated. 1. chipset error - intel 5000x chipset mch asserts appropriate err pin, depending on severity. this can be routed by the system to generate an interrupt at an interrupt controller. (intel 5000x chipset mch pins err[2:0], mcerr, intel 631xesb/632xesb i/o controller hub reset). the err[0] pin denotes a correctable and recoverable error. the err[1] pin denotes an uncorrectable error from intel 5000x chipset mch. the err[2] pin denote s a fatal error output from intel 5000x chipset mch. 2. pci express error - intel 5000x chipse t mch asserts appropriate err pin, depending on severity. this can be routed by the system to generate an interrupt. a. the intel 5000x chipset mch can receive error indications from the pci express ports. these are in the form of inbo und err_cor/unc/fatal messages. intel 5000x chipset mch will assert the approp riate err signal just like any internal intel 5000x chipset mch error as described in the ras chapter. 3. pci express hot-plug - intel 5000x chipset mch send assert_hpgpe (deassert_hpgpe) or generates an msi or a legacy interrupt on behalf of a pci express hot-plug event. a. intel 5000x chipset mch generated ho t-plug event such as presdet change, attn button, mrl sensor changed, power fault, and so forth. each of these events have a corresponding bit in the pci express hot-plug registers (attention button, power indicator, power controller, presence detect, mrl sensor, port capabilities/slot registers). this will generate an interrupt via the assert_hpgpe, intx, or an msi. refer to figure 5-15 for the hotplug interrupt flow priority. b. pci express hot-plug event from downstream. ? gpe message: upon receipt of a assert _gpe message from pci express, intel 5000x chipset mch will send assert_gpe si gnal to the esi port. to generate an sci (acpi), this signal will be routed to the intel? 631xesb/632xesb i/o controller hub appropriate gpio pin to match the gpe0_en register settings. when the hot-plug event has been se rviced, intel 5000x chipset mch will receive a deassert_gpe message. at this point the intel 5000x chipset mch can deassert_gpe message to esi. there needs to be a tracking bit per pci express port to keep track of assert/d eassert_gpe pairs. these tracking bits should be or?d together to determ ine whether to send the assert_gpe/ deassert_gpe message. when intel 5000x chipset mch receives a matching deassert_gpe message for that port, it will clear the corresponding tracking bit. when all the tracking bits are cleared, the intel 5000x chipset mch will send a deassert_gpe message to the esi port. ? sideband signals: some systems may choose to connect the interrupt via sideband signals directly to the intel 631xesb/632xesb i/o controller hub. no action is required from the intel 5000x chipset mch.
intel ? 5000x chipset memory controller hub (mch) datasheet 343 functional description 4. pci hot-plug - chipset will receive an assert/deassert gpe message from the pci express port when a pci hot-plug ev ent is happening. assert/deassert gpe messages should be treated the same as assert/deassert gpe messages for pci express hot-plug. (keep track of assert/deassert gpe messages from each port and send assert_gpe, deassert_gpe message to esi appropriately) 5. pci express power management - pci express sends a pme message. chipset sends assert_pmegpe to esi port when a power management event is detected. a. upon receipt of the pme message, in tel 5000x chipset mch will set the pexrtsts.pmestatus bit corresponding to that port and send assert_pmegpe to esi port to generate the interrupt. (a ssert_pmegpe should be sent if one or more of the pmestatus bits are set and enabled.) to generate an sci (acpi), this message will be used by the intel 631xesb/632xesb i/o controller hub to drive appropriate pin. when software has completed servicing the power figure 5-15. pci express hot-plug interrupt flow n pexslotctrl[x]. hpinten = 1? y sw polls status (pexctrl.hpgpe en == 1) n sends msi per msiar and msidr pexhpint intel? 5000p chipset sends desassert_intx message via dmi when the respective bits of pexslotsts str cleared (wired- or) y intel? 5000p chipset sends assert_hpgpe message via dmi n hpgpeen msien output 1 x assert_hpgpe 0 1 msi 0 0 assert_intx intx disable x x 0 0 0 1 -- hpinten x 1 1 1 0 0 x x -- pexcmd[x].intx disable == 1? y (msictrl[x]. msien == 1) ? y n intel? 5000p chipset sends assert_intx message via dmi per intp intel? 5000p chipset sends desassert_hpgp e message via dmi when the respective bits of pexslotsts str cleared (wired- or) intel? 5000p chipset
functional description 344 intel ? 5000x chipset memory controller hub (mch) datasheet management event, it will clear the pexrtsts.pmestatus bit (by writing 1), at which point the intel 5000x chipset mch can send deassert_pmegpe to esi port. the following table summarizes the different types of chipset generated interrupts that were discussed. although the interrupt an d sw mechanism is flexible and can be changed depending on how the system is h ooked up, for reference this table also describes what sw mechanism is expected to be used. 5.9.1 intel 5000x chipse t generation of msis the intel 5000x chipset mch generates msis on behalf of pci express hot-plug events if intel 5000p chipset mch.msictrl.msien is set. refer to figure 5-15 . the intel 5000x chipset mch will interp ret pci express hot-plug events and generate an msi interrupt based on intel 5000p chipset mch.msiar and intel 5000p chipset mch.msidr registers. when the intel 5000x chipset mch detects any pci express hot-plug event, it will generate an interrupt transaction to both processor buses. the address will be the value in intel 5000p ch ipset mch.msiar. the data value will be the value in msidr. internal to the intel 5000x ch ipset mch, the msi can be considered an inbound write to address msiar with data value of msid r, and can be handled the same as other inbound writes that are msis or apic interrupts. 5.9.1.1 msi ordering in intel 5000x chipset mch ordering issues on internally generated msis could manifest in the intel 5000x chipset mch if software/device drivers rely on ce rtain usage models, for example, interrupt rebalancing, hot-plug to flush them. the producer-consumer violation may happen, if a table 5-14. chipset generated interrupts source signalling mechanism intel 5000x chipset mch signal method expected sw mechanism chipset error intel 5000x chipset mch registers err[2:0], mcerr, intel 631xesb/632xesb i/o controller hub reset any pci express error pci express err_cor/unc/fatal message err[2:0], mcerr, intel 631xesb/632xesb i/o controller hub reset any pci express hp (presdet chg, attn button, and so forth.) intel 5000x chipset mch registers for card-these registers are set via the vpp/sm bus interface. for module- these registers are set by inband hot-plug messages. msi or assert_intx, deassert_intx, or assert_hpgpe, deassert_hpgpe sci->acpi or msi pci express hp from downstream device msi msi interrupt (processor bus) msi pci express hp from downstream device (non-native, intel part) pci express assert/deassert gpe assert_gpe, deassert_gpe to esi sci->acpi pci express hp from downstream device (non-native, non-intel part) sideband signals directly to intel 631xesb/632xesb i/o controller hub n/a sci->acpi downstream pci hot- plug pci express assert/deassert gpe assert_gpe, deassert_gpe to esi sci->acpi power management event (pme) pci express pm_pme message assert_pmegpe, deassert_pmegpe to esi sci->acpi
intel ? 5000x chipset memory controller hub (mch) datasheet 345 functional description root port has posted an msi write interna lly in the mch and th e software wants to ?flush? all msi writes from the root port that is, guarantee that all the msi writes pending in the mch from the root port have been delivered to the local apic in the processor. to accomplish this flush operatio n, os can perform a configuration read to, say, the vendorid/deviceid register of the root port and the expectation is that the completion for this read will flush all the previously issued memory writes. the reason the os wants to flush is for cases where an interrupt source (like a root port) is being retargeted to a different processor and os needs to flush any msi that is already pending in the fabric that is still targeting the old processor. as a case in point, reads to intel 5000x chipset mch pci express (internal) configuration spaces will not generally guarantee ordering of internal msis from a root port/dma engine device as required since the intel 5000x chipset mch uses a configuration ring methodology which houses the registers for the various pci express ports, mc, dma engine, dfx and so forth) and it operates independently of the msi/ interrupt generation logic. thus any configuration ring access targeting a pci express port registers will not necessarily orde r and align with the internal msis. solution : to mitigate this problem and enforce ordering of the msis, the intel 5000x chipset mch will implement a ?pending msi signal? that is broadcast from the msi/ hotplug blocks to the coherency engine and thereby block the configuration request (non-posted) till all the msi gets committed. software will ensure that it will block future msi generation for that device when it issues the configuration read for that device. the ce will block sending any completion with the new bit-slice bit set when any of the pending msi wires is asserted. ce will not block other transactions or completions during the block. when the pending msi wires are deasserted, ce will be able to send the configuration completions. the intel 5000x chipset mch coherency engine (ce) will block processor initiated mch configuration access completions (mmcfg or cfc/cf8) if there is a pending internally generated msi within the intel 5000x chipset mch. (msis could be generated from the dma engine or the hotplu g-pwr-mgr-pex error block. the pending msi signal will be deasserted after fetch-completion is asserted for the msi from ce, that is, global visibility is guaranteed on the fsb. then release the configuration block and allow the configurat ion completion to flow through. this approach will order the msi and then send the non-posted configuration for that device. ce will add a bit-slice (one bit per table entry) to track processor initiated mch configuration access in ce transaction ta ble. note: inbound configuration access will not set this bit. a defeature mode to control the msi/np_cfg ordering is defined in the cohdef.dis_msi_npcfg register field. note: internal msis cannot be continuously genera ted since the corresponding status register field needs to be cleared by software through configuration access before a new msi can be asserted.
functional description 346 intel ? 5000x chipset memory controller hub (mch) datasheet 5.10 legacy/8259 interrupts 8259 interrupt controller is supported in in tel 5000x chipset platforms. 8259 interrupt request is delivered using the interrupt group sideband signals lint[1:0] (a.k.a. nmi/ intr) or through an i/o xapic using the message based interrupt delivery mechanism with the delivery mode set to extint (111b). there can be only one active 8259 controller in the system. the mechanism in which a pci express device requests an 8259 interrupt is a pci express inband message. (assert_inta/b/c/d, deassert_inta/b/c/d). the target processor for the interrupt uses the interrupt acknowledge transaction to obtain the interrupt vector from the 8259 controller. the intel 5000p chipset forwards the interrupt acknowledge to the intel 6 31xesb/632xesb i/o controller hub where the active 8259 controller resides. the intel 5000p chipset will support pci expr ess devices that generate 8259 interrupts (for example, during boot). 8259 interrupts from pci express devices will be sent in- band to the intel 5000p chipset which w ill forward these interrupts to the intel 631xesb/632xesb i/o controller hub. the intel 5000x chipset will have a mechan ism to track inband 8259 interrupts from each pci express and assert virtual interrupt signals to the 8259 through the inband ?assert_(deassert)_intx? messages. this is do ne by a tracking bit per interrupt (a, b, c, d) in each pci express which are combined (or?d) into virtual signals that are sent to the intel 631xesb/632xesb i/o controller hu b. each interrupt signal (a, b, c, d) from each pci express is or?ed together to form virtual int a, b, c, and d signals to the intel 631xesb/632xesb i/o contro ller hub (assert_(deassert)_inta/b/c/d (assertion encoding)). when all of the tracking bits for a given interrupt (a, b, c, or d) are cleared from all pci express ports, the virt ual signal a, b, c, or d is deasserted via the inband deassert_intx message. for pci express hierarchies, interrupts will be consolidated at each level. for example, a pci express switch connected to a intel 5 000p chipset pci express port will only send a maximum of 4 interrupts at a time, regardless of how many interrupts are issued downstream. smi (system management interrupt) interrupts are initiated by the smi# signal in the platform. on accepting a system management interrupt, the processor saves the current state and enters smm mode. note that the intel 5000x chip set core components do not interact with the lint[1:0] and smi signals. they are present on th e intel 631xesb/632xesb i/o controller hub and the processor. intel 5000x chipset interrupt signals described in section 5.9 can be routed to the intel 631xesb/632xesb i/o controller hub to generate an smi interrupt. similarly sci interrupts can be generated by routing intel 5000x chipset interrupt signals to the appropriate intel 631xesb/632xesb i/o controller hub pin. 5.11 interrupt error handling software must configure the system so that each interrupt has a valid recipient. in the event that an interrupt doesn?t have a valid recipient, since the intel 5000x chipset will not necessarily know that the interrupt is targeted for a non-existing processor, will deliver the interrupt to the processor buses following the interrupt routing rules described in this chapter. if the interrupt targets a non-existing processor, it may be ignored but the transactio n should still complete.
intel ? 5000x chipset memory controller hub (mch) datasheet 347 functional description any error in the data part of an interrupt message, interrupt acknowledge, or eoi will be treated the same way as data error with any other transaction ? single bit errors will be corrected by ecc, double bit error will be treated and logged as uncorrectable. for more details on error handling, please refer to the ras chapter. 5.12 enterprise south bridge interface (esi) the enterprise south bridge interface (esi) in the intel 5000x chipset north bridge is the chip-to-chip connection to the intel 631xesb/632xesb i/o controller hub see figure 5-16 . the esi is an extension of the stan dard pci express specification with special commands/features added to enhance the pci express interface for enterprise applications. this high-speed interface inte grates advanced priority-based servicing allowing for concurrent traffic. base functi onality is completely transparent permitting current and legacy software to operate normally. for the purposes of this document, the intel 631xesb/632xesb i/o controller hu b will be used as a reference point for the esi discussion in the intel 5000x chipset north bridge. the esi port in the intel 5000x chipset north bridge may be combined with two additional pci express ports to augment th e available bandwidth to the intel 631xesb/ 632xesb i/o controller hub. when operating alone the available bi-directional bandwidth to the intel 631xesb/632xesb i/o controller hub is 2 gb/s (1 gb/s each direction). when the esi is pared with 2 additional x4 pci express links the available bi-directional bandwidth to the intel 631x esb/632xesb i/o controller hub is increased to 6 gb/s. the details of how the esi port is combined with additional x4 pci express ports are covered in section 5.13.3 . figure 5-16. mch to intel 631xesb/632xesb i/ o controller hub enterprise south bridge interface link transaction physical intel? 631xesb/632xesb i/o controller h ub link transaction physical mch port 0 x4 dmi
functional description 348 intel ? 5000x chipset memory controller hub (mch) datasheet 5.12.1 power management support the intel 631xesb/632xesb i/o controller hub provides a rich set of power management capabilities for the operating system. the mch receives pm_pme messages on its standard pci express port and propagates it to the intel 631xesb/ 632xesb i/o controller hub over the es i as an assert_pmegpe message. when software clears the pexrtsts.pme status register bit, in the pexrststs[7:2, 0] pci express root status register , after it has completed the pme protocol, the mch will generate a deassert_pmegpe message to the intel 631xesb/632xesb i/o controller hub. the mch must also be able to genera te the assert_pmegpe message when exiting s3 (after the reset). the pmgpe messages are also sent using a wired-or approach. 5.12.1.1 rst_warn and rst_warn_ack the rst_warn message is generated by th e intel 631xesb/632xesb i/o controller hub as a warning to the mch that it wants to assert pltrst# before sending the reset. in the past, problems have been encountered du e to the effects of an asynchronous reset on the system memory states. since memory has no reset mechanism itself other than cycling the power, it can cause problems with the memory?s internal states when clocks and control signals are asynchronously tri-st ated or toggled, if operations resume following this reset without power cycling. to protect against this, the intel 631xesb/ 632xesb i/o controller hub will send a rese t warning to the mch. the gold bridge (advanced memory buffer) is supposed to ha ndle putting the dimms into a non-lockup state in the event the link ?goes down? in th e middle of ddr2 protocol. the intel 5000p chipset mch is not required to place quiesce the dram?s prior to reset. the mch completes the handshake by genera ting the rst_warn_ack message to the ich6 at the earliest. 5.12.1.2 stpclk propagation the intel 631xesb/632xesb i/o controller hub has a sideband signal called stpclk. this signal is used to place ia32 cpus into a low power mode. traditionally, this signal has been routed directly from the i/o controller hub to the cpus. in future esbx components, the plan is to rearchitect the mechanism for alerting the cpus of a power management event. however, this chipset (using intel 631xesb/ 632xesb i/o controller hub) will require th e same method used for past server chipsets (route stpclk on the board as appropriate). the mch will not provide any in-band mechanisms for stpclk. 5.12.2 special interrupt support the intel 631xesb/632xesb i/o controller hub in tegrates an i/o apic controller. this controller is capable of sending interrupts to the processors with an inbound write to a specific address range that th e processors recognize as an interrupt. in general, the compatibility interface cluster treats these no differently from inbound writes to dram. however, there are a few notable differences listed below. 5.12.3 inbound interrupts to the mch, interrupts from the intel 631x esb/632xesb i/o controller hub are simply inbound non-coherent write commands routed to the processor buses. the mch does not support the serial apic bus.
intel ? 5000x chipset memory controller hub (mch) datasheet 349 functional description 5.12.4 legacy interrupt messages the esi and pci express interfaces support two methods for handling interrupts: msi and legacy interrupt messages. the interrupt messages are a mechanism for taking traditionally out-of -band interrupt signals and using in-band messages to communicate. each pci express interface accepts up to four interrupts (a through d) and each interrupt has an assert/deassert message to emulate level-triggered behavior. the mch effectively wire-ors all the inta messages together (intbs are wire-ored together, and so forth). when the mch accepts these pci express inte rrupt messages, it aggregates and passes the corresponding ?assert_intx? messages to the intel 631xesb/632xesb i/o controller hub?s i/oapic with from the pci express ports (wired-or output transitions from 0 ? > 1) mechanism. when the corresponding deassert_intx message is received at all the pci express ports (wired -or output transitions from 1 ? > 0), the ?deassert_intx? message is sent to esi port. 5.12.5 end-of-interrupt (eoi) support the eoi is a specially encoded processor bus transaction with the interrupt vector attached. since the eoi is not directed, the mch will broadcast the eoi transaction to all i/o(x)apics. the mch.pexctrl.dis_apic_eoi bit per pci express port can be used to determine whether an eoi needs to be sent to a specific port. 5.12.6 error handling ta b l e 5 - 3 1 describes the errors detected on es i through the standard pci express and advanced error reporting mechanism. 5.12.6.1 inbound errors in general, if an inbound read transactio n results in a master abort (unsupported request), the compatibility interface cluster returns a master abort completion with data as all ones. likewise, for a target abort condition, the esi cluster returns a target abort completion with data as all ones. if a read request results in a master or target abort, the mch returns the requested number of data phases with all ones data. master aborted inbound writes are dropped by the mch, the error is logged, and the data is dropped. if the mch receives an inbound unsupported special cycle message it is ignored and the error condition is logged. if the comple tion required bit is set, an unsupported special cycle completion is returned. 5.12.6.2 outbound errors it is possible that the compatibility interfac e cluster will receive an error response for an outbound request. this can include a ma ster or target abort for requests that required completions. the mch might also receive an ?unsupported special cycle? completion. 5.13 pci express ports the intel 5000x chipset mch contains two cl asses of pci express derived ports. these are:
functional description 350 intel ? 5000x chipset memory controller hub (mch) datasheet ? enterprise south bridge interface (esi), port 0 ? general purpose ports, port 2, port 3, note: there is no pci express port designated as port 1. the esi port is the primary interface to the intel 631xesb/632xesb i/o controller hub. this interface can be paired with up to two of the pci express ports (port 2 and port 3) to increase available bandwidth to the in tel 631xesb/632xesb i/o controller hub. the intel 5000x chipset mch supports a high performance x16 graphics pci express port. this port contains several architectural enhancements to increase graphics performance. the following sections describe the characteristics of each of these port classes in detail. 5.13.1 intel 5000x chipset mc h pci express port overview the intel 5000x chipset mch utilizes genera l purpose pci express high speed ports to achieve superior i/o performance. the mch pci express ports are compliant with the pci express interface sp ecification, rev 1.0a . a pci express port is defined as a collection of bit lanes. each bit lane consists of two differential pairs in each direction (transmit and receive) as depicted in ta b l e 5 - 1 7 . the raw bit-rate per pci express bit lane is 2.5 gbit/s. this results in a real bandwidth per bit lane pair of 250 mb/s given the 8/10 encoding used to transmit data across this interface. the result is a maximum theoreti cal realized bandwidth on a x4 pci express port of 1 gb/s in each direction. figure 5-17. x4 pci express bit lane rx tx device tx rx rx device rx tx lane 0 lane 3 link (x4) p o r t p o r t tx ac coupling capacitors ac coupling capacitors tx rx rx tx lane 1 ac coupling capacitors tx rx rx tx lane 2 ac coupling capacitors
intel ? 5000x chipset memory controller hub (mch) datasheet 351 functional description each of the intel 5000x chipset mch pci express port are organized as four bi- directional bit lanes, and are referred to as a x4 port. 5.13.2 enterprise south bridge interface (esi) the esi is the intel 631xesb/632xesb i/o co ntroller hub to intel 5000x chipset mch interface. the available bandwidth to th e intel 631xesb/632xesb i/o controller hub can be increased by using the one or more of the pci express ports 2 and 3. figure 5-18 depicts the esi port and pci express ports 2 and 3. 5.13.3 pci express ports 2 and 3 the pci express ports 2 and 3 are general pu rpose x4 pci express ports that may be used to connect to pci express devices. th e possible configurations of the pci express ports are depicted in figure 5-18 . by configuring ports 2 and 3 with the esi port to the intel 631xesb/632xesb i/o controller hub, band width is definable from 1gb/s in each direction up to a maximum of 6 gb/s bi-directional. figure 5-19 depicts the various combinations of esi and ports 2 and 3 connecting to the intel 631xesb/632xesb i/o controller hub. ports 2 and 3 are also gene ral purpose pci express ports that may be used as high performance interfaces to other pci express devices. figure 5-18. esi and pci express ports 2 and 3 link transaction physical intel? 631xesb/632xesb i/o controller hub link transaction physical mch port 0 x4 dmi
functional description 352 intel ? 5000x chipset memory controller hub (mch) datasheet 5.13.4 pci express general purpose ports port 4, port 5, port 6, and port 7 are conf igurable for general purpose i/o applications. the intel 5000x chipset mch combines thes e four general purpose x4 ports into a single optimized x16 high performance graphics interface. this interface is depicted in figure 5-20 . these ports contain several architectural enhancements to improve graphics performance. figure 5-19. mch to intel 631xesb/632xes b i/o controller hub port configurations mch intel? 631xesb/632xesb i/o controller hub esi 2 gb/sec pci-e x4 2 gb/sec pci-e x4 2 gb/sec port 2 port 3 esi
intel ? 5000x chipset memory controller hub (mch) datasheet 353 functional description 5.13.5 supported length width port partitioning to establish a connection between pci expr ess endpoints, they both participate in a sequence of steps known as training. this sequence will establish the operational width of the link as well as adjust skews of the va rious lanes within a link so that the data sample points can correctly take a data sample off of the link. in the case of a x8 port, the x4 link pairs will first attempt to train independently, and will collapse to a single link at the x8 width upon de tection of a single device returning link id information upstream. once the number of links has been established, they will negotiate to train at the highest common width, and will step down in its supported link widths in order to succeed in training. the ultimate result may be that the link has trained as a x1 link. although the bandwidth of this link size is substantially lower than a x8 link or x4 link, it will allow communication between the two devices. software will then be able to interrogate the device at the other end of th e link to determine why it failed to train at a higher width. this autonomous capability can be overridden by the values sampled on the pewidth[3:0] pins. ta b l e 5 - 4 illustrates the pewidth strapping options for various link widths in the pci express ports in the mch. figure 5-20. intel 5000x chipset pc i express* high pe rformance x16 port pci-express cluster (iou1) physical link transaction port 4 port 5 port 6 port 7 x16 x4 x4 x4 x4 high performance graphics port
functional description 354 intel ? 5000x chipset memory controller hub (mch) datasheet note: intel 5000v chipset does not have pci express ports 4, 5, 6, and 7. so the only option is to configure ports 2 and 3 as a single x8 or two x4 ports. note: the pci express base specification , revision 1.0a requires that a port be capable of negotiating and operating at the native widt h and 1x. the intel 5000x chipset mch will support the following link widths for its pci- express ports viz., x16, x8, x4, x2 and x1. during link training, the mch will attempt link negotiation starting from its native link width from the highest and ramp down to the nearest supported link width that passes negotiation. for example, a port strapped at 8x, will first attempt negotiation at 8x. if that attempt fails, an attempt is made at x4, then a x1 link.note that the x8 and x4 link widths will only use the lsb positions from lane 0 while a x1 can be connect to any of the 4 positions (lane0,lane1, lane2, lane3) pr oviding a higher tolerance to single point lane failures. 5.13.6 pci express port support summary the following table describes the options and limitations supported by the mch pci express ports. table 5-4. pci express link wid th strapping options for port cpci configuration in mch pewidth[3:0] port0 (esi) port2 port3 port4 port5 port6 port7 0000 x4 x4 x4 x4 x4 x4 x4 0001 x4 x4 x4 x4 x4 x8 0010 x4 x4 x4 x8 x4 x4 0011 x4 x4 x4 x8 x8 0100 x4 x4 x4 x16 others reserved 1000 x4 x8 x4 x4 x4 x4 1001 x4 x8 x4 x4 x8 1010 x4 x8 x8 x4 x4 1011 x4 x8 x8 x8 1100 x4 x8 x16 others reserved 1111 x4. all port widths determin ed by link negotiation. table 5-15. options and limitations (sheet 1 of 2) parameter support number of supported ports the mch will support six x4 standard pci express ports and an additional x4 esi port for intel 631xesb/632xesb i/o controller hub. (total: 6 + 1 = 7 ports) max payload 256b hot-plug serial port to support pins virtual channels mch only supports vc0 isochrony mch does not support isochrony ecrc mch does not support ecrc ordering mch only supports strict pci ordering no snoop mch will not snoop processor caches for transactions with the no snoop attribute
intel ? 5000x chipset memory controller hub (mch) datasheet 355 functional description 5.13.7 pci express port phys ical layer characteristics the pci express physical layer implements high-speed differential serial signalling using the following techniques: ? differential signalling (1.6 v peak-to-peak) ? 2.5 ghz data rate (up to 2 gb/s/direction peak bandwidth for a x8 port) ? 8b/10b encoding for embedded clocking and packet framing ? unidirectional data path in each direction supporting full duplex operation ? random idle packets and spread-spectrum clocking for reduced emi ? loop-back mode for testability ? lane reversal ? polarity inversion figure 5-21 illustrates the scope of the physical layer on a pci express packet. there are two types of packets: link layer packets and transaction layer packets. the physical layer is responsible for framing these packets with stp/end symbols (transaction layer packets) and sdp/end symbols (data link layer packets). the grayed out segment is not decoded by the physical layer. 5.13.7.1 pci express training to establish a connection between pci expr ess endpoints, they both participate in a sequence of steps known as training. this sequence will establish the operational width of the link as well as adjust skews of the va rious lanes within a link so that the data sample points can correctly take a data sample off of the link. in the case of a x8 port, the x4 link pairs will first attempt to train independently, and will collapse to a single link at the x8 width upon de tection of a single device returning link id information upstream. once the number of links has been established, they will negotiate to train at the highest common width, and will step down in its supported link widths in order to succeed in training. the ultimate result may be that the link has trained as a x1 link. although the bandwidth of this link size is substantially lower than a x8 link or x4 link, power management the mch cannot be powered down, bu t will forward messages, generate pme_turn_off and collect pme_to_acks. it will provide the pm capabilities structure. the mch does not support active state power management nor the l0s state. no cable support & no repeaters retry buffers are sized to meet the intel 5000x chipset platform requirements for an integrated dp ch assis and which do not require cable or repeater support. only an 8 inch es of fr4 internal trace connector latency is assumed. poisoning mch will poison data that it cannot correct table 5-15. options and limitations (sheet 2 of 2) parameter support figure 5-21. pci express packet visibility by physical layer stp link/txn layer visible info end sdp link layer visible info end
functional description 356 intel ? 5000x chipset memory controller hub (mch) datasheet it will allow communication between the two de vices. software will then be able to interrogate the device at the other end of the link to determine why it failed to train at a higher width. 5.13.7.2 8b/10b encoder/decoder and framing as a transmitter, the physical layer is responsible for encoding each byte into a 10 bit data symbol before transmission across the link. packet framing is accomplished by the physical layer by adding special framin g symbols (stp, sdp, end). pci express implements the standard ethernet and infiniband* 8b/10b encoding mechanism. 5.13.7.3 elastic buffers every pci express port implements an inde pendent elastic buffer for each pci express lane. the elastic buffers are required since the intel 5000x chipset mch and pci express endpoints could be clocked from different sources. clocks from different sources will never be exactly the same. the ou tputs of the elastic buffers feed into the deskew buffer. the elastic buffer is eight symbols deep. this accounts for three clocks of synchronization delay, the longest possible tlp allowed by the intel 5000x chipset mch (256 b), a 600ppm difference between tr ansmitter and receiver clocks, and worst case skip ordered sequence interval of 1538 , framing overheads, and a few symbols of margin. 5.13.7.4 deskew buffer every pci express port implements a deskew buffer. the deskew buffer compensates for the different arrival times for each of the symbols that make up a character. the outputs of the deskew buffer is the data path fed into the link layer. figure 5-22. pci express elastic buffer (x4 example) 4x local clock = 2.501 ghz remote clock = 2.499 ghz
intel ? 5000x chipset memory controller hub (mch) datasheet 357 functional description at reset, the delay of each la ne in the deskew buffer is ad justed so that the symbols on each lane are aligned. the receiver must compensate for the allowable skew between lanes within a multi-lane link before deliver ing the data and control to the data link layer. the deskew buffer is eight symbols d eep to compensate for up to 20 ns of skew between lanes. 5.13.7.5 polarity inversion the pci express base specification , revision 1.0a defines a concept called polarity inversion. polarity inversion allows the boar d designer to connect the d+ and d- lines incorrectly between devices. the intel 5000x chipset mch supports polarity inversion. 5.13.8 link layer the data link layer of the pci express pr otocol is primarily responsible for data integrity. this is accomplishe d with the following elements: ? sequence number assignment for each packet ? ack/nak protocol to ensure successful transmission of every packet ? crc protection of packets ? time-out mechanism to detect ?lost? packets ?credit exchange figure 5-24 illustrates the scope of the link layer on a pci express packet. there are two types of packets: data link layer packets (dllp) and transaction layer packets (tlp). data link layer packets are sent be tween the link layers of each pci express device and do not proceed to the transaction layer. for transaction layer packets (tlp), the link layer is responsible for prepending sequence numbers and appending 32-bit crc. the grayed out segment is not decoded by the data link layer. figure 5-23. pci express deskew buffer (4x example) elastic buffer
functional description 358 intel ? 5000x chipset memory controller hub (mch) datasheet 5.13.8.1 data link layer packets (dllp) refer to pci express base specification , revision 1.0a for an explicit definition of all the fields in a data link layer packet. dllps are used to ack or nak packets as they are sent from the transmitter to the receiver. they are sent by the receivers of th e packet to indicate to the transmitter that a packet was successfully received (ack) or not (nak). dllps are also used to exchange credit information betw een the transmitter and receiver. dllps are protected with 16b crc. if the crc of a received dllp indicates an error, the dllp is dropped. this is safe because the pci express protocol supports dropping these packets and the next dllp allows th e transmitter to process successfully. 5.13.8.2 ack/nak the data link layer is responsible for ensuring that packets are successfully transmitted between pci express agents . pci express implements an ack/nak protocol to accomplish this. every packet is decoded by the physical layer and forwarded to the link layer. the crc code appe nded to the packet is then checked. if this comparison fails, the packet is ?retried?. if the comparison is successful, an ack is i ssued back to the transmitter and the packet is forwarded for decoding by the receiver?s transaction layer. typically, as each packet is successfully received by the data link layer, the receiver issues an ack. however, the pci express protocol allows that acks can be combined. 5.13.8.3 link level retry the pci express base specification , revision 1.0a lists all the conditions where a packet gets negative acknowledged. one example is on a crc error. the link layer in the receiver is responsible for calculating 32 b crc (using the polynomial defined in the pci express base specification , revision 1.0a) for incoming packets and comparing the calculated crc with the received crc. if they do not match, then the packet is retried by negative acknowledging the packet with a nak dllp and specifying the sequence number of the last good packet. subsequent packets are dropped until the reattempted packet is observed again. when the transmitter receives the nak, it is responsible for retransmitting the packet. furthermore, any packets sent after the last good packet will also be resent since the receiver has dropped any packets after the corrupt packet. the transmitter keeps track of packets that have been sent but not acknowledged through the use of a retry buffer. transactions are added to the buffer as they are on the pci express port. transactions are remove d from the buffer after they have been acknowledged by the receiver. figure 5-24. pci express pack et visibility by link layer seq # tlp crc dllp
intel ? 5000x chipset memory controller hub (mch) datasheet 359 functional description 5.13.8.4 ack time-out packets can get ?lost? if the packet is corrupted such that the receiver?s physical layer does not detect the framing symbols properly. normally, lost packets are detectable with non-linearly incrementing sequence numbers. a time-out mechanism exists to detect (and bound) cases where the last packet sent (over a long period of time) was corrupted. a replay timer bounds the time a re try buffer entry waits for an ack or nak. refer to the pci express base specification , revision 1.0a for details on this mechanism for the discussion on retry management and the recommended timer values. 5.13.9 flow control the pci express mechanism for flow control is credit based and only applies to tlps. dllp packets do not consume any credits. through initial hardware negotiation and subsequent updates, a pci expr ess transmitter is aware of the credit capabilities of the interfacing device. a pci express requester will never issue a transaction when there are not enough advertised credits in the ot her component to support that transaction. if there are not enough credits, the requeste r will hold off that transaction until enough credits free up to support the transaction. if the ordering rules and available credits allow other subsequent transactions to proc eed, the mch will allow those transactions. for example, assume that there are no no n-posted request header credits (nprh) credits remaining and a memory write is the next transaction in the queue. pci express ordering rules allow posted writes to pass reads. therefore, the intel 5000x chipset mch will issue the memory write. subsequent memory reads from the source device must wait until enough nprh credits free up. note: flow control is orthogonal with packet acks. the pci express flow control credit types are described in ta b l e 5 - 1 6 . the pci express base specification , revision 1.0a defines which tlps are covered by each flow control type. table 5-16. pci express credit mapping for inbound transactions (sheet 1 of 2) flow control type definition initial mch advertisement inbound posted request header credits (iprh) tracks the number of inbound posted requests the agent is capable of supporting. each credit accounts for one posted request. 14 (4x) 28(8x) 56(x16) inbound posted request data credits (iprd) tracks the number of inbound posted data the agent is capable of supporting. each credit accounts for up to 16 bytes of data. 54 (4x) 108(8x) 216(16x) inbound non- posted request header credits (inprh) tracks the number of non-posted requests the agent is capable of supporting. each credit accounts for one non-posted request. 14 (4x) 28(8x) 56(16x)
functional description 360 intel ? 5000x chipset memory controller hub (mch) datasheet the credit advertisements for the mch are shown in ta b l e 5 - 1 6 and ta b l e 5 - 1 7 . every pci express device tracks the above six credit types (inbound) for both itself and the interfacing device. the rules governin g flow control are described in the pci express base specification , revision 1.0a. inbound non- posted request data credits (inprd) tracks the number of non-posted data the agent is capable of supporting. each credit accounts for up to 16 bytes of data. 2 (4x) 4 (8x) 8 (16x) completion header credits (cph) (outbound request completions received at the mch) tracks the number of completion headers the agent is capable of supporting. 1 0 (infinite) (4) [x4] (8) [x8] (16) (x16) completion data credits (cpd) (outbound request completions (data) received at the mch) tracks the number of completion data the agent is capable of supporting. each credit accounts for up to 16 bytes of data. 0 (infinite) (8) [x4] (16) [x8] (32) [x16] notes: 1. root complexes and end points are permitted to adve rtise an infinite number of credits for completions. though the mch implements finite queue structures as indicated in bracket for the completions on the inbound side, by construction, it will never overflow since for each outbound request, the mch allocates sufficient space on the inbound side. i.e guarantee by construction table 5-17. pci express credit ma pping for outbound transactions flow control type definition initial mch advertisement outbound posted request header credits (oprh) tracks the number of outbound posted requests the agent is capable of supporting. each credit accounts for one posted request. 4(4x) 8(8x) 16(16) outbound posted request data credits (oprd) tracks the number of outbound posted data the agent is capable of supporting. each credit accounts for up to 16 bytes of data. 8(4x) 16(8x) 32(16x) outbound non- posted request header credits (onprh) tracks the number of non-posted requests the agent is capable of supporting. each credit accounts for one non-posted request. 16(4x) 32(8x) 64(16x) outbound non- posted request data credits (onprd) tracks the number of non-posted data the agent is capable of supporting. each credit accounts for up to 16 bytes of data. 16(4x) 32(8x) 64(16x) completion header credits (cplh) (inbound request completions from mch) tracks the number of completion headers the agent is capable of supporting. 2(x4) 4(x8) 8(x16) completion data credits (cpld) (inbound request completions (data) from the mch) tracks the number of completion data the agent is capable of supporting. each credit accounts for up to 16 bytes of data. 8(x4) 16(x8) 32(x16) table 5-16. pci express credit mapping for inbound transactions (sheet 2 of 2) flow control type definition initial mch advertisement
intel ? 5000x chipset memory controller hub (mch) datasheet 361 functional description 5.13.9.1 credit update mechanism, flow control protocol (fcp) after reset, credit information is initialized with the values indicated in ta b l e 5 - 1 6 by following the flow control initialization protocol defined in the pci express base specification , revision 1.0a. since the mch supports only vc0, only this channel is initialized. 5.13.10 transaction layer the pci express transaction layer is responsible for sending read and write operations between components. this is the pci expr ess layer which actually moves software visible data between components. the transaction layer provides the mechanisms for: ? software configuration of components ? communication between the processo r bus and different i/o technologies ? communication between the memory and different i/o technologies figure 5-17 illustrates the scope of the transaction layer on a pci express packet. some transaction layer packets have only a header (for example, read request). some transaction layer packets have a header followed by data (for example, write requests and read completions). 5.14 power management the intel 5000x chipset mch power management support includes: ? acpi supported ? system states: s0, s1 (desktop), s3, s4, s5, c0, c1, c2 (desktop) 5.14.1 supported acpi states the mch supports the following acpi states: ? processor ? c0: full on. ?c1: auto halt. ? c2 desktop: stop grant. clock to processor still running. clock stopped to processor core. ?system ? g0/s0: full on. ? g1/s1: stop grant, desktop s1, same as c2. ? g1/s2: not supported. ? g1/s3: suspend to ram (str). power and context lost to chipset. ? g1/s4: suspend to disk (std). all power lost (except wake-up logic on intel 631xesb/632xesb i/o controller hub). figure 5-25. pci express packet visibility by transaction layer hdr hdr payload
functional description 362 intel ? 5000x chipset memory controller hub (mch) datasheet ? g2/s5: soft off. requires total system reboot. ? g3: mechanical off. all power lost (except real time clock). 5.14.2 fb-dimm thermal management the intel 5000x chipset mch implemen ts the following thermal management mechanisms. these mechanisms manage the read and write cycles of the system memory interface to implement thermal throttling. hardware-based thermal management the number of hex-words transferred over th e dram interface are tracked per row. the tracking mechanism takes into account that the dram devices consume different levels of power based on cycle type (page hit/mi ss/empty). if the programmed threshold is exceeded during a monitoring window, the activity on the dram interface is reduced. this helps in lowering the power and temperature. software-based thermal management this is used when the external thermal sensor in the system interrupts the processor to engage a software routine for thermal management. 5.14.3 fb-dimm ther mal diode overview the fb-dimm advanced memory buffer (amb) contains an internal thermal diode to measure amb / dimm temperature. upon detecting a thermal over temperature condition the amb initiates a thermal throttling event. for more information see the gold bridge component external design specification . 5.15 system reset the intel 5000x chipset mch is the root of the i/o subsystem tree, and is therefore responsible for general propagation of system reset throughout the platform. the mch must also facilitate any specialized synchron ization of reset mechanisms required by the various system components. 5.15.1 mch power sequencing general power sequencing requirements for the intel 5000x chipset mch are simple. in general higher voltages must come up before lower voltages. figure 5-26 depicts the sequencing of the three main voltages powering the intel 5000x chipset mch. note: power-up -> 3.3v must ramp ahead and stay above 1.5v, which must ramp ahead and stay above 1.2v. figure 5-26. intel 5000p chipset power sequencing
intel ? 5000x chipset memory controller hub (mch) datasheet 363 functional description 3.3v must always be at least 0.7v greater than 1.5v. duration of the power ramp must be between 0.1 ms and 100 ms. 5.15.2 mch reset types the intel 5000x chipset mch differentiates among five types of reset as defined in table ta b l e 5 - 1 8 . 5.15.2.1 power-good mechanism the initial boot of a intel 5000x chipset mc h platform is facilitated by the power-good mechanism. the voltage sources from all platform power supplies are routed to a system component which tracks them as they ramp-up, asserting the platform ?pwrgd? signal a fixed interval (nominally 2ms) after the last voltage reference has stabilized. there are no requirements within the mch regarding the precise sequencing of power- supply ramps, thus the platform should in itialize properly regardless of the order in which supplies stabilize. both the intel 5000x chipset mch and th e intel 631xesb/632xesb i/o controller hub receive the system pwrgd signal via dedicate d pins as an asynchronous input, meaning that there is no assumed relationship between the assertion or deassertion of pwrgd and any system reference clock. when pwrgd is deasserted all platform subsystems are held in their reset state. this is accomplished by various mechanisms on each of the different interfaces. the mc h will hold itself in a power-on reset state when pwrgd is deasserted. the intel 631xesb/632xesb i/o controller hub is expected to assert its pcirst# output and maintain its assertion for 1ms after power is good. the pcirst# output from intel 631xesb/632xesb i/o co ntroller hub is expected to drive the rstin# input pin on the intel 5000x chipset mch, which will in turn hold the processor complex in reset via assertion of the fsbxreset# fsb signals. the pci express attached devices and any hierarchy of components underneath them are held in reset via implicit messaging ac ross the pci express interface. the mch is the root of the hierarchy, and will not engage in link training until power is good and the internal ?hard? reset has deasserted. a pwrgd reset will clear all internal state mach ines and logic, and initialize all registers to their default states, including ?sticky? error status bits that are persistent through all other reset classes. to eliminate potential system reliability problems, all devices are also required to either tri-state their outputs or to drive them to ?safe? levels during a power-on reset. table 5-18. mch reset classes type mechanism effect / description power-good pwrgd input pin propagated throughout the system hierarchy. resets all logic and state machines, and initializes all registers to their default states (sticky and non-sticky). tri-states all mch outputs, or drives them to ?safe? levels. hard rstin # input pin, configuration write propagated throughout the system hierarchy. resets all logic and state machines, and initializes all non-stick y registers to their default states. tri-states all mch outputs, or drives them to ?safe? levels. processor- only configuration write propagated to all processors via the fsbxrerset# pins on the fsb. the mch does not undergo an internal reset. targeted configuration write propagated down the targeted pci express port hierarchy. treated as a ?hard? reset by all affected comp onents, clearing all machine state and non-sticky configuration registers. binit# internal error handling propagated via fsb binit # pin propagated to all fsb attached components (the mch and up to two processors). clears the ioq, and resets all fsb arbiters and state machines to their default states. not recoverable.
functional description 364 intel ? 5000x chipset memory controller hub (mch) datasheet the only system information that will ?survive? a pwrgd reset is either contained in battery-backed or non-volatile storage. 5.15.2.2 hard reset mechanism once the intel 5000x chipset mch platform has been booted and configured, a full system reset may still be required to recove r from system error conditions related to various device or subsystem failures. the ?hard? reset mechanism is provided to accomplish this recovery without clearing the ?sticky? error status bits useful to track down the cause of system reboot. a hard reset is typically initiated by th e intel 631xesb/632xesb i/o controller hub component via the pcirst# output pin, whic h is commonly connected directly to the intel 5000x chipset mch rstin# in put pin. the intel 631xesb/632xesb i/o controller hub may be caused to assert pcirst# via both software and hardware mechanisms. the intel 5000x chipset mc h will recognize a hard reset any time rstin# is asserted while pwrgd remains asserted. the intel 5000x chipset mch will propagate a hard reset to the fsb and to all subordinate pci express subsystems. the fsb components are reset via the fsbxreset# signals, while th e pci express subsystems are reset implicitly when the root port links are taken down. a hard reset will clear all internal state ma chines and logic, and initialize all ?non- sticky? registers to their default states. no te that although the error registers will remain intact to facilitate root-cause of the hard reset, the intel 5000x chipset mch platform in general will require a full configuration and initialization sequence to be brought back on-line. 5.15.2.3 processor-only reset mechanism for power management and other reasons, th e intel 5000x chipset mch supports a targeted processor only reset semantic. this mechanism was added to the platform architecture to eliminate double-reset to the system when reset-signaled processor information (such as clock gearing selection) must be updated during initialization bringing the system back to the s0 state after power had been removed from the processor complex. 5.15.3 targeted re set mechanism the targeted reset is provided for hot-plug events, as well as for port-specific error handling under machine check architecture (m ca) or smi software control. the former usage model is new with pci express techno logy, and the reader is referred to the pci express interface specification, rev 1.0a for a description of the hot-plug mechanism. a targeted reset may be reques ted by setting bit 6 (secondary bus reset) of the bridge control register (offset 3eh) in the target root port device. this reset will be identical to a general hard reset from the perspectiv e of the destination pci express device; it will not be differentiated at the next level down the hierarchy. sticky error status will survive in the destination device, but softwa re will be required to fully configure the port and all attached devices once reset an d error interrogation have completed. after clearing bit 6, software may determine when the downstream targeted reset has effectively completed by monitoring the state of bit 1 (link active) of the vs_sts1 register (offset 47h) in the target root port device. this bit will remain deasserted until the link has regained ?link up? status, whic h implies that the downstream device has completed any internal and downstream resets, and successfully completed a full training sequence.
intel ? 5000x chipset memory controller hub (mch) datasheet 365 functional description under normal operating conditions it should no t be necessary to initiate targeted resets to downstream devices, but the mechanism is provided to recover from combinations of fatal and uncorrectable errors which compromise continued link operation. 5.15.4 binit# mechanism the binit# mechanism is provided to facilitate processor handling of system errors which result in a hang on the fsb. th e machine check architecture (mca) code responding to an error indication, typically ierr# or mcerr#, will cause an attempt to interrogate the mch for error status, and if that fsb transaction fails to complete the processor will automatically time out and respond by issuing a binit# sequence on the fsb. when binit# is asserted on the fsb, all bus agents (cpus and mch) are required to reset their internal fsb arbiters and all fsb tracking state machines and logic to their default states. this will effectively ?un-hang ? the bus to provide a path into chipset configuration space. note that the mch device implements ?sticky? error status bits, providing the platform software architect with free choice between binit# and a general hard reset to recover from a hung system. although binit# will not clear any configurat ion status from the system, it is not a recoverable event from which the platform may continue normal execution without first running a hard reset cycle. to guarantee that the fsb is cleared of any hang condition, the mch will clear all pending transaction states within its internal buffers. this applies to outstanding fsb cycles as required, but also to in-flight memory transactions and inbound transactions. the resulting state of the platform will be highly variable depending upon what precisely got wiped-out due to the binit# event, and it is not possible for hardware to guarantee that the resulting state of the machine will support continued operation. what the mch will guar antee is that no subordinate device has been reset due to this event (pci express lin ks will remain ?up?), and that no internal configuration state (sticky or otherwise) ha s been lost. the mch will also continue to maintain main memory via the refresh mechanism through a binit# event, thus machine-check software will have access not only to machine state, but also to memory state in tracking-down the source of the error. 5.15.5 reset sequencing figure 5-27, ?power-on reset sequence? on page 366 contains a timing diagram illustrating the progression through the power-on reset sequence. this is intended as a quick reference for system designers to clarify the requirements of the mch. note the breaks in the clock waveform at the top of figure 5-27 , which are intended to illustrate further elapsed time in the interest of displaying a lengthy sequence in a single picture. each of the delays in the rese t sequence is of fixed duration, enforced by either the mch or the intel 631xesb/632xes b i/o controller hub. in the case of a power-on sequence, the mch internal ?hard? and ?core? resets deassert simultaneously. the two lines marked with names beginning ?hla? illustrate the esi special cycle handshake between the mc h and the intel 631xesb/632xesb i/o controller hub to coordinate across the dea sserting edge of the fsbxreset# output from the mch. ta b l e 5 - 1 9 summarizes the durations of the various reset stages illustrated above, and attributes the delays to the component that enforces them. the fixed delays provide time for subordinate pll circuitry to lock on interfaces where the clock is withheld or resynchronized during the reset sequence.
functional description 366 intel ? 5000x chipset memory controller hub (mch) datasheet 5.16 smbus interfaces description the intel 5000x chipset mch provides six fully functional system management bus (smbus) revision 2.0 compliant target interf aces. these interfaces are used to support platform level operations such as fb-dimm memory serial presence detect, pci hot- plug, and configuration of platform devices. each of these interfaces have dedicated uses as shown in figure 5-28 . figure 5-27. power-on reset sequence table 5-19. reset sequences and durations from to duration source comment power on pwrgd >2 ms platform control logic on the platform must ensure that there are at least 2 ms of stable power before pwrgd is asserted. pwrgd rstin# deassertion 1ms intel 631xesb/ 632xesb i/o controller hub intel 631xesb/632xesb i/o controller hub enforces delay between detecting pwrgd asserted and releasing pcirst# (note that intel 631xesb/ 632xesb i/o controller hub pcirst# is directly connected to mch rstin#). rstin# deassertion hard/core deassertion 4-6 hclk mch mch waits for a common rising edge on all internal clocks, then releases core reset(s). rstin# deassertion fsbxreset# deassertion 1 ms mch mch enforces delay between rstin# and fsbxreset# deassertion. esi handshake is incremental to the timer. hclk rstin# hard_reset core_reset hla_rstdonecomp cpurst# 4-6 hclk 1 ms hla_cpurstdone pwrgd cold_reset 1 ms
intel ? 5000x chipset memory controller hub (mch) datasheet 367 functional description sm buses 1, 2, 3 and 4 are dedicated to memory serial presence detect and fb-dimm configuration. each bus is dedicated to a single fb-dimm channel. sm bus 1 is assigned to fb-dimm channel 0, sm bus 2 is assign ed to fb-dimm channel 1, sm bus 3 is assigned to fb-dimm channel 2, and sm bus 4 is assigned to fb-dimm channel 3. sm bus 6 is used to support pci express hot-plug. the each smbus interface consists of two interface pins; one a clock, and the other serial data. multiple initiator and target devi ces may be electrically present on the same pair of signals. each target recognizes a start signaling semantic, and recognizes its own 7-bit address to identify pertinent bus traffic. the mch address is hard-coded to 01100000b (60h). the smbus protocol allows for traffic to stop in ?mid sentence,? re quiring all targets to tolerate and properly ?clean up? in the even t of an access sequence that is abandoned by the initiator prior to normal completion. the mch is compliant with this requirement. the protocol comprehends ?wait states? on read and write operations, which the mch takes advantage of to keep the bus busy du ring internal configuration space accesses. 5.16.1 internal access mechanism all smbus accesses to internal register space are initiated via a write to the cmd byte. any register writes received by the mch wh ile a command is already in progress will receive a nak to prevent spurious operation. the master is no longer expected to poll the cmd byte to prevent the obliteration a command in progress prior to issuing further writes. the smbus access will be delayed by stretching the clock until such time that the data is delivered. note that per the system management bus (smbus) specification, rev 2.0 , this can not be longer than 25 ms. to set up an internal access, the four addr bytes are programmed followe d by a command indicator to execute a read or write. depending on the type of acce ss, these four bytes indicate either the bus number, device, function, extended register offset, and register offset, or the memory-mapped region selected and the addr ess within the region. the configuration type access utilizes the traditional bus numb er, device, function, and register offset; but in addition, also uses an extended register offset which expands the addressable register space from 256 bytes to 4 k ilobytes. the memory-mapped type access redefines these bytes to be a memory-mapped region selection byte, a filler byte which is all zeroes, and then the memory address within the region. refer to the earlier figure 5-28. mch sm bus interfaces intel? 5000p chipset (mch) jtag sm bus 0 sm bus 1 sm bus 2 sm bus 6 a ster: spd ave: sm bus a ster: pci-e o t-plug vpi sm bus 3 sm bus 4
functional description 368 intel ? 5000x chipset memory controller hub (mch) datasheet tables, which display this information. note that the filler byte is not utilized, but enforces that both types of accesses have th e same number of address bytes, and does allow for future expansion. it is perfectly legal for an smbus access to be requested while an fsb-initiated access is already in progress. the mch supports ?wait your turn? arbitration to resolve all collisions and overlaps, such that the access that reaches the configuration ring arbiter first will be serviced first while the conflicting access is held off. an absolute tie at the arbiter will be resolved in favor of the fsb. note that smbus accesses must be allowed to proceed even if the internal mch transa ction handling hardware and one or more of the other external mch interfaces are hung or otherwise unresponsive. 5.16.2 smbus transaction field definitions the smbus target port has it?s own set of fi elds which the mch sets when receiving an smbus transaction. they are not directly accessible by any means for any device. ta b l e 5 - 2 0 indicates the sequence of data as it is presented on the smbus following the byte address of the mch itself. note that the fields can take on different meanings depending on whether it is a configur ation or memory-mapped access type. the command indicates how to interpret the bytes. 5.16.2.1 command field the command field indicates the type and size of transfer. all configuration accesses from the smbus port are initiated by this field. while a command is in progress, all future writes or reads will be negative ackn owledged (nak) by the mch to avoid having registers overwritten while in use. the two command size fields allows more flexibility on how the data payload is transferred, both internally and externally. the begin and end bits support the breaking of the transact ion up into smaller transfers, by defining the start and finish of an overall transfer. table 5-20. smbus transaction field summary position mnemonic field name 1cmdcommand 2 bytcnt byte count 3 addr3 bus number (register mode) or de stination memory (memory mapped mode) 4 addr2 device / function number (register mode) or address offset [23:16] (memory mapped mode) 5 addr1 extended register number (register mode) or address offset [15:8] (memory mapped mode) 6 addr0 register number (register mode) or ad dress offset [7:0] (memory mapped mode) 7 data3 fourth data byte [31:24] 8 data2 third data byte [23:16] 9 data1 second data byte [15:8] 10 data0 first data byte [7:0] 11 sts status, only for reads
intel ? 5000x chipset memory controller hub (mch) datasheet 369 functional description 5.16.2.2 byte count field the byte count field indicates the number of bytes following the byte count field when performing a write or when setting up for a read. the byte count is also used, when returning data, to indicate the number of bytes (including the status byte) which are returned prior to the data. note that the byte count is only transmitted for block type accesses on smbus. smbus word or byte accesses do not use the byte count. 5.16.2.3 address byte 3 field this field should be programmed with the bus number of the desired configuration register in the lower 5 bits for a config uration access. for a memory-mapped access, this field selects which memory-map region is being accessed. there is no status bit to poll to see if a transfer is in progress, beca use by definition if the transfer completed when the task is done. clock stretch is used to guarantee the transfer is truly complete. the mch does not support access to other logical bus numbers via the smbus port. all registers ?attached? to the smbus have access to all other registers that are on logical bus#0. the mch makes use of this knowledg e to implement a modified usage of the bus number register providing access to internal registers outside of the pci compatible configuration window. position description 7 begin transaction indicator. 0 = current transaction is not the first of a read or write sequence. 1 = current transaction is the first of a read or write sequence. on a single transaction sequence this bit is set along with the end transaction indicator. 6 end transaction indicator. 0 = current transaction is not the la st of a read or write sequence. 1 = current transaction is the last of a read or write sequence. on a single transaction sequence this bit is set along with the begin transaction indicator. 5 address mode. indicates whether memory or config uration space is being accessed in this smbus sequence. 0 = memory mapped mode 1 = configuration register mode 4 packet error code (pec) enable. wh en set, each transaction in the sequence ends with an extra crc byte. the mch would check for crc on writ es and generate crc on reads. pec is not supported by the mch. 0 = disable 1 = not supported 3:2 internal command size. all accesses are naturally aligned to the access width. this field specifies the internal command to be issued by the smbus slave logic to the mch core. 00 = read dword 01 = write byte 10 = write word 11 = write dword 1:0 smbus command size. this field specifies the smbus command to be issued on the smbus. this field is used as an indication of the length of the transfer so th at the slave knows when to expect the pec packet (if enabled). 00 = byte 01 = word 10 = dword 11 = reserved position description 7:0 byte count. number of bytes following th e byte count for a transaction.
functional description 370 intel ? 5000x chipset memory controller hub (mch) datasheet 5.16.2.4 address byte 2 field this field indicates the device number and function number of the desired configuration register if for a configuratio n type access, otherwise it should be set to zero. 5.16.2.5 address byte 1 field this field indicates the upper address bi ts for the 4k region specified by the register offset. only the lower bit positions of this field are used, the upper four bits are ignored. 5.16.2.6 address byte 0 field this field indicates the lower eight address bits for the register with the 4k region, regardless whether it is a configurat ion or memory-map type of access. 5.16.2.7 data field this field is used to receive read data or to provide write data associated with the addressed register. at the completion of a read command, this field will contain the data retrieved from the addressed register. all reads will return an entire aligned dword (32 bits) of data. for write operations, the number of byte(s) of th is 32 bit field is loaded with the desired write data. for a byte write only bits 7:0 will be used, for a word write only bits 15:0 will be used, and for a dword write all 32 bits will be used. position configuration register mode description memory mapped mode description 7:5 ignored. memory map region to access. 01h = dma 08h = ddr 09h = chap others = reserved 4:0 bus number. must be zero: the smbus port can only access devices on the mch and all devices are bus zero. position configuration register mode desc ription memory mapped mode description 7:3 device number. can only be devices on the mch. zeros used for padding. 2:0 function number. position description 7:4 ignored. 3:0 extended register number. upper address bits for the 4k region of register offset. position description 7:0 register offset. position description 31:24 byte 3 (data3). data bits [31:24] for dword. 23:16 byte 2 (data2). data bits [23:16] for dword. 15:8 byte 1 (data1). data bits [15:8] for dword and word. 7:0 byte 0 (data0). data bits [7:0] for dword, word and byte.
intel ? 5000x chipset memory controller hub (mch) datasheet 371 functional description 5.16.2.8 status field for a read cycle, the returned data is preceded by one byte of status. the following table shows how the status byte bits are defined. 5.16.2.9 unsupported access addresses it is possible for an smbus master to program an unsupported bit combination into the addr registers. the mch does not support such usage, and may not gracefully terminate such accesses. 5.16.3 smb transaction pictographs the intel 5000x chipset mch sm bus target interface is targeted to enterprise domains. the enterprise domain is an extension of the original smbus desktop domain. the following drawings are included to descr ibe the smbus enterprise transactions. i position description 7 internal time-out. 0 = smbus request is completed within 2 ms internally 1 = smbus request is not completed in 2 ms internally. 6 ignored. 5 internal master abort. 0 = no internal master abort detected. 1 = detected an internal master abort. 4 internal target abort. 0 = no internal target abort detected. 1 = detected an internal target abort. 3:1 ignored. 0 successful. 0 = the last smbus transaction was not completed successfully. 1 = the last smbus transaction was completed successfully. figure 5-29. dword configuration read pr otocol (smbus block write / block read, pec disabled) figure 5-30. dword configuration write protocol (smbus block write, pec disabled) s 0110_000 w a cmd = 11000010 a sr 0110_000 r a byte count = 5 a status a data[31:24] a data[23:16] a data[15:8] a data[7:0] s 0110_000 w a cmd = 11000010 a byte count = 4 a bus number a device/function a reg number[15:0] a reg number [7:0] clock stretch a p n p a s 0110_000 w a cmd = 11001110 a byte count = 8 a bus number a device/function a reg number[15:8] a reg number [7:0] a data[31:24] data[23:16] a data[16:8] a data[7:0] cl ock st ret ch a p
functional description 372 intel ? 5000x chipset memory controller hub (mch) datasheet figure 5-31. dword memory read protocol (smbus bloc k write / bock read, pec disabled) figure 5-32. dword memory write protocol figure 5-33. dword configuration read pr otocol (smbus word write / word read, pec disabled) figure 5-34. dword configuration write prot ocol (smbus word write, pec disabled) s 0110_000 w a cmd = 11100010 a byte count = 4 a destination mem a add offset[23:16] a add offset[15:8] a s 0110_000 w a cmd = 11100010 a sr 0110_000 r a byte count = 5 a status a data[31:24] a data[23:16] a data[15:8] a data[7:0] n p add offset[7:0] cl ock st ret ch a p a s 0110_000 w a cmd = 11101110 a byte count = 8 a destination mem a add offset[23:16] a add offset[15:8] a add ofset[7:0] data[23:16] a data[16:8] a data[7:0] c l oc k st ret ch a p a data[31:24] s 0110_000 w a cmd = 10000001 a bus number a device/function s 0110_000 w a cmd = 01000001 a register num[15:8] a p s 0110_000 w a cmd = 10000001 sr 0110_000 r a status s 0110_000 w a cmd = 00000001 a sr 0110_000 r a data[23:16] a data[15:8] p a a data[31:24] p a register num[7:0] cl ock st retch a p s 0110_000 w a cmd = 01000000 a sr 0110_000 r a data[7:0] p n n n s 0110_000 w a cmd = 10001101 a bus number a device/function s 0110_000 w a cmd = 00001101 a register num[15:8] a p a register num[7:0] a p clock st ret ch a p s 0110_000 w a cmd = 00001101 a data[31:24] a data[23:16] a p s 0110_000 w a cmd = 01001101 a data[15:8] a data[7:0] s 0110_000 w a cmd = 10101101 a dest mem a add offset[23:16] s 0110_000 w a cmd = 00101101 a add offset[15:8] a p a add offset[7:0] a p cl ock st ret ch a p s 0110_000 w a cmd = 00101101 a data[31:24] a data[23:16] a p s 0110_000 w a cmd = 01101101 a data[15:8] a data[7:0]
intel ? 5000x chipset memory controller hub (mch) datasheet 373 functional description 5.16.4 slave sm bus, sm bus 0 system management software in a intel 5000x chipset platform can initiate system management accesses to the configuration registers via the slave sm bus, sm bus 0. the mechanism for the server management (sm) software to access configuration registers is through a smbus specification, revision 2.0 compliant slave port. some intel 5000x chipset components contain this slave port and allow accesses to their configuration registers. the product specif ic details are compatible with the intel 631xesb/632xesb i/o controller hub smbus configuration access mechanism. most of the intel 5000x chipset mch registers can be accessed through the smbus configuration mechanism. smbus operations are made up of two major steps: 1. writing information to registers within each component 2. reading configuration registers from each component. the following sections will describe the protocol for an smbus master to access a intel 5000x chipset platform component?s internal configuration registers. refer to the smbus specification, revision 2.0 for the bus protocol, timings, and waveforms. figure 5-35. dword memory read protocol (smbus word write / word read, pec disabled) figure 5-36. word configurat ion wrote protocol (smbus byte write, pec disabled) s 0110_000 w a cmd = 10100001 a dest mem a add offset[23:16] s 0110_000 w a cmd = 01100001 a add offset[15:8] p s 0110_000 w a cmd = 10100001 sr 0110_000 r a status s 0110_000 w a cmd = 00100001 a sr 0110_000 r a data[23:16] a data[15:8] n p a a data[31:24] n p a add offset[7:0] cl ock st retch a p s 0110_000 w a cmd = 01100000 a sr 0110_000 r a data[7:0] p a n s 0110_000 w a cmd = 10001000 a bus number device/function s 0110_000 w a cmd = 00001000 a register num[15:8] a p a p clock stretch a p s 0110_000 w a cmd = 00001000 a data[w:x] a p s 0110_000 w a cmd = 01001000 a data[y:z] s 0110_000 w a cmd = 00001000 a p a s 0110_000 w a cmd = 00001000 a register num[7:0] a p
functional description 374 intel ? 5000x chipset memory controller hub (mch) datasheet each component on the intel 5000x chipset platform must have a unique address. intel 5000x chipset platform component addresses are defined in the following table. 5.16.4.1 supported smbus commands product name components smbus rev. 2.0 sl ave ports support the following six smbus commands: sequencing these commands will initiate internal accesses to the component?s configuration registers. each configuration read or write first consists of an smbus write sequence which initializes the bus number, device number, and so forth. the term sequence is used since these variables may be written with a single block write or multiple word or byte writes. once these parameters are initializ ed, the smbus master can initiate a read sequence (which perform a configuration read ) or a write sequence (which performs a configuration write). each smbus transaction has an 8-bit command driven by the master. the format for this command is illustrated in ta b l e 5 - 2 2 below. the begin bit indicates the first transaction of a read or write sequence. the end bit indicates the last transaction of a read or write sequence. the pecan bit enables the 8-bit packet error code (pec) generation and checking logic. the internal command field specifies the internal command to be issued by the smbus slave logic. note that the internal command must remain consistent during a sequence that accesses a configuration register. operation cannot be guaranteed if it is not consistent when the command setup sequence is done. the smbus command field specifies the smbus command to be issued on the bus. this field is used as an indication of the leng th of transfer so the slave knows when to expect the packet error code packet. reserved bits should be written to zero to preserve future compatibility. table 5-21. smbus address for product name platform component smbus address (7:1) intel 5000x chipset mch 1100_000 ? block write ? word write ? byte write ? block read ? word read ? byte read table 5-22. smbus command encoding 7654 3:2 1:0 begin end rsvd pec_en internal command: 00 - read dword 01 - write byte 10 - write word 11 - write dword smbus command: 00 - byte 01 - word 10 - block 11 - rsvd
intel ? 5000x chipset memory controller hub (mch) datasheet 375 functional description 5.16.4.2 configuration register read protocol configuration reads are accomplished through an smbus write(s) and later followed by an smbus read. the write sequence is used to initialize the bus number, device, function, and register number for the configuration access. the writing of this information can be accomplished through any combination of the supported smbus write commands (block, word or byte). the internal command field for each write should specify read dword. after all the information is set up, the last write ( end bit is set) initiates an internal configuration read. if the data is not availa ble before the slave interface acknowledges this last write command (ack), the slave w ill ?clock stretch? until the data returns to the smbus interface unit. if an error occurs during the internal access, the last write command will receive a nak. a status field indicates abnormal termination and contains status information such as target abort, master abort, and time-outs. the status field encoding is defined in the following table. examples of configuration reads are illustra ted below. all of these examples have packet error code (pec) enabled. if the mast er does not support pec, then bit 4 of the command would be cleared and there would not be a pec phase. for the definition of the diagram conventions below, refer to the smbus specification , revision 2.0. for smbus read transactions, the last byte of data (or the pec byte if enabled) is naked by the master to indicate the end of the transaction. for diagram compactness, ?register number[]? is also sometimes referred to as ?reg number? or ?reg num?. this is an example using word read s. the final data is a byte read. table 5-23. status field encoding for smbus reads bit description 7 internal time-out. this bit is set if an smbus request is not completed in tbd internally (2ms?) 6 reserved 5 internal master abort 4 internal target abort 3:1 reserved 0 successful figure 5-37. smbus configuration read (block write / block read, pec enabled) s 11x0_xxx w a cmd = 11010010 a sr 11x0_xxx r a byte count = 5 a status a data[31:24] a data[23:16] a data[15:8] a data[7:0] a s 11x0_xxx w a cmd = 11010010 a byte count = 4 a bus number a device/function a reg number[7:0] a reg number [15:8] a pec clock stretch a p pec n p smbus read smbus write
functional description 376 intel ? 5000x chipset memory controller hub (mch) datasheet the following example uses byte reads. 5.16.4.3 configuration register write protocol configuration writes are accomplished through a series of smbus writes. as with configuration reads, a write sequence is firs t used to initialize the bus number, device, function, and register number for the configuration access. the writing of this information can be accomplished through any combination of the supported smbus write commands (block, word or byte). examples of configuration writes are illustrate d below. for the definition of the diagram conventions below, refer to the smbus specification , revision 2.0. figure 5-38. smbus configuration read (w ord writes / word reads, pec enabled) s 11x0_xxx w a cmd = 10010001 a bus number a device/function a pec s 11x0_xxx w a cmd = 01010001 a register number[15:8] a a p s 11x0_xxx w a cmd = 00010001 sr 11x0_xxx r a data[23:16] s 11x0_xxx w a cmd = 01010000 a sr 11x0_xxx r a data[7:0] a pec n p a a data[15:8] a pec n p register number[7:0] a pec clock stretch a p s 11x0_xxx w a cmd = 10010001 sr 11x0_xxx r a status a a data[31:24] a pec n p figure 5-39. smbus configuration read (w rite bytes / read bytes, pec enabled) s 11x0_xxx w a cmd = 10010000 a bus number a pec a p s 11x0_xxx w a cmd = 00010000 a device/function a pec a p s 11x0_xxx w a cmd = 01010000 a register[7:0] a pec s 11x0_xxx w a cmd = 00010000 sr 11x0_xxx r a data[31:24] s 11x0_xxx w a cmd = 00010000 a sr 11x0_xxx r a data[23:16] a pec n p s 11x0_xxx w a cmd = 00010000 a sr 11x0_xxx r a data[15:8] a pec n p s 11x0_xxx w a cmd = 01010000 a sr 11x0_xxx r a data[7:0] a pec n p a clock stretch a p a pec n p s 11x0_xxx w a cmd = 10010000 sr 11x0_xxx r a status a a pec n p s 11x0_xxx w a cmd = 00010000 a register[15:8] a pec a p figure 5-40. smbus configuration write (block write, pec enabled) a s 11x0_xxx w a cmd = 11011110 a byte count = 8 a bus number a device/function a reg number[15:8] a reg number [7:0] a data[31:24] data[23:16] a data[16:8] a data[7:0] a pec clock stretch a p
intel ? 5000x chipset memory controller hub (mch) datasheet 377 functional description 5.16.4.4 smbus error handling the smbus slave interface handles two types of errors: internal and pec. for example, internal errors can occur when the intel 5000p chipset issues a configuration read on the pci express port that read?s terminates in error. these errors manifest as a not- acknowledge (nak) for the read command ( end bit is set). if an internal error occurs during a configuration write, the final writ e command receives a nak just before the stop bit. if the master receives a nak, the entire configuration transaction should be reattempted. if the master supports packet error checki ng (pec) and the pec_en bit in the command is set, then the pec byte is checked in th e slave interface. if the check indicates a failure, then the slave will nak the pec packet. 5.16.4.5 smbus interface reset ? the slave interface state machine can be reset by the master in two ways: ? the master holds scl low for 25 ms cumulative. cumulative in this case means that all the ?low time? for scl is counted between the start and stop bit. if this totals 25 ms before reaching the stop bit, the interface is reset. ? the master holds scl continuously high for 50 ms. note: since the configuration registers are affected by the reset pin, smbus masters will not be able to access the internal registers while the system is reset. figure 5-41. smbus configuration write (word writes, pec enabled) figure 5-42. smbus configuration write (write bytes, pec enabled) s 11x0_xxx w a cmd = 10011101 a bus number a device/function a pec a p s 11x0_xxx w a cmd = 00011101 a register[15:8] a register[7:0] a pec s 11x0_xxx w a cmd = 00011101 a data[31:24] a data[23:16] a pec a p s 11x0_xxx w a cmd = 01011101 a data[15:8] a a p data[7:0] a pec a p s 11x0_xxx w a cmd = 10011100 a bus number a pec a p s 11x0_xxx w a cmd = 00011100 a device/function a pec a p s 11x0_xxx w a cmd = 00011100 a register[15:8] a pec a p s 11x0_xxx w a cmd = 01011100 a data[7:0] a pec a p s 11x0_xxx w a cmd = 00011100 a data[31:24] a pec a p s 11x0_xxx w a cmd = 00011100 a data[23:16] a pec a p s 11x0_xxx w a cmd = 00011100 a data[15:8] a pec a p s 11x0_xxx w a cmd = 00011100 a register[7:0] a pec a p
functional description 378 intel ? 5000x chipset memory controller hub (mch) datasheet 5.16.5 fb-dimm spd interface, sm buses 1, 2, 3 and 4 the mch integrates a 100 khz spd controller to access the fb-dimm configuration information. smbus 1 is dedicated to fb-dim m branch 0, channel 0 dimms. smbus 2 is dedicated to fb-dimm branch 0, channel 1 dimms. smbus 3 is dedicated to fb-dimm branch 1, channel 0 dimms and smbus 4 is dedicated to fb-dimm branch 1, channel 1 dimms. there can be a maximum of four spd eeprom?s associated with each spd bus. the fb-dimm spd interfaces are wired as depicted in figure 5-8 . board layout must map chip selects to spd slave addresses as shown in ta b l e 5 - 7 . the slave address is written to the spdcmd configuration register. 5.16.5.1 spd asynchronous handshake the spd bus is an asynchronous serial interface. once software issues an spd command (spdcmd.cmd = spdw or spdr), software is responsible for verifying command completion before another spd command can be issued. software can determine the status of an spd command by observing the spd configuration register. an spd command has completed when any one command completion field (rdo, wod, sbe) of the spd configuration register is observed set to 1. an spdr command has successfully completed when the rdo field is observed set to 1. an spdw command has successfully completed when the wod fiel d is observed set to 1. an unsuccessful command termination is observed when the sb e field is set to 1. the mch will clear the spd configuration register command completion fields automatically whenever an spdr or spdw command is initiated. polling may begin immediately after initiating an spd command. software can determine when an spd comma nd is being performed by observing the busy field of the spd configuration register. when this configuration bit is observed set to 1, the interface is executing a command. valid spd data is stored in the data field of the spd configuration register upon successful completion of the spdr command (i ndicated by 1 in the rdo field). data to be written by an spdw command is plac ed in the data field of the spdcmd configuration register. unsuccessful command termination will occu r when an eeprom does not acknowledge a packet at any of the required ack points , resulting in the sbe field being set to 1. 5.16.5.2 request packet for spd random read upon receiving the spdr command, the mc h generates the random read register command sequence as shown in figure 5-43 . the returned data is then stored in the mch spd configuration register in bits [7:0], and the rdo field is set to 1 by the mch to indicate that the data is present and that the command has completed without error. figure 5-43. random byte read timing slave address byte address slave address data a c k b a 7 r / w a 2 d t i 0 d t i 1 d t i 2 d t i 3 d t i 3 d t i 2 a c k b a 0 b a 1 b a 2 b a 3 b a 4 b a 5 b a 6 a c k d t i 0 d t i 1 n a c k r / w s a 1 s a 0 s a 2 s a 1 s a 0 s s t a r t s t a r t s t o p 0 1
intel ? 5000x chipset memory controller hub (mch) datasheet 379 functional description 5.16.5.3 request packet for spd byte write upon receiving the spdw command, the mch generates the byte write register command sequence as shown in figure 5-44 . the mch indicates that the sio command has completed by setting the wod bit of the spd configuration register to 1. 5.16.5.4 spd protocols the mch supports the spd protocols shown in ta b l e 5 - 2 4 . 5.16.5.5 spd bus time-out if there is an error in the transaction, such that the spd eeprom does not signal an acknowledge, the transaction will time out. the mch will discard the cycle and set the sbe bit of the spd configuration register to 1 to indicate this error. the time-out counter within the mch begins counting after the last bit of data is transferred to the dimm, while the mch waits for a response. 5.16.6 pci express hot-pl ug support, sm bus 6 sm bus 6 is the pci express hot-plug port. sm bus 6 is a hot-plug virtual pin port (vpp) that operates using the sm bus masters protocol as defined in system management bus specification 2.0 . sm bus 6 is dedicated to support pci ex press hot-plug devices. support for pci express is an option described in pci express base specification , revision 1.0a. the pci express hot-plug model implies a hot-plug controller per port which is identified to software as a capability of the p2p bridge configuration space. pci express hot-plug support requires that the intel 5000x chipset mch supports a set of hot-plug messages (listed in figure 5-15 and figure 5-21 ) to manage the states between the hot-plug controller and the device. the pci express form factor has an impact to the level of support required of the mch. for example, some of the hot-plug messages are required only if the led indicators reside on the actual card and are accessed through the endpoint device. the intel 5000x chipset mch supports all of the hot-pl ug messages so that the platform is not constrained to any particular form factor. figure 5-44. byte write register timing a c k b a 7 r / w s a 0 s a 1 s a 2 d t i 0 d t i 1 d t i 2 d t i 3 s t a r t a c k b a 0 b a 1 b a 2 b a 3 b a 4 b a 5 b a 6 a c k s t o p slave address byte address data 0 table 5-24. mch supp orted spd protocols mch supported spd protocols random byte read byte write
functional description 380 intel ? 5000x chipset memory controller hub (mch) datasheet a standard hot-plug usage model is benefici al to customers who buy systems with hot- plug slots because many customers utilize hardware and software from different vendors. a standard usage model allows customers to use the pci hot-plug slots on all of their systems without having to retrain operators. in order to define a programming model for the pci standard hot-plug controller (shpc), it is necessary to make some assumptions about the interface between a human operator and a hot-plug slot. the shpc programming model includes two indicators, one optional push button, and a sensor on the manually-operated retention latch for each supported slot. 5.16.6.1 hot-plug indicators the standard usage model assumes that the platform provides two indicators per slot (the power indicator and the attention indicator). each indicator is in one of three states: on, off, or blinking. hot-plug system software has exclusive control of the indicator states by issuing commands to the shpc. the shpc controls blink frequency, duty cycl e, and phase. blinking indicators operate at a frequency of 1.5 hz and 50% (+/- 5%) du ty cycle. both indicators are completely under the control of system software. 5.16.6.2 attention button an attention button is a momentary-contact push-button, located adjacent to each hotplug slot, that is pressed by the user to initiate a hot-insertion or a hot-removal at that slot. the power indicator provides visual feedback to the human operator (if the system software accepts the request initia ted by the attention button) by blinking. once the power indicator begins blinking, a 5- second abort interval exists during which a second depression of the attention button cancels the operation. software has the responsibility to implement this 5-second abort interval. 5.16.7 hot-plug controller pci express hot-plug requires that the intel 5000x chipset mch implement a hot-plug controller for every hot-pluggable interface. the hot-plug controller is a capability of the bridge configuration space and the register set is accessible through the standard pci capability mechanism defined in the pci express base specification , revision 1.0a. details on hot-plug operation and flow will be described in the intel 5000p chipset software programmer?s guide . 5.16.8 pci express ho t-plug usage model not all concepts from the pci standard hot-pl ug definition apply directly to pci express interfaces. the pci express specification still calls for an identical software interface in order to facilitate adoption with minimal de velopment overhead on this aspect of the implementation. the largest variance from th e old pci hot-plug model is in control of the interface itself. pci required arbitr ation support for idlin g already connected components, and ?quick switches? to isolate the bus interface pins of a hot-plug slot. pci express is a point-to-point interface, making hot-plug a degenerate case of the old model that doesn?t require such arbiter support. furthermore, the pci express interface is inherently tolerant of hot conn ect or disconnect, and does not have explicit clock or reset pins defined as a part of the bus (although they are standard pieces of some defined pci express connector form factors). as a result of these differences, some of the inherited hot-plug command and status codes are misleading when applied to pci express.
intel ? 5000x chipset memory controller hub (mch) datasheet 381 functional description the compatible set of hot-plug regist ers may be accessed via memory-mapped transactions, or via the intel 5000x chipset mch configuration mechanism as defined in the configuration mechanism chapter of th is document. for specific information on the hot-plug register set, refer to the chapter on configuration register details. the messages used for the hot-plug model are listed in table 5-15, ?pci express hot- plug interrupt flow? on page 343 and table 5-19, ?mch to intel 631xesb/632xesb i/o controller hub port configurations? on page 352 describe the behavior of the button and leds. 5.16.9 virtual pin ports shown in the figure 5-1 is a high level block diagram of virtual pin ports and theoretical maximum number of pci express card slots that could be supported for hot-plug operations. in this vpp usage model, 16 slots (max) are shown in figure 5-1 but for the intel 5000p chipset platform only 6 pci express slots 1 will be used for the i/o hot-plug operations. note: port 0, the esi slot, is not hot-pluggable. since intel 5000x chipset mch has only six pci express ports, only six hot-plug slots should be present in a intel 5000x chipse t mch platform. intel 5000x chipset mch pci express virtual pin port will only process six hot-plug slots accordingly. 1. this does not include the esi (port 0) which is not hot-pluggable.
functional description 382 intel ? 5000x chipset memory controller hub (mch) datasheet the intel 5000x chipset mch masters a 100k hz hot-plug smbus interface thru pins gpiosmbclk,and gpiosmbdata, for pci expr ess ports that connect to a variable number of serial to parallel i/o ports such as the phillips pca9555 1 i/o extender. the intel 5000x chipset mch only supports smbus devices with registers mapped as per ta b l e 5 - 2 5 . these i/o extender components have 16 i/os, divided into two 8-bit ports that can be configured as inputs or outputs. the intel 5000x chipset mch has a crossbar which associates each pci express ho t-plug unit (hpu) slots with one of these 8-bit ports. the mapping is defined by a virtual pin port register field, pexctrl.vpp, for each of the pci express hpu slots. the vpp register holds the smbus address and port number of the io port associated with the pci express hpu. a[2:0] pins on each i/o extender (that is, pca9555 or compatible components) connected to the intel 5000x chipset mch must strapped uniquely. ta b l e 5 - 2 6 defines how the eight hot-plug signals are mapped to pins on the vpp. figure 5-1. pci express hot-plug/vpp block diagram i/o extender 1 i/o extender 7 i/o extender 0 vpp 100k hz sm bus slot 0 pex root port (p2p bridge, hpc) ich6/esb msi intx intel ? 5000p chipset fsb 0 board power manager button led button led button led button led button led button led a2 a1 a0 slot 1 slot 2 slot 3 slot 14 slot 15 fsb 1 a2 a1 a0 1. intel 5000x chipset mch vpp supports pca9555 or compatible i/o extender only.
intel ? 5000x chipset memory controller hub (mch) datasheet 383 functional description . 5.16.9.0.1operation when the intel 5000x chipset mch comes out of reset, the i/o ports are inactive. after a reset, the intel 5000x chipse t mch is not aware of how many io ports are connected to it, what their addresses are, nor what pc i express ports are hot-pluggable. the intel 5000x chipset mch does not master any commands on the smbus until a hot-plug capable bit is set. for a pci express slot, an additional dis_vpp bit is used to differentiate card or module hot-plug support, dis_vpp bit needs to be se t to 0 to enable hot-plug support for pci express card slot. when bios sets a hot-plug capable bit (pexslotcap.hpc and pexctrl.dis_vpp for pci express; hpctl.hpc for fb-dimm hpu), the intel 5000x chipset mch initializes the associated vpp with direction and voltage logic level configuration as per ta b l e 5 - 2 6 . vpp registers for pci express which do not have the hot-plug capable bit set are invalid. additionally, if the dis_vpp bi t is set to 1, then the corresponding vpp register is invalid for the pci express slot. this is intended for pci express module hot- plug which no vpp support is required. the i/o extender?s polarity is left at its default value and never written, but the direction and voltage logic levels are written using the addresses defined in ta b l e 5 - 2 6 . when the intel 5000x chipset mch is not do ing a direction write, it performs input register reads and output register writes to all valid vpps. this sequence repeats indefinitely until a new hot-plug capability bit is set. to minimize the completion time of this sequence and minimize complexity, both ports are always read or written. for the maximum number of 6 io ports, and assuming no clock stretching, this sequence can take up to 51ms. if new hot- plug capability bits are not being set, this is the maximum timing uncertainty in sampling or driving these signals. ta b l e 5 - 2 6 describes the hot-plug signals used for hot-plug. table 5-25. i/o port registers in i/o extend er supported by inte l 5000x chipset mch register name intel 5000x chipset mch usage 0 input port 0 continuously reads input values 1input port 1 2 output port 0 continuously writes output values 3output port 1 4 polarity inversion port 0 not wr itten by intel 5000x chipset mch 5 polarity inversion port 1 6 configuration port 0 direction set as per ta b l e 5 - 2 6 7 configuration port 1
functional description 384 intel ? 5000x chipset memory controller hub (mch) datasheet the intel 5000x chipset mch will send a ssert_intx/deassert_intx or assert_hpgpe/ deassert_hpgpe messages to the esi port as virtual pin messages to enable the intel 631xesb/632xesb i/o controller hub take the appropriate action for handling the hot- plug (legacy/acpi interrupt mode) in non-msi mode. 5.17 clocking the following section describes the intel 5000x chipset mch clocks. 5.17.1 reference clocks the busclk, and coreclk (herein referred to ?in aggregate? as ?busclk?) reference clocks, operating at 133/166/266 mhz, are su pplied to the intel 5000x chipset mch. these are the processor bus, core, and snoop filter pll reference clocks. this frequency is common between all processor bus agen ts. phase matching between agents is required. the two processor fsbs operate in phase with the core clock. the fb-dimm(0/1)clk reference clocks, (her ein referred to as fbdclk) operating at half the ddr2 frequency (operating at th e sdram command-clock frequency, which is the fb-dimm packet frequency), are supplied to the intel 5000x chipset mch. this is the fb-dimm pll reference clock. this frequency is common between the intel 5000x chipset mch and dimms. phase matching between agents is not required (plesiochronous). the intel 5000x chipset mch and dimms treat this frequency domain synchronously. the fb-dimm unit-interval (ui) pll outputs 12x the fbdclk frequency. for example, for ddr2 667 mhz dimms, the fbdclk frequency is 333 mhz and the ui (link) frequency is 4.0 ghz. the peclk reference clock, operating at 100 mhz, is supplied to the intel 5000x chipset mch. this is the pci express pll reference clock. the pci express flit pll outputs 250 mhz. the pci express phit pll outputs 2.5 ghz. the phit clock frequency must be tightly matched (mesochronous mode ) between both pci express agents when spectrum-spreading is not employed. the phit clock frequency is common to both pci express agents when spectrum-spreading is employed. when the phit clock frequency table 5-26. hot-plug signals on a virtual pin port bit direction voltage logic level signal logic true meaning logic false meaning 0 output high_true atnled attn led is to be turned on attn led is to be turned off 1 output high_true pwrled pwr led is to be turned on pwr led is to be turned off 2 input low_true button# attn button is pressed attn button is not pressed 3 input low_true pwrflt# pwr fault in the vrm no pwr fault in the vrm 4 input low_true prsnt# card present in slot card not present in slot 5 output high_true pwren power is to be enabled on the slot power is not to be enabled on the slot 6 input low_true mrl# mrl is open mrl is closed 7 input low_true gpi# power good on slot no power good on slot
intel ? 5000x chipset memory controller hub (mch) datasheet 385 functional description is common to both pci express agents, no phase matching between them is required (plesiochronous mode). the intel 5000x chipset mch core treats this frequency domain asynchronously. the busclk and fbdclk reference clocks ar e derived from the same oscillator. the peclk reference clock may be derived from a different oscillator. the pci express interfaces operate asynchro nously with respect to the core clock. table 5-27. intel 5000x chipset mch frequenc ies for processors and core core domain frequency reference clock 133 mhz busclk 133 mhz fsb 1x busclk fsb 2x 266 mhz fsb 4x 533 mhz 266 mhz busclk 266 mhz fsb 1x fsb 2x 533 mhz fsb 4x 1,067 mhz 333 mhz busclk 167 mhz fsb 1x fsb 2x 333 mhz fsb 4x 667 mhz 333 mhz busclk 333 mhz fsb 1x fsb 2x 667 mhz fsb 4x 1333 mhz table 5-28. intel 5000x chipset mch frequencies for memory ddr domain frequency reference clock 533 mhz fbd u 3.2 ghz fbdclk fbd packet 266 mhz fbdclk 133 mhz 667 mhz fbd u 4.0 ghz fbd packet 333 mhz fbdclk 167 mhz 800 mhz fbd u 4.8 ghz fbd packet 400 mhz fbdclk 200 mhz
functional description 386 intel ? 5000x chipset memory controller hub (mch) datasheet 5.17.2 jtag tck is asynchronous to core clock. for private tap register accesses, one tck cycle is a minimum of 10 core cycles. the tck high time is a minimum of 5 core cycles in duration. the tck low time is a minimum of 5 core cycles in duration. the possibility of metastability during private register access is mitigated by circuit design. a metastability hardened synchronizer wi ll guarantee an mtbf greater than 10 7 years. for public tap register accesses, tck operates independently of the core clock. 5.17.3 smbus clock the smbus clock is synchronized to the core clock. data is driven into the intel 5000p chipset with respect to the serial clock sign al. data received on the data signal with respect to the clock signal will be sync hronized to the core using a metastability hardened synchronizer guaranteeing an mtbf greater than 10 7 years. the serial clock can not be active until 10 ms after reseti# deassertion. when inactive, the serial clock should be deasserted (high). the serial clock frequency is 100 khz. 5.17.4 gpio serial bus clock the transmitted 100 khz virtual pin interface (vpi) clock (one of the scl[4:0]?s) is derived from the core clock. the pci express hot-plug signals reside on the virtual pin interface. 5.17.5 clock pins table 5-29. intel 5000x chipset mch frequencies for pci express domain frequency reference clock pci express phit 2.5 ghz peclk pci express flit 250 mhz peclk table 5-30. clock pins (sheet 1 of 2) pin name pin description busclkp processor bus clock busclkn processor bus clock (complement) peclkp pci express clock peclkn pci express clock (complement) fbd{0/1}clkp fb-dimm clocks fbd{0/1}clkn fb-dimm clocks (complement) pllbypass pll bypass mode prcspeed busclk:coreclk bus ratio selector vcc{0/1/2/3}amp analog power supply for fb-dimm plls vss{0/1/2/3}amp analog ground for fb-dimm plls vccapb analog power supply for processor bus pll vssapb analog ground for processor bus pll vccape analog power supply for pci express plls
intel ? 5000x chipset memory controller hub (mch) datasheet 387 functional description 5.17.6 high frequenc y clocking support 5.17.6.1 spread spectrum support the intel 5000x chipset mch plls will suppor t spread spectrum clocking (ssc). ssc is a frequency modulation technique for emi reduction. instead of maintaining a constant frequency, ssc modulates the cloc k frequency/period along a predetermined path, that is, the modulation profile.the intel 5000x chipset mch is designed to support a nominal modulation frequency of 30 khz with a down spread of 0.5%. 5.17.6.2 stop clock plls in the intel 5000x chipset mch cannot be stopped. 5.17.6.3 jitter the fb-dimm ui clocks are produced by plls that multiply the fbdclk frequency by 12. the pci express phit clocks are produced by plls that multiply the peclk frequency by 25. these multi-ghz phit clocks require ultra-clean sources, ruling out all but specifically-crafted low-jitter clock synthesizers. 5.17.6.4 external reference an external crystal oscillator is the prefe rred source for the pll reference clock. a spread spectrum frequency sy nthesizer that meets the jitter input requirements of the pll is acceptable. 5.17.6.5 pll lock time all plls should be locked by pwrgood signal assertion. the reference clocks must be stable 1ms before the assertion of the pwrgood signal. the assertion of the pwrgood signal initiates the pll lock proces s. external clocks dependent on plls are gpio clock and smbus clock. many jtag private registers are dependent on core pll- generated clocks. vssape analog ground for pci express plls vccacore analog power supply for core pll vssacore analog ground for core pll tck tap clock gpioscl gpio (virtual pin port) clock scl smbus clock ocpstbp# debug bus data strobe ocpstbn# debug bus data strobe (complement) pb{0/1}stbp[3:0]# processor bus data strobes pb{0/1}stbn[3:0]# processor bus data strobes (complements) pb{0/1}adstb[1:0]# processor bus address strobes table 5-30. clock pins (sheet 2 of 2) pin name pin description
functional description 388 intel ? 5000x chipset memory controller hub (mch) datasheet 5.17.6.6 other pll characteristics the pll vcos oscillate continually from powe r-up. the pll output dividers consistently track the vco, providing pulses to the cloc k trees. logic that does not receive an asynchronous reset can thus be reset ?synchronously?. a ?locked? pll will only serve to prove that the feedback loop is continuous. it will not prove that the entire clock tree is continuous. 5.17.6.7 analog power supply pins the intel 5000x chipset mch incorporates seven plls. each pll requires an analog vcc and analog vss pad and external lc filt er. therefore, there will be external lc filters for the intel 5000x chipset mch. important: the filter is not to be connected to board vss. the ground connection of the filter will be routed through the package and grounded to on-die vss. 5.17.6.8 i/o interface metastability pci express can be operated frequency-locked to the core. flits are fifteen-sixteenths of the core frequency in 266 mhz mode, th ree-quarters of the core frequency in 333 mhz mode. however, the phase between the frequency-locked domains is not controlled. this scheme results in the possibility of a metast ability resonance where, for example, the commands generated by the core miss setup and hold to i/o every time. this condition can be tolerated by carefully hardened metastability design. 5.18 error list this section provides a summary of errors de tected by the intel 5000x chipset . in the following table, errors are listed by the unit / interfaces. some units / interfaces may provide additional error logging registers. the following table provides the list of detected errors of a the mch. table 5-31. intel 5000x chipset error list (sheet 1 of 7) err # in mch error name definition error type log register cause / actions f1 request/ address parity error mch monitors the address and request parity signals on the fsb. a parity discrepancy over these fields during a valid request. mch only detects this error caused by cpus. fatal ferr_fat_fsb/ nerr_fat_fsb. nrecfsb, nrecfsb_addrh, nrecfsb_addrl for ferr only. complete transaction on fsb with response (non-hard fail response) f2 unsupported request or data size on fsb. mch detected an fsb unsupported transaction. mch only detects this error caused by cpus. fatal ferr_fat_fsb/ nerr_fat_fsb. nrecfsb for ferr only. treat as nop. no data response or retry by mch f5 outstanding deferred fsb transaction has timed out mch detected that a previously deferred fsb txn has not completed with defer reply within a specified time frame. fatal ferr_fat_fsb/ nerr_fat_fsb. nrecfsb for ferr only an access issued on the fsb has timed out.
intel ? 5000x chipset memory controller hub (mch) datasheet 389 functional description f6 data parity error mch monitors the data/ parity signals on the fsb. set when the mch detects an parity error during the data transfer. mch only detects this error caused by cpus. uncorr ferr_nf_fsb/ nerr_nf_fsb. recfsb for ferr only received a parity error. poison data and forward to the appropriate interface. f7 detected mcerr mch detected that a processor issued an mcerr. uncorr ferr_nf_fsb/ nerr_nf_fsb. based on poc[5] setting if (receive an mcerr) forward the mcerr to the other fsb bus, adhering to the mcerr protocol f8 b-init mch detected that a processor issued an b-init. uncorr ferr_nf_fsb/ nerr_nf_fsb. based on poc[5] setting do not propagate to other fsb bus, reset arb. unit, and programatically reset platform f9 fsb protocol error bnd detected fsb protocol error, for example, hitm on bil and hitm on ewb. fatal ferr_fat_fsb/ nerr_fat_fsb. nrecfsb, nrecfsb_addrh, nrecfsb_addrl for ferr only. complete transaction on fsb with response (iwb as in the example) io0 pci express - data link layer protocol error mch detects a dl layer protocol error from the dllp. default= fatal (check uncerr sev) log pex_fat_ferr/nerr or pex_nf_cor_ferr/ nerr based on their respective error types and severity (uncerrsev) log rperrsts for io1, io11 and io17. log uncerrsts for their respective error types. log the first error pointer for uncerrsts in aerrcapctrl. log corrersts for their respective error types. log pexdevsts for io12 and other i/o errors based on uncersev( log header of dllp packet. check corresponding bit in uncerrsev register for severity level (fatal or non fatal) io1 pci express - received fatal error message mch received a fatal error message from the south bridge. fatal log header of packets with errors io2 pci express - received unsupported request received an unsupported request, similar to master abort. default= uncorr (check uncerr sev) log header of packet check corresponding bit in uncerrsev register for severity level (fatal or non fatal) io4 pci express - poisoned tlp received a poisoned transaction layer packet from the south bridge. default= uncorr (check uncerr sev) log header of packets with errors check corresponding bit in uncerrsev register for severity level (fatal or non fatal) io5 pci express - flow control protocol error mch has detected a pci express flow control protocol error default= fatal (check uncerr sev) log header of packets with errors check corresponding bit in uncerrsev register for severity level (fatal or non fatal) table 5-31. intel 5000x chipset error list (sheet 2 of 7) err # in mch error name definition error type log register cause / actions
functional description 390 intel ? 5000x chipset memory controller hub (mch) datasheet io6 pci express - completion time-out pending transaction was acked in the data link layer but not within the time limit. default= uncorr (check uncerr sev) log pex_fat_ferr/nerr or pex_nf_cor_ferr/ nerr based on their respective error types and severity (uncerrsev) log rperrsts for io1, io11 and io17. log uncerrsts for their respective error types. log the first error pointer for uncerrsts in aerrcapctrl. log corrersts for their respective error types. log pexdevsts for io12 and other i/o errors based on uncersev log header of packets with errors check corresponding bit in uncerrsev register for severity level (fatal or non fatal) io7 pci express - completer abort received return ca status for horrible error on the component. this is equivalent to a target abort on pci. default= uncorr (check uncerr sev) log header of packets with errors check corresponding bit in uncerrsev register for severity level (fatal or non fatal) io8 pci express - unexpected completion error received a completion requestorid that matches the requestor but the tag does not match any pending entries. default= uncorr (check uncerr sev) log header of packets with errors check corresponding bit in uncerrsev register for severity level (fatal or non fatal) io9 pci express - malformed tlp received a transaction layer packet that does not follow the tlp formation rules. default= uncorr (check uncerr sev) log header of packets with errors check corresponding bit in uncerrsev register for severity level (fatal or non fatal) io10 pci express - receive buffer overflow error receiver gets more data or transactions than credits allow. default= fatal (check uncerr sev) log header of packets with errors check corresponding bit in uncerrsev register for severity level (fatal or non fatal) io11 pci express - received nonfatal error message mch received a nonfatal error message from the south bridge. uncorr log header of packets with errors io12 pci express - receiver error log header of packets with errors corr log header of packets with errors io13 pci express - bad tlp error received bad crc or a bad sequence number in a transport layer packet. corr log header of packets with errors io14 pci express - bad dllp received bad crc in a data link layer packet. corr log header of packets with errors io15 pci express - replay_num rollover replay maximum count for the retry buffer has been exceeded. corr log header of packets with errors io16 pci express - replay timer time-out replay timer timed out waiting for an ack or nak dllp. corr log header of packets with errors io17 pci express - received correctable error message mch received a correctable error message from the south bridge. corr log header of packets with errors io18 esi reset time- out did not receive esi cpu_reset_done_ack or cpu_reset_done_ack_secr ets messages within t 10max after assertion of processor reset# while pwrgood was asserted fatal log pex_fat_ferr/nerr deassert processor reset#. necessary to prevent processor thermal runaway. table 5-31. intel 5000x chipset error list (sheet 3 of 7) err # in mch error name definition error type log register cause / actions
intel ? 5000x chipset memory controller hub (mch) datasheet 391 functional description b1 mch -parity error from dm (do not include poisoned data) mch detected internal dm parity error. (this error was not generated by receiving bad data from an external interface) fatal ferr_fat_int/ nerr_fat_int and nrecint log dm entry on ferr. b2 mch -multi-tag hit from snoop filter on any sf lookup port mch detected multiple hits in the sf lookup on any sf lookup port fatal ferr_fat_int/ nerr_fat_int and nrecsf log, hit/miss, set, tag, state and presence vector on ferr. b3 mch- coherency violation error mch detected a cache coherency protocol error for ewb. any requestor not in ?e/m? state in the sf fatal ferr_fat_int/ nerr_fat_int nrecint and nrecsf log ce entry on ferr b4 virtual pin interface error mch detected an error on the virtual pin interface fatal ferr_fat_int/ nerr_fat_int and nrecint b5 mch-address map error mch detected address mapping error due to software programming error. the errors are described in system address map chapter. uncorr ferr_nf_int/ nerr_nf_int and nrecint mch might malfunction. b6 single bit ecc error on snoop filter lookup mch detected a hit in sf lookup and the entry has a single bit ecc error, or mch detected a miss in sf lookup and the victim entry has a single bit error. corr ferr_nf_int/ nerr_nf_int and recsf log, hit/miss, set, tag, state and presence vector on ferr. b7 multiple bit ecc error on snoop filter lookup mch detected a multiple ecc error in any of the ways during snoop filter lookup fatal ferr_fat_int/ nerr_fat_int and nrecsf log, hit/miss, set, tag, state and presence vector on ferr. b8 write post queue parity error intel 5000x chipset mch detected a cache coherency protocol error for a bil. any requestor from the bus that issued bil not present in the sf. non fatal ferr_fat_int/ nerr_fat_int nrecint and nrecsf log ce entry on ferr this applies to sf enable mode only m1 alert on fb- dimm replay or fast reset time-out the mch detected an ?alert? on a non-redundant replay or hit a time-out on non-redundant fast reset before normal completion fatal ferr_fat_fbd nerr_fat_fbd nrecmem nrecfglog memory read: poison to requestor, update nrecmem configuration read: master- abort to requestor, update cfglog all others: drop. m2 northbound crc error on fb-dimm replay the mch detected a northbound crc error on a replay fatal ferr_fat_fbd nerr_fat_fbd nrecmem nrecfglog nrecfbd memory read: poison to requestor, update nrecmem configuration read: master- abort to requestor, update cfglog all others: drop. m3 tmid thermal event with intelligent throttling disabled intelligent throttling is disabled and the thermal sensor transitions from ?below tmid? to ?above tmid?. fatal ferr_fat_fbd nerr_fat_fbd m4 uncorrectable data ecc error on fb-dimm replay the mch detected an uncorrectable data ecc error during replay of the head of the fb-dimm replay queue uncorr ferr_nf_fbd nerr_nf_fbd poison to requestor. don?t log error again... it was logged when the replay was launched. table 5-31. intel 5000x chipset error list (sheet 4 of 7) err # in mch error name definition error type log register cause / actions
functional description 392 intel ? 5000x chipset memory controller hub (mch) datasheet m5 aliased uncorrectable non-mirrored demand data ecc error the mch determined that a normally ?correctable? error could be an aliased (x8 only) full device failure plus an additional single bit error. rec ferr_nf_fbd nerr_nf_fbd recmem redmem uerrcnt re-read once. if ecc is uncorrectable with good crc after re-read, then poison the data in memory and to the requestor. if correctable after re-read, then correct the data in memory and to the requestor. m6 aliased uncorrectable mirrored demand data ecc error in mirrored mode, the mch determined that a normally ?correctable? error could be an aliased (x8 only) full device failure plus an additional single bit error. rec ferr_nf_fbd nerr_nf_fbd recmem redmem uerrcnt first redundant read to branch x fails. mch performs a fast reset on both branches x and y. if both branches pass, then replay on branch y. if branch x fails the disable branch x and replay on branch y. if both branches fail or branch y fails disable branch x and poison data. under these conditions we get an m1 error. second redundant read to branch x fails with an uncorrectable error. perform fast reset and disable branch x and replay on branch y. m7 aliased uncorrectable spare-copy data ecc error during a sparing copy read from the failing dimm the mch determined that a normally ?correctable? error could be an aliased (x8 only) full device failure plus an additional single bit error. rec ferr_nf_fbd nerr_nf_fbd recmem redmem uerrcnt re-read once. if ecc is uncorrectable with good crc after re-read, then poison the data in the spare dimm or the off-line branch. if correctable after re-read, then correct the data in the spare dimm or the off-line branch. m8 aliased uncorrectable patrol data ecc error during a patrol scrub, the mch determined that a normally ?correctable? error could be an aliased (x8 only) full device failure plus an additional single bit error. rec ferr_nf_fbd nerr_nf_fbd recmem redmem uerrcnt the patrol read is dropped. m9 non-aliased uncorrectable non-mirrored demand data ecc error the mch detected uncorrectable data with good crc. rec ferr_nf_fbd nerr_nf_fbd recmem uerrcnt re-read once. if ecc is uncorrectable with good crc after re-read, then poison the data in memory and to the requestor. if correctable after re-read, then correct the data in memory and to the requestor. does not include poisoned northbound data. table 5-31. intel 5000x chipset error list (sheet 5 of 7) err # in mch error name definition error type log register cause / actions
intel ? 5000x chipset memory controller hub (mch) datasheet 393 functional description m10 non-aliased uncorrectable mirrored demand data ecc error in mirrored mode, the mch detected uncorrectable or poisoned data with good crc. rec ferr_nf_fbd nerr_nf_fbd recmem uerrcnt first redundant read to branch x fails. mch performs a fast reset on both branches x and y. if both branches pass, then replay on branch y. if branch x fails the disable branch x and replay on branch y. if both branches fail or branch y fails disable branch x and poison data. under these conditions we get an m1 error. second redundant read to branch x fails with an uncorrectable error. perform fast reset and disable branch x and replay on branch y m11 non-aliased uncorrectable spare-copy data ecc error the mch detected uncorrectable data with good crc from the failing dimm rank during a sparing copy. rec ferr_nf_fbd nerr_nf_fbd recmem uerrcnt re-read once. if ecc is uncorrectable with good crc after re-read, then poison the data in the spare dimm or the off-line branch. if correctable after re-read, then correct the data in the spare dimm or the off-line branch. does not include poisoned northbound data. m12 non-aliased uncorrectable patrol data ecc error during a patrol scrub, the mch detected uncorrectable data with good crc. rec ferr_nf_fbd nerr_nf_fbd recmem uerrcnt the patrol read is dropped. m13 non-retry or redundant fb- dimm memory alert, or redundant fast reset time-out the mch detected an ?alert? or corrupted write acknowledgement on the first attempt at an fb-dimm memory access packet or on the replay of a redundant fb-dimm memory access packet. rec ferr_nf_fbd nerr_nf_fbd recmem non-redundant or 1st attempt: fast reset and initiate replay. redundant replay or fast reset time-out: auto- degrade. m14 non-retry fb- dimm configuration alert the mch detected an ?alert? or corrupted write acknowledgement on the first attempt at an fb-dimm configuration write command or on the replay of a redundant fb-dimm configuration write command rec ferr_nf_fbd nerr_nf_fbd cfglog 1st attempt: fast reset and initiate replay. redundant replay: auto- degrade. m15 non-retry fb- dimm northbound crc error on read data the mch detected a northbound crc error on the first attempt at a configuration or memory read or on the replay of a redundant configuration or memory read. rec ferr_nf_fbd nerr_nf_fbd recfbd 1st redundant memory read: re-read once from other image. replay redundant memory read: auto-degrade all others: fast reset and initiate replay from the same image, branch, or channel. table 5-31. intel 5000x chipset error list (sheet 6 of 7) err # in mch error name definition error type log register cause / actions
functional description 394 intel ? 5000x chipset memory controller hub (mch) datasheet m17 correctable non-mirrored demand data ecc error. the mch detected correctable data. corr ferr_nf_fbd nerr_nf_fbd recmem redmem cerrcnt badcnt badrank correct the data in memory and to the requestor. m18 correctable mirrored demand data ecc error the mch detected correctable data. corr ferr_nf_fbd nerr_nf_fbd recmem redmem cerrcnt badcnt badrank correct the data in memory and to the requestor. m19 correctable spare-copy data ecc error the mch detected correctable data from the failing dimm rank during a sparing copy. corr ferr_nf_fbd nerr_nf_fbd recmem redmem cerrcnt badcnt badrank correct the data in the spare dimm or the off-line branch. m20 correctable patrol data ecc error during a patrol scrub, the mch detected correctable data. corr ferr_nf_fbd nerr_nf_fbd recmem redmem cerrcnt badcnt badrank correct the data in memory. m21 fb-dimm northbound crc error on fb-dimm sync status the mch detected a northbound crc error on a sync status corr ferr_nf_fbd nerr_nf_fbd recfbd drop. if sync was issued to prepare a fast reset for alert recovery then replay any queued configuration command destined for an alerting dimm or a dimm with a corrupted status crc. warning: possible double dimm configuration command execution may incur undesirable side- effects. m22 spd protocol error the mch detected an spd interface error. corr ferr_nf_fbd nerr_nf_fbd successive correction attempts performed by software. m27 dimm-spare copy start triggered dimm-spare copy corr ferr_nf_fbd nerr_nf_fbd start dimm-spare copy m28 dimm-spare copy complete dimm-spare copy completed normally corr ferr_nf_fbd nerr_nf_fbd no action table 5-31. intel 5000x chipset error list (sheet 7 of 7) err # in mch error name definition error type log register cause / actions
intel ? 5000x chipset memory controller hub (mch) datasheet 395 testability 6 testability 6.1 jtag port each component in the intel 5000p chipset includes a test access port (tap) slave which complies with the ieee 1149.1 (jtag) test architecture standard. basic functionality of the 1149.1- compatible test logic is described here, but this document does not describe the ieee 1149.1 standard in detail. for this, the reader is referred to the published standard 1 , and to the many books currently available on the subject. 6.1.1 jtag access to configuration space jtag has become a name that is synonymous with the ieee 1149.1 test access port (tap). besides the boundary scan capabilities for low speed buses and pins, it provides an inexpensive serial interface port to up/download data to and from the chip. throughout this document any reference to jtag will imply the test access port (tap) and the private chains that it is connected too, unless specifically mentioning the boundary scan attributes. the feature described here is a jtag privat e data chain that initiate a configuration request to the components configuration arbitration logic. during platform debug it is helpful to have a back door access to register space to determine correct configuration states. the in-target probe (itp) provides an effective observation capability that links the hardware and the user together to examine and control a number of dft and debug features. access to a component?s configuration space must be non-blocking to a jtag initiated configuration request to the intel 5000p chip set mch?s register space. since the intel 5000p chipset mch can source configuration transactions to other components and an errant configuration transaction that could potentially hang the system and prevent a jtag access to the intel 5000p chipset mch?s configuration space. an additional chain is provided to ensure the itp tool has uncon ditional access privilege to the intel 5000p chipset mch in case there are configuration transaction hangs from another source. 6.1.2 tap signals the tap logic is accessed serially through five dedicated pins on each component as shown in ta b l e 6 - 1 . tms, tdi and tdo operate synchronously with tck (which is independent of all other clocks). trst# is an asynchronous reset inpu t signal. this 5-pin interface operates as defined in the 1149.1 specification. a simplified block diagram of the tap used in the intel 5000p chipset components is shown in figure 6-1 . table 6-1. tap signal definitions tck tap clock input tms test mode select. controls the tap finite state machine. tdi test data input. the serial inpu t for test instructions and data. tdo test data output. the serial output for the test data. trst# test reset input.
testability 396 intel ? 5000x chipset memory controller hub (mch) datasheet the tap logic consists of a finite state machine controller, a serially-accessible instruction register, instruction decode logic and data registers. the set of data registers includes those described in the 1149 .1 standard (the bypass register, device id register, and so forth.), plus in tel 5000x chipset-sp ecific additions. 6.1.3 accessing the tap logic the tap is accessed through an 1149.1-compliant tap controller finite state machine, which is illustrated in figure 6-1 . the two major branches represent access to either the tap instruction register or to one of the component-specific data registers. the tms pin controls the progress through the st ate machine. tap instructions and test data are loaded serially (in the shift-ir an d shift-dr states, respectively) using the tdi pin. a brief description of the controller?s states follows; refer to the ieee 1149.1 standard for more detailed descriptions. figure 6-1. simplified tap controller block diagram
intel ? 5000x chipset memory controller hub (mch) datasheet 397 testability the following list describes the behavior of each state in the tap. test-logic-reset: in this state, the test logic is disabled so that normal operation of the device can continue unhind ered. the instruction in the instruction register is forced to idcode. the controller is guaranteed to enter test- logic-reset when the tms input is held active for at least five clocks. the controller also enters this state immediately when trst# is pulled active. the tap controller cannot leave this state as long as trst# is held active. run-test/idle: the tap idle state. all test registers retain their previous values. capture-ir: in this state, the shift register contained in the instruction register loads a fixed value (of which the two least signific ant bits are ?01?) on the rising edge of tck . the parallel, latched output of the instruction register (?current instruction?) does not change. shift-ir: the shift register contained in the inst ruction register is connected between tdi and tdo and is shifted one stage toward its serial output on each rising edge of tck . the output arrives at tdo on the falling edge of tck . the current instruction does not change. pause-ir: allows shifting of the instruction register to be temporarily halted. the current instruction does not change. update-ir: the instruction which has been shifte d into the instruction register is latched onto the parallel output of the in struction register on the falling edge of tck . once the new instruction has been latched, it remains the current instruction until the next update-ir (or until the tap controller state machine is reset). capture-dr: in this state, the data register selected by the current instruction may capture data at its parallel inputs. figure 6-2. tap controller state machine
testability 398 intel ? 5000x chipset memory controller hub (mch) datasheet shift-dr: the data register connected between tdi and tdo as a result of selection by the current instruction is shifted one stage towa rd its serial output on each rising edge of tck . the output arrives at tdo on the falling edge of tck . the parallel, latched output of the selected data register does no t change while new data is being shifted in. pause-dr: allows shifting of the selected data register to be temporarily halted without stopping tck . all registers retain their previous values. update-dr: data from the shift register path is loaded into the latched parallel outputs of the selected data register (if applicable) on the falling edge of tck . this and test-logic-reset are the only controller states in which the latched paralleled outputs of a data register can change. all other states are temporary controller states, used to advance the controller between active states. during such temporary states, all test registers retain their prior values. 6.1.4 reset behavior of the tap the tap and its related hardware are reset by transitioning the tap controller finite state machine into the test-logic-reset state. once in this state, all of the reset actions listed in figure 6-2 are performed. the tap is completely disabled upon reset (i.e. by resetting the tap, the device will function as though the tap did not exist). the tap can be transitioned to the test-logic-reset state in one of two ways: ? assert the trst# pin at any time. this asynchronously resets the tap controller. cycling power on a device does not ensure that the tap is reset. system designers must utilize one of the two methods stated above to reset the tap. the method used depends on the manufacturing and debug requirements of the system. 6.1.5 clocking the tap there is no minimum frequency at which the intel 5000p chipset tap will operate. because the private chains are synchronized to the local core clock of that chain there is a maximum rate relative to the core that the interface can operate. the ratio is 12:1 providing a maximum rate of 27 mh z for a core frequency of 333 mhz. 6.1.6 accessing the instruction register figure 6-3 shows the (simplified) physical im plementation of the tap instruction register. this register consists of a 7-bit shift register (connected between tdi and tdo), and the actual instruction register (w hich is loaded in parallel from the shift register). the parallel output of the tap inst ruction register goes to the tap instruction decoder. table 6-2. tap reset actions tap logic affected tap reset state action related tap instructions (instr equivalent to reset is highlighted) tap instruction register idcode ? boundary scan logic disabled extest tdo pin tri-stated ?
intel ? 5000x chipset memory controller hub (mch) datasheet 399 testability figure 6-4 shows the operation of the instruction register during the capture-ir, shift- ir and update-ir states. shaded areas in dicate the bits that are updated. in capture-ir, the shift register portion of the inst ruction register is loaded in parallel with the fixed value ?0000001?. in shift-ir, the shift register portion of the instruction register forms a serial data path between td i and tdo. in update-ir, the shift register contents are latched in parallel into the actual instruction register. note that the only time the outputs of the actual instruction register change is during update-ir. therefore, a new instruction shifted into th e tap does not take effect until the update- ir state is visited. figure 6-5 illustrates the timing when loadin g the bypass instruction (opcode 1111111b) into the tap instruction register. ve rtical arrows on the figure show the specific clock edges on which the capture-ir, shift-ir and update-ir actions actually take place. capture-ir (which preloads the instruction register with 0000001b) and shift-ir operate on rising edges of tck, and update- ir (which updates the actual instruction register) takes place on the falling edge of tck. figure 6-3. tap instruction register figure 6-4. tap instruct ion register operation
testability 400 intel ? 5000x chipset memory controller hub (mch) datasheet 6.1.7 accessing the data registers the test data registers in the intel 5000p chipset components are architected in the same way as the instruction register, with components (that is, either the ?capture? or ?update? functionality) removed from the basic structure as needed. data registers are accessed just as the instruction register is, only using the ?select-dr-scan? branch of the tap finite state machine in ta b l e 6 - 2 . a specific data register is selected for access by each tap instruction. note that the only controller states in which data register contents actually change are capture-dr, shift-dr, update-dr and run-test/ idle. for each of the tap instructions described below, therefore, it is noted what operation (if any) occurs in the selected data register in each of these four states. 6.1.8 public tap instructions ta b l e 6 - 3 contains descriptions of the encoding and operation of the public tap instructions. there are four 1149.1-defined instructions implemented in the intel 5000p chipset devices. these instructions se lect from among three different tap data registers ? the boundary scan, device id, and bypass registers. the public instructions can be executed with only the standard connection of the jtag port pins. this means the only clock required will be tck. full deta ils of the operation of these instructions can be found in the 1149.1 standard. the opcodes are 1149.1-compliant, and are consistent with the intel-standard encoding s. a brief description of each instruction follows. for more thorough descriptions refer to the ieee 1149.1 specification. figure 6-5. tap instruction register access
intel ? 5000x chipset memory controller hub (mch) datasheet 401 testability 6.1.9 public data instructions this section describes the data registers that are accessed by the public and private instructions. data shifts into all chains thro ugh the msb of the data register as shown in figure 6-6 which is the same as the instruction register. table 6-3. public tap instructions instructio n encoding data register selected description bypass 11111111 boundary scan the bypass command selects the bypass register, a single bit register connected between the tdi and tdo pins. this allows more rapid movement of test data to and from other components in the system. extest 00000000 boundary scan the extest instruction allows circuitry or wiring external to the devices to be tested. boundary scan register cells at outputs are used to apply stimulus, while boundary scan register cells at inputs are used to capture data. sample/ preload 00000001 boundary scan the sample/preload instru ction is used to allow scanning of the boundary scan register without causing interference to the normal operation of the device. two functions can be performed by use of the sample/preload instruction: 1. sample allows a snapshot of the data flowing into and out of the device to be taken without affecting the normal operation of the device. 2. preload allows an initial pa ttern to be placed into the boundary scan register cells . this allows initial known data to be present prior to the selection of another boundary scan test operation. idcode 0000010 idcode the idcode instruction is forced into the parallel output latches of the instruction register during the test-logic-tap state. this allows the device identification register to be selected by manipulation of the broadcast tms and tck signals for testing purposes, as well as by a conventional instruction register scan operation. clamp 0000100 bypass this allows static ?guard ing? values to be set into components that are not specifically bein g tested while maintaining the bypass register as the serial path through the device. highz 0001000 bypass the highz instruction is us ed to force all outputs of the device (except tdo) into a high impedance state. this instruction shall select the bypass register to be connected between tdi and tdo in the shift-dr controller state. figure 6-6. tap data register
testability 402 intel ? 5000x chipset memory controller hub (mch) datasheet 6.1.10 public data register control ta b l e 6 - 4 define the actions that o ccur in the selected data register in controller states that can alter data register contents. if a tap state does not affect the selected data register, then the corresponding table entry will be blank. not all data registers have a parallel output latch. all data registers have a parallel input latch. several table entries are still under investigation. 6.1.11 bypass register this register provides the minimal length path between tdi and tdo . it is loaded with a logical 0 during the capture-dr state. the bypass register is a single bit register and is used to provide a minimum-length serial pa th through the device. this allows more rapid movement of test data to and from other components in the system. when in bypass mode, the operation of the test logic sh all have no effect on the operation of the devices normal logic. refer to figure 6-7 for an implementation example. 6.1.11.1 bypass register definition 6.1.12 device id register this register contains the device identification code in the format shown in ta b l e 6 - 5 three fields are predefined as the version number (stepping number), the manufacturer?s identification code, and a logi cal 1 field. the component identification field is sub-divided into 3 fields. the product segment field identifies if the component is intended for cpu, laptop, desktop, serv er, etc. product type further defines the table 6-4. actions of public tap in structions during various tap states instruction capture-dr shift-dr update-dr bypass reset bypass register shift bypass register highz reset bypass register shift bypass register idcode load device id into register shift id register extest load input pin values into boundary scan shift register shift boundary scan shift register load boundary scan shift register into boundary scan register; drive pins accordingly sample/preload load pin values into boundary scan shift register shift boundary scan shift register load boundary scan shift register into boundary scan register figure 6-7. bypass register implementation
intel ? 5000x chipset memory controller hub (mch) datasheet 403 testability component within a segment by stating it to be a cpu, memory, chipset, etc. the last field is a sequential component number assi gnment. this value will be maintained as sequential as possible depending on when each component?s request was satisfied in the corporate database. 6.1.12.1 device id register 6.1.13 boundary scan register the following requirements apply to those interfaces that continue to support boundary scan (bscan) or the miscellaneous i/o signals. ? each signal or clock pin (with the exception of the tap specific pins tck, tdi, tdo, tms, & trst#) will have an associated boundary-scan register cell. differential driver or receiver pin pairs that cannot be used independently shall be considered table 6-5. intel? 5000p chipset device id codes device versio n component identification fields manufacturing id ?1? entire code (hex) product segment product type component number 4655 11132 intel 5000p chipset mch ? a0 0000 000100 01000 01000 00000001001 1 0x0118013 jtag encode: 0000010 bit attr default description 31:28 r 0000 version: this number changes for each stepping including metal ?dash? steppings. the most significant 2 bits are the stepping number: 00 a-step; 01 b-step, 10 c-step, and 11 d-step. the least significant 2 bits is the revision within a stepping. 27:22 r 000100 product segment: number assigned that determines the market segment into which this component belongs. since this format is new, the value for chipset is shown with others as an example. r&d:000 000 cpu:100 000 desktop:010 000 laptop:001 000 server:000 100 etc. 21:17 r 01000 product type: number assigned to further define the component within the market segment. since this format is new, the value for chipset is shown with others as an example. test:00 000 cpu:10 010 memory:00 100 modem:00 101 chipset:01 000 etc. 16:12 r listed in next column component number: sequential listing based on request to database. intel? 5000p chipset mch:01000b 11:1 r 00000001001 manufacturing id: this number is assigned to intel. 0r1 ?1?
testability 404 intel ? 5000x chipset memory controller hub (mch) datasheet a single pin (that is, one boundary-scan register cell after the differential receiver). ? internal signals which control the direction of i/o pins shall also have associated boundary- scan register cells. ? each output pin (with the exception of tdo) shall be able to be driven to a tristate condition for highz test. 6.2 extended debug port (xdp) the extended debug port is covered in the xdp design guide.
intel ? 5000x chipset memory controller hub (mch) datasheet 405 electrical characteristics 7 electrical characteristics this chapter provides the absolute maximu m ratings and dc characteristics for the intel 5000p chipset mch. 7.1 absolute maximum ratings ta b l e 7 - 1 lists the maximum environmental stress ratings for the intel 5000p chipset mch. functional operation at or exceeding the absolute maximum and minimum ratings is neither implied nor guaranteed. functional operating parameters are listed in the ac tables. warning: stressing the device beyond the ?absolut e maximum ratings? may cause permanent damage. these are stress ratings only. operating beyond the ?operating conditions? is not recommended and extended exposure beyond ?operating conditions? may affect reliability. 7.1.1 thermal characteristics for information on thermal characteristics, consult the intel ? 5000p/5000v chipset memory controller hub (mch) thermal/mechanical design guidelines. 7.1.2 power characteristics notes: 1. under no circumstances may the supply voltage go past the ac min/max window. the supply voltage may go outside the dc min/max window for transient events, table 7-1. absolute maximum ratings symbol parameter min max unit t storage storage temperature -40.0 85.0 c vcc mch supply voltage with respect to vss -0.50 1.85 v v tt fsb termination supply voltage input with respect to vss -0.30 1.85 v table 7-2. operating condition power supply rails symbol parameter ac min dc min nom dc max ac max unit notes v tt host agtl+ termination voltage 1.140 1.164 1.20 1.236 1.260 v 1,2 i tt host agtl+ termination current 2.6 4.8 a vcc 1.5v mch supply voltage 1 .425 1.455 1.53 1.575 1.605 v 1, 2 icc 1.5v mch supply current 17.6 22.0 a 3 icc 1.5v mch supply current 19.3 24.1 a 4 icc 1.5v mch supply current 15.3 19.1 a 5 amb vcc 1.5v fbd supply voltage 1.425 1.455 1.5 1.575 1.605 v6 other 3.3v supply voltage 3.1185 3.2175 3.3 3,3825 3,481 5 v
electrical characteristics 406 intel ? 5000x chipset memory controller hub (mch) datasheet 2. the supply voltage must stay within the dc min/max wi ndow in a static system (no active switching). the dc window only assumes voltage regulator ripple and motherboard induced noise 3. intel 5000p chipset mch with 4 acti ve fb-dimm channels. total core + i/o current drawn off the 1.5 vrail 4. intel 5000x chipset mch with 4 active fb-dimm channe ls. total core + i/o current drawn off the 1.5 v rail 5. intel 5000v chipset mch with 2 active fb-dimm channe ls. total core + i/o current drawn off the 1.5 v rail 6. tolerances are specified at the amb dram package( s) and fb-dimm voltage regulator designs should be scaled accordingly to support these tolerances for the 1.5. dc min/max per the jedec specification. ac tolerances from vr loop bw ~30 khz to 1 mhz. 1. the analog voltage is intended to be a filtered copy of its associated supply voltage. refer to the new dual- core intel? xeon? processor-based servers platform design guide (pdg) for the recommended implementation and frequency response requirements of each filter. 7.2 dc characteristics this section documents the dc characteristi cs of the mch. the specifications are split into five sections: ?clocks ?fsb interface ? fb-dimm (fully buffered dimm) memory interface 1 ? pci express/ esi interface ? miscellaneous interface ?smbus interface ?jtag interface table 7-3. analog and bandgap voltage and current specifications symbol parameter min nom max uni t notes vcca analog mch supply voltage 1.4055 1.5 1.545 v 1 icca analog mch supply current 28.9 ma fsbvcca analog pll voltage 1.4055 1.5 1.545 v 1 fsbicca analog pll current 28.9 ma fbdvcca analog fbd voltage 1.4055 1.5 1.545 fbdicca analog fbd current 52 ma pevcca analog pci express voltage 1.4055 1.5 1.545 v 1 peicca analog pci express current 48 ma 1 pevccbg analog pci express bandgap voltage 2.425 2.5 2.575 v 1 peiccbg analog pci express bandgap current 600 a1 1. refer to the intel ? 6400/6402 advanced memory buffered external design specification (eds) addendum for additional details on the fb-dimm interface.
intel ? 5000x chipset memory controller hub (mch) datasheet 407 electrical characteristics 7.2.1 clock dc characteristics table 7-4. clock dc characteristics symbol signal group parameter min nom max unit note s 333 mhz fsb clock (coreclkn / coreclkp) v il (h) input low voltage -0.150 0 0.150 v 1 v ih (h) input high voltage 0.660 0.700 0.850 v v cross(abs) (h) absolute crossing point 0.250 0.550 v 2, 7 v cross(rel) (h) relative crossing point 0.250 + 0.5 x (v havg ? 0.700) 0.550 - 0.5 x (0.700 - v havg ) v7, 8 v cross (h) range of crossing points 0.140 v v os (h) overshoot v ih + 0.300 v 3 v us (h) undershoot -0.300 v 4 v rbm (h) ringback margin 0.200 v 5 v tr (h) threshold region v cross ? 0.100 v cross + 0.100 v 6 266 mhz fsb clock (coreclkn / coreclkp) v il (h) input low voltage -0.150 0 0.150 v 1 v ih (h) input high voltage 0.660 0.700 0.850 v v cross(abs) (h) absolute crossing point 0.250 0.550 v 2, 7 v cross(rel) (h) relative crossing point 0.250 + 0.5 x (v havg ? 0.700) 0.550 - 0.5 x (0.700 - v havg ) v7, 8 v cross (h) range of crossing points 0.140 v v os (h) overshoot v ih + 0.300 v 3 v us (h) undershoot -0.300 v 4 v rbm (h) ringback margin 0.200 v 5 v tr (h) threshold region v cross ? 0.100 v cross + 0.100 v 6 100 mhz pci express cl ock (peclkn / peclkp) v il (q) input low voltage -0.150 0 v v ih (q) input high voltage 0.660 0.700 0.850 v v cross(abs) (q) absolute crossing point 0.250 0.550 v 2, 7 v cross(rel) (q) relative crossing point 0.250 + 0.5 x (v havg ? 0.700) 0.550 + 0.5 x (v havg ? 0.700) v7, 8 v cross (q) range of crossing points 0.140 v 1, 2 v os (q) overshoot v ih + 0.300 v 3 v us (q) undershoot -0.300 v 4 v rbm (q) ringback margin 0.200 v 5 v tr (q) threshold region v cross ? 0.100 v cross + 0.100 v 6 133/167 mhz fb-dimm clock (fbdxxclkn/ fbdxxclkp) v il (k) input low voltage -0.150 0 v v ih (k) input high voltage 0.660 0.700 0.850 v v cross(abs) (k) absolute crossing point 0.250 0.550 v 2, 7 v cross(rel) (k) relative crossing point 0.250 + 0.5 x (v havg ? 0.700) 0.550 + 0.5 x (v havg ? 0.700) v7, 8
electrical characteristics 408 intel ? 5000x chipset memory controller hub (mch) datasheet notes: 1. refer to chapter 5 of intel ? 5000p chipset/intel ? 5000v chipset and intel ? 5000x chipset external design specification (eds) addendum . 2. crossing voltage is defined as the instantaneous voltage when the rising edge of coreclkp is equal to the falling edge of coreclkn. 3. overshoot is defined as the abso lute value of the maximum voltage. 4. undershoot is defined as the absolute value of the minimum voltage. 5. ringback margin is defined as the abso lute voltage difference between the maximu m rising edge ringback and the maximum falling edge ringback. both maximum rising and falling ringbacks should not cross the threshold region. 6. threshold region is defined as a region centered around the crossing point voltage in which the differential receiver switche s. it includes input threshold hysteresis. 7. the crossing point must meet the absolute and rela tive crossing point specif ications simultaneously. 8. vhavg (the average of v ih ) can be measured directly using ?vtop? on agilent scopes and ?high? on tektronix scopes. 7.2.2 fsb interface dc characteristics notes: 1. gtlref is equivalent to fsbxfsbvref . gtlref is generated from v tt on the baseboard by a voltage divider or 1% resistors. 2. v il is defined as the voltage range at a receiving agent that will be inte rpreted as an electrical low value. 3. v ih is defined as the voltage range at a receiving agent that will be interpreted as an electrical high value. 4. v ih and v oh may experience excursions above v cc. however, input signal drivers must comply with the signal quality specifications chapter in the document. 5. leakage to vss with land held at v tt. 6. leakage to v tt with land held at 300 mv. 7. use 50 ohm 15% for all microstrip. 8. i ol is defined as current when output low. the formula computes the total current drawn by the driver from vr (voltage regulator). half of the total current goes through rtt on the chipset, and another half goes through the rtt on the cpu (the end-bus-agency). table 7-5. fsb interface dc characteristics symbol signal group parameter min nom max unit note s v il ?(a) (b) host agtl+ input low voltage 0 gtlref ? (0.1 v tt ) v1, 2 v ih ?(a) (b) host agtl+ input high voltage gtlref + (0.1 v tt ) v tt v1, 3 v ol ?(a) (c) host agtl+ output low voltage 0.4 v v oh ?(a) (c) host agtl+ output high voltage 0.90 x v tt v tt v4 i ol ?(a) (c) host agtl+ output low current v tt / (0.50 x r tt_min + r on_min ) ma 8 i li ?(a) (b) host agtl+ input leakage current n/a +/- 200 ua 5, 6 i lo ?(a) (b) host agtl+ output leakage current n/a +/- 200 ua 5, 6 r on ? buffer on resistance 7 11 gtlref ?(e) host bus reference voltage (0.98 x 0.67) x v tt 0.67 x v tt (1.02 x 0.67) x v tt v1 r tt ? host termination resistance common clock, async on stripline 45 50 55 7
intel ? 5000x chipset memory controller hub (mch) datasheet 409 electrical characteristics 7.2.3 fb-dimm dc characteristics notes: 1. defined as: v tx-cm = dc (avg) of | v tx-d+ + v tx-d- | / 2. 2. tx dc impedance matching between d+ and d- on a given lane. notes: 1. dc (avg) of | v rx-d+ + v rx-d- | / 2. 2. rx dc impedance matching between d+ and d- on a given lane. table 7-6. fb-dimm transmitter (t x) output dc characteristics symbol signal group parameter min nom max unit note s v tx-cm_s (i) (j) dc common mode output voltage for small voltage swing 135 280 mv 1 v tx-cm_l (i) (j) dc common mode output voltage for large voltage swing 375 mv 1 v tx-se (i) (j) single-ended voltage 0 700 mv rltx-diff (i) (j) differential return loss -10 db rltx-cm (i) (j) common mode return loss -6 db z tx-match-dc (i) (j) d+/d- tx impedance difference 4% 2 z tx-com-esi- imp-dc (i) (j) d+/d- tx common mode high impedance state 520k table 7-7. fb-dimm receiver (r x) output dc characteristics symbol signal group parameter min nom max unit note s v rx-cm (i) (j) dc common mode input voltage 190 400 mv 1 z rx-match-dc (i) (j) d+/d- rx impedance difference 4% 2 rlrx-diff (i) (j) differential return loss -10 db rlrx-cm (i) (j) common mode return loss -6 db
electrical characteristics 410 intel ? 5000x chipset memory controller hub (mch) datasheet 7.2.4 pci express/ esi interface dc characteristics notes: 1. no test load is necessarily associated with this value. 2. specified at the measurement point into a timing and voltage compliance te st load and measured over any 250 consecutive tx uis. notes: 1. no test load is necessarily associated with this value. 2. specified at the measurement point and measured over any 250 consecutive ui s. if the clock to the rx and tx are not derived from the same reference clock, the tx ui recovered from 3500 consecutive ui must be used as a reference for the eye diagram. 3. a trx-eye=0.40ui provides for a total sum of 0.60 ui dete rministic and random jitter budget for the transmitter and interconnect collected any 250 consecutive uis. the trx-ey e-median-to-max-jitter specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total.6 ui jitter budget collected over any 250 consecutive tx uis. it should be noted th at the median is not the same as the mean. the jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. if the clocks to the rx and tx are not derived from the same reference clock, the tx ui recovered from 3500 consecutive ui must be used as the reference for the eye diagram. 4. the receiver input impedance shall result in a differential return loss greater than or equal to 15 db with the d+ line biase d to 300mv and the d- line biased to -300 mv an d a common mode return loss greater than or equal to 6 db (no bias required) over a frequency range of 50 mhz to 1.25 ghz. this input im pedance requirement applies to all valid input levels. the reference impedance for return loss measurements for is 50 ohms to ground for both the d+ and d- line (that is, as measured by a vector network analyzer with 50 ohm probes). note: that the series capacitors ctx is optional for the return loss measurement. table 7-8. pci express/ esi differential transmitter (tx) output dc characteristics symbol signal group parameter min nom max unit note s vtx-dif-dc (o) (p) differential peak to peak output voltage 0.8 1.2 v 2 vtx-cm-dc- active- idle-delta (o) (p) absolute delta of dc common mode voltage during l0 and electrical idle 0100mv2 vtx-cm-dc- line-delta (o) (p) absolute delta of dc common mode voltage between d+ and d- 025mv2 vtx-idle- diffp (o) (p) electrical idle differential peak output voltage 20 mv 2 vtx-rcv- detect (o) (p) the amount of voltage change allowed during receiver detection 600 mv vtx-dc-cm (o) (p) the tx dc common mode voltage 03.6v2 itx-short (o) (p) the short circuit current limit 90 ma ztx-diff-dc (o) (p) dc differential tx impedance 80 100 120 ztx-dc (o) (p) transmitter dc impedance 40 table 7-9. pci express/ esi differential receiver (rx) input dc characteristics symbol signal group parameter min nom max unit note s zrx-diff-dc (o) (p) dc differential input impedance 80 100 120 5 zrx-dc (o) (p) dc input impedance 40 50 60 2, 3 zrx-high- imp-dc (o) (p) power down dc input common mode impedance 200k 6 vrx-idle- det-diffp (o) (p) electrical idle detect threshold 65 175 mv
intel ? 5000x chipset memory controller hub (mch) datasheet 411 electrical characteristics 5. impedance during all ltssm states. when transitioning from a fundamental reset to detect (the initial state of the ltssm) there is a 5 ms transition time before receiver terminati on values must be met on all un-configured lanes of a port. 6. the rx dc common mode impedance that exists when no power is present or fundamenta l reset is asserted. this helps ensure that the receiver detect circuit will not falsely assume a receiver is powered on when it is not. this term must be measured at 300 mv above the rx ground. 7.2.5 miscellaneous dc characteristics notes: 1. at vol max, iol = max. table 7-10. smbus dc characteristics symbol signal group parameter min nom max unit note s v ih (w) input high voltage 2.1 v v il (w) input low voltage 0.8 v v ol (w) output low voltage 0.4 v 1 i ol (w) output low current 4 ma i leak (w) leakage current 10 a c pad (w) pad capacitance 10 pf table 7-11. jtag dc characteristics symbol signal group parameter min nom max unit note s v ih (y) input high voltage 0.9 v v il (y) input low voltage 0.5 v v ol (z) output low voltage 0.4 v i leak (y) (z) leakage current 2.9 a table 7-12. 1.5 v cmos dc characteristics symbol signal group parameter min nom max unit note s v ih (d) (cc) input high voltage 1.0 1.6 v v il (d) (cc) input low voltage -0.2 0.5 v v oh (cc) output high voltage 1.1 v v ol (cc) output low voltage 0.4 v i leak (cc) leakage current 70 a v abs (d) (cc) input damage thresholds -0.2 1.6 v table 7-13. 3.3 v cmos dc ch aracteristics (sheet 1 of 2) symbol signal group parameter min nom max unit note s v ih (dd) input high voltage 2.1 v v il (dd) input low voltage 0.8 v v oh (ee) output high voltage v
electrical characteristics 412 intel ? 5000x chipset memory controller hub (mch) datasheet v ol (ee) output low voltage 0.4 v i leak (ee) leakage current 10 a v abs (dd) input damage thresholds -0.3 3.5 v table 7-13. 3.3 v cmos dc ch aracteristics (sheet 2 of 2) symbol signal group parameter min nom max unit note s
intel ? 5000x chipset memory controller hub (mch) datasheet 413 ballout and package information 8 ballout and package information 8.1 intel 5000x chipset mch ballout the following section presents preliminary ballout information for the intel 5000x chipset mch. this ballout is subject to ch ange and is to be used for informational purposes only. figure 8-1. intel 5000x chipset quadrant map 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 21 fbd misc vcc core fsb1 fsb0 am an al ak aj ah af ag ae ad ac ab y aa w v u t p r n m l k h j g f e d c b a at ar au av ap 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 21 38 37 36 35 34 am an al ak aj ah af ag ae ad ac ab y aa w v u t p r n m l k h j g f e d c b a at ar au av ap pe0 lws pe3 pe2 rsvd pe7 pe4 pe5 pe6
ballout and package information 414 intel ? 5000x chipset memory controller hub (mch) datasheet figure 8-2. intel 5000x chipset mc h ballout left side (top view) 38 37 36 35 34 33 32 31 30 29 28 27 26 av vss vss fsb0defer# fsb0hitm# vss fsb0rs[0]# fsb0bnr# vss fsb0a[17]# rsvd vss av au vss fsb0d[21]# fsbslwcres fsb0bpri# vss fsb0hit# fsb0rs[2]# vss fsb0ads# fsb0a[21]# vss fsb0a[25]# au at vss fsb0d[22]# fsb0d[19]# fsbcres vss fsb0dp[ 1]# fsb0trdy# vss fsb0lock# fsb0drdy# vss fsb0a[23]# fsb0a[24]# at ar fsb0dstbp[1]# fsb0dstbn[1]# vss vss fsbodtcres rsvd vss fsb0dp[0]# fsb0dbsy# vss fsb0bpm[4]# fsb0a[19]# vss ar ap fsb0d[27]# fsb0dbi[1]# fsb0d[23]# fsb0d[18]# fsb0d[20]# vss rsvd fsb0dp[2]# vss fsb0bpm[5]# rsvd vss fsb0a[7]# ap an vss vss fsb0d[26]# fsb0d[24]# vss fsb0d[16]# fsb0d[5]# vss fsb0reset# fsb0dp[3]# vss fsb0rsp# fsb0a[6]# an am fsb0d[28]# fsb0d[31]# vss vss fsb0d[29]# fsb0d[12]# vss rsvd fsb0vref vss fsb0breq[0]# fsb0vref vss am al fsb0d[50]# fsb0d[52]# fsb0d[51]# fsb0d[25]# fsb0d[17]# vss fsb0dbi[0]# fsb0d[7]# vss fsb0d[1]# fsb0rs[1]# vss fsb0req[0]# al ak vss vss fsb0d[53]# fsb0d[30]# vss fsb0dstbp[0]# fsb0dstbn[0]# vss fsb0d[6]# fsb0d[3]# vss fsb0binit# fsb0ap[1]# ak aj fsb0d[56]# fsb0d[55]# vss vss fsb0d[49]# fsb0d[15]# vss fsb0d[8]# fsb0d[10]# vss fsb0d[0]# fsb0mcerr# vss aj ah fsb0d[57]# fsb0dbi[3]# fsb0d[61]# fsb0dstbp[3]# fsb0dstbn[3]# vss fsb0d[9]# fsb0d[11]# vss fsb0d[4]# fsb0d[2]# vss fsb0ap[0]# ah ag vss vss fsb0d[60]# fsb0d[54]# vss fsb0d[32]# fsb0d[36]# vss fsb0d[33]# fsb0d[13]# vss fsb0d[14]# fsb0breq[1]# ag af fsb0d[59]# fsb0d[48]# vss vss fsb0vref fsb0d[37]# vss fsb0d[35]# fsb0dbi[2]# vss fsb0d[45]# vss vss af ae fsb0d[58]# fsb0d[63]# fsb0d[62]# vccsf fsb0d[34]# vss fsb0d[39]# fsb0d[40]# vss fsb0d[43]# fsb0d[47]# vss vtt ae ad vss vss vss fsb0d[38]# vss fsb0dstbp[2]# fsb0dstbn[2]# vss fsb0d[41]# fsb0d[46]# vss vss vccsf ad ac vss fbd0sbon[6] testhi vss fbd0sbop[8] fbd0sbon[8] vss fsb0d[44]# fsb0d[42]# vss vss vss vccsf ac ab fbd0sbon[5] fbd0sbop[6] vss fbd0sbop[7] fbd0sbon[7] vss fbd0nbin[2] fbd0nbip[2] vss vss vss vss vccfbd ab aa fbd0sbop[5] vss fbd0sbop[9] fbd0sbon[9] vss fbd0sbon[2] fbd0sbop[2] vss vss vss vss vccfbd vccfbd aa y vss fbd0sbon[4] fbd0sbop[4] vss fbd0sbop[3] fbd0sbon[3] vss fbd0nbin[1] fbd0nbip[1] vss fbd0nbin[0] fbd0nbip[0] vccfbd y w fbd0sbon[1] vss vss fbd0nbin[9] fbd0nbip[9] vss fbd0sbop[0] fbd0sbon[0] vss fbd0nbin[5] fbd0nbip[5] vss vccfbd w v fbd0sbop[1] vss fbd0nbin[10] fbd0nbip[10] vss fbd0nbin[7] fbd0nbip[7] vss fbd0nbin[13] fbd0nbip[13] vss fbd0nbip[3] vccfbd v u vss fbd0nbin[11] fbd0nbip[11] vss fbd0nbin[8] fbd0nbip[8] vss fbd0nbin[12] fbd0nbip[12] vss fbd0nbip[4] fbd0nbin[3] vccfbd u t fbd01clkn rsvd vss fbd01vcca fbd01vssa vss fbd0nbin[6] fbd0nbip[6] vss vss fbd0nbin[4] vccfbd vccfbd t r fbd01clkp vss fbd1sbop[6] fbd1sbon[6] vss fbd1sbop[8] fbd1sbon[8] vss vss vss vss vss vss r p vss fbd1sbop[5] fbd1sbon[5] vss fbd1sbop[7] fbd1sbon[7] vss vss vss vss fbd1nbin[0] fbd1nbip[0] vccfbd p n fbd1sbop[9] fbd1sbon[9] vss fbd1sbon[4] fbd1sbop[4] vss fbd1nbin[12] vss vss fbd1nbin[3] fbd1nbip[3] vss vccfbd n m vss vss fbd1sbon[3] fbd1sbop[3] vss fbd1nbin[6] fbd1nbip[12] vss fbd1nbin[4] fbd1nbip[4] vss fbd1nbin[1] fbd1nbip[1] m l fbd1sbon[2] fbd1sbon[1] fbd1sbop[1] vss fbd1nbin[7] fbd1nbip[6] vss fbd1nbin[5] fbd1nbip[5] vss fbd1nbin[2] fbd1nbip[2] vss l k fbd1sbop[2] vss vss fbd1nbin[8] fbd1nbip[7] vss fbd1nbin[13] fbd1nbip[13] vss vss vss vss vss k j vss fbd1sbon[0] fbd1sbop[0] fbd1nbip[8] vss fbd2sbon[8] fbd2sbop[8] vss vss vss vss vss vss j h fbd1nbin[11] fbd1nbin[10] fbd1nbip[10] vss fbd2sbon[7] fbd2sbop[7] vss vss vss vss vss vss vss h g fbd1nbip[11] vss vss fbd2sbon[6] fbd2sbop[6] vss vss vss vss fbd2sbon[0] fbd2sbop[0] vss fbd3sbop[1] g f vss fbd1nbin[9] fbd1nbip[9] fbdicompbias vss fbd2sbon[4] fbd2sbop[4] vss fbd2sbon[1] fbd2sbop[1] vss fbd23vssa vss f e fbd2nbin[11] fbdbgbiasext fbdresin vss fbd2sbon[9] fbd2sbop[9] vss fbd2sbon[2] fbd2sbop[2] vss fbd23clkn fbd23vcca vss e d fbd2nbip[11] fbd2nbin[10] vss fbd2sbon[5] fbd2sbop[5] vss fbd2sbon[3] fbd2sbop[3] vss rsvd fbd23clkp vss fbd3nbin[11] d c vss fbd2nbip[10] fbd2nbip[9] vss fbd2nbip[7] vss vss fbd2nbip[13] vss vss fbd2nbip[3] vss vss c b vss fbd2nbin[9] fbd2nbip[8] fbd2nbin[7] fbd2nbip[6] fbd2nbip[12] fbd2nbin[13] fbd2nbip[5] fbd2nbip[4] fbd2nbin[3] fbd2nbip[2] fbd2nbip[1] b a vss fbd2nbin[8] vss fbd2nbin[6] fbd2nbin[12] vss fbd2nbin[5] fbd2nbin[4] vss fbd2nbin[2] fbd2nbin[1] a 38 37 36 35 34 33 32 31 30 29 28 27 26
intel ? 5000x chipset memory controller hub (mch) datasheet 415 ballout and package information figure 8-3. intel 5000x chipset mch ballout center (top view) 25 24 23 22 21 20 19 18 17 16 15 14 av fsb0a[28]# fsb0a[31]# vss fsb0a[35]# vtt vtt vtt vtt vss vss vss vss av au fsb0a[22]# vss fsb0a[29]# fsb0a[34]# vtt vtt vtt vtt fsbvcca corevssa vss vss au at vss fsb0a[27]# fsb0a[30]# vss vtt vtt vtt vtt corevcca vss vss fsb1vref at ar fsb0a[26]# fsb0a[20]# vss fsb0a[33]# vtt vtt vtt vtt vss rsvd rsvd vss ar ap fsb0a[18]# vss fsb0adstb[1]# fsb0a[32]# vtt vtt vtt vtt coreclkn fsb1d[55]# vss fsb1d[47]# ap an vss fsb0a[4]# rsvd vss vtt vtt vtt vtt coreclkp vss fsb1d[53]# fsb1d[50]# an am fsb0a[5]# rsvd vss fsb0a[9]# vtt vtt vtt vtt vss fsb1d[49]# fsb1d[51]# vss am al fsb0a[3]# vss fsb0adstb[0]# fsb0a[12]# vtt vtt vtt vtt vcc fsb1d[56]# vss fsb1d[52]# al ak vss fsb0req[2]# rsvd vss vtt vtt vtt vtt rsvd vss fsb1dstbp[3]# fsb1dstbn[3]# ak aj fsb0req[4]# fsb0req[3]# vss fsb0a[11]# vtt vtt vtt vtt vss fsb1d[61]# fsb1d[60]# vss aj ah fsb0req[1]# vss fsb0a[8]# fsb0a[13]# vtt vtt vtt vtt vss fsb1d[54]# vss fsb1d[48]# ah ag vss fsb0a[10]# fsb0a[15]# vss vtt vtt vtt vtt vss vss fsb1d[59]# fsb1d[62]# ag af fsb0a[14]# vss vss fsb0a[16]# vtt vtt vtt vtt vss fsb1d[63]# fsb1d[58]# vss af ae v tt v tt v tt v tt vtt v tt v tt vtt v tt v tt v tt v tt ae ad v tt v tt v tt v tt vtt v tt v tt vtt v tt v tt v tt v tt ad ac vccsf vss vcc vss vcc vss vcc vss vcc vss vcc vtt ac ab vccfbd vcc vss vcc vss vcc vss vcc vss vcc vss vccsf ab aa vccfbdvssvccvssvccvssvccvssvccvssvccvss aa y vccfbd vcc vss vcc vss vcc vss vcc vss vcc vss vccpe y w vccfbdvssvccvssvccvssvccvssvccvssvccvccpe w v vccfbd vcc vss vcc vss vcc vss vcc vss vcc vss vccpe v u vccfbdvssvccvssvccvssvccvssvccvssvccvccpe u t vccfbd vcc vss vcc vss vcc vss vcc vss vcc vss vccpe t r vccfbdvssvccvssvccvssvccvssvccvssvccvccpe r p vccfbd vcc vss vcc vss vcc vss vcc vss vcc vss vccpe p n vccfbd vccfbd vccfbd vccfbd vccfbd vccfbd vcc vss vcc vss vccpe vccpe n m vccfbd vccfbd vccfbd vccfbd vccfbd vccfbd vss vcc vcc vcc vccpe vccpe m l vsssen vccsen vccfbd vccfbd vccfbd vccfbd vcc vcc vcc vcc vccpe vccpe l k vss vss vccfbd vccfbd vccfbd vss fbd3sbop[8] fbd3sbon[8] vss vss spd1smbdata cfgsmbclk k j vss fbd3sbop[3] fbd3sbon[3] vss fbd3sbop[5] fbd3sbon[5] vss fbd3sbon[7] vss spd1smbclk xdpslwcres cfgsmbdata j h fbd3sbop[2] fbd3sbon[2] vccfbd fbd3sbop[9] fbd3sbon[9] vccfbd fbd3sbon[6] fbd3sbop[7] pwrgood spd3smbdata spd3smbclk vss h g fbd3sbon[1] vss fbd3sbop[4] fbd3sbon[4] vss fbd3nbip[0] fbd3sbop[6] vss reseti# testhi_v3ref vss xdpodtcres g f vccfbd fbd3nbin[9] fbd3nbip[9] vss vss fbd3nbin[0] vss fbd3nbip[1] testhi_v3ref vss spd2smbclk xdpcomcres f e fbd3nbin[10] fbd3nbip[10] vccfbd fbd3sbon[0] vss vccfbd fbd3nbin[5] fbd3nbin[1] vss xdpd[15]# spd2smbdata xdpd[5]# e d fbd3nbip[11] vss fbd3nbip[7] fbd3sbop[0] vss fbd3nbip[13] fbd3nbip[5] vss fbd3nbin[2] xdpd[14]# xdpd[8]# vss d c fbd2nbip[0] vss fbd3nbin[7] vss fbd3nbip[12] fbd3nbin[13] vss fbd3nbin[3] fbd3nbip[2] xdpd[12]# vss xdpdstbp# c b fbd2nbin[0] fbd3nbin[8] vss fbd3nbip[6] fbd3nbin[12] vss fbd3nbin[4] fbd3nbip[3] vss vss xdpd[9]# xdpd[7]# b a vss fbd3nbip[8] vss fbd3nbin[6] vss vccfbd fbd3nbip[4] vss xdprdy# xdpd[11]# xdpd[13]# xdpd[10]# a 25 24 23 22 21 20 19 18 17 16 15 14
ballout and package information 416 intel ? 5000x chipset memory controller hub (mch) datasheet figure 8-4. intel 5000x chipset mc h ballout right side (top view) 13121110987654321 av fsbslw ctrl fsb1d[40]# vss fsb1d[39]# fsb1d[37]# vss fsb1d[32]# fsb1d[9]# vss fsb1d[10]# vss av au vss vss fsb1dbi[2]# fsb1d[38]# vss fsb1d[33]# fsb1d[13]# vss fsb1d[15]# fsb1dstbp[0]# fsb1dstbn[0]# vss au at vss fsb1d[42]# fsb1d[41]# vss fsb1d[34]# fsb1d[36]# vss fsb1d[11]# fsb1d[8]# vss fsb1d[7]# fsb1d[6]# vss at ar fsb1d[45]# fsb1d[46]# vss fsb1dstbp[2]# fsb1d[35]# vss fsb1d[14]# fsb1d[12]# vss fsb1d[5]# fsb1d[4]# vss fsb1d[3]# ar ap fsb1d[43]# vss fsb1d[44]# fsb1dstbn[2]# vss fsb1d[22]# fsb1dbi[0]# vss fsb1d[1]# fsb1d[2]# vss fsb1ads# fsb1d[0]# ap an vss fsb1d[25]# fsb1d[27]# vss fsb1d[24]# fsb1d[23]# vss fsb1d[18]# fsb1vref vss fsb1bpm[5]# fsb1bpm[4]# vss an am fsb1d[28]# fsb1d[26]# vss fsb1dstbp[1]# fsb1d[21]# vss rsvd fsb1d[20]# vss fsb1dbsy# fsb1drdy# vss fsb1breq[1]# am al fsb1d[30]# vss fsb1d[29]# fsb1dstbn[1]# vss fsb1d[17]# fsb1d[16]# vss fsb1rs[2]# fsb1lock# vss fsb1breq[0]# fsb1rs[1]# al ak vss fsb1d[31]# fsb1dbi[1]# vss fsb1d[19]# fsb1hit# vss fsb1trdy# fsb1rs[0]# vss fsb1bnr# fsb1rsp# vss ak aj fsb1d[57]# fsb1dp[1]# vss fsb1bpri# fsb1defer# vss fsb1hitm# fsb1req[2]# vss fsb1binit# fsb1a[26]# vss rsvd aj ah fsb1dbi[3]# vss fsb1mcerr# vccsf vss fsb1a[6]# rsvd vss fsb1a[19]# fsb1vref vss fsb1a[24]# fsb1a[25]# ah ag vss fsb1ap[0]# fsb1dp[0]# fsb1ap[1]# fsb1req[0]# fsb1a[7]# vss rsvd fsb1a[18]# vss fsb1adstb[1]# rsvd vss ag af fsb1dp[3]# fsb1dp[2]# vss vss fsb1req[3]# vss fsb1a[8]# fsb1a[11]# vss fsb1a[17]# fsb1a[28]# vss fsb1a[27]# af ae vtt vss fsb1reset# fsb1req[4]# vss rsvd fsb1a[9]# vss fsb1a[21]# fsb1a[30]# vss fsb1a[31]# fsb1a[32]# ae ad vtt fsb1a[3]# fsb1req[1]# vss fsb1a[4]# fsb1a[12]# vss fsb1a[20]# fsb1a[23]# vss fsb1a[29]# fsb1a[33]# vss ad ac vtt fsb1a[5]# vss fsb1adstb[0]# fsb1a[13]# vss fsb1a[15]# fsb1a[22]# vss fsb1a[34]# fsb1a[35]# vss psel[0] ac ab vccsf vss fsb1a[10]# fsb1a[14]# vss pe0rp[2] pe0rn[2] vss pe0tn[2] pe0tp[2] vss psel[1] psel[2] ab aa vccsf fsb1a[16]# pewidth[0] vss pe0tn[3] pe0tp[3] vss pe0rn[3] pe0rp[3] vss pe0tp[1] pe0tn[1] vss aa y vccpe pewidth[1] vss pe0rp[0] pe0rn[0] vss pe0tp[0] pe0tn[0] vss pe0rp[1] pe0rn[1] vss rsvd y w vccpe vccpe pew idth[2] pew idth[3] vss pe3rn[2] pe3rp[2] vccpe pe3tp[ 1] pe3tn[1] vss pe3rn[0] rsvd w v vccpe vss vss vss pe3tn[3] pe3tp[3] vss pe3rn[1] pe3rp[1] vss pe3tn[0] pe3rp[0] vss v u vccpe vss vss pe3rn[3] pe3rp[3] vccpe pe3tn[2] pe3tp[2] vss pe2tp[1] pe3tp[0] vccpe pe2rn[3] u t vccpe vss vss vss vss pe2tp[0] pe2tn[0] vss pe2rp[0] pe2tn[1] vss pe2tn[3] pe2rp[3] t r vccpe peicompi pevccbg vccpe rsvd rsvd vss rsvd pe2rn[0] vccpe pe2rn[2] pe2tp[3] vss r p vccpe percompo vss rsvd rsvd vss rsvd rsvd vss pe2rn[1] pe2rp[2] vss pe2tn[2] p n vccpe vccpe pevssbg rsvd vss rsvd rsvd vccpe rsvd pe2rp[1] vss rsvd pe2tp[2] n m vccpe rsvd rsv1 vss pe6tp[0] pe6tn[0] vss rsvd rsvd vss rsvd rsvd vss m l vccpe gpiosmbdata vss pe4rn[3] vssquiet vccpe pe7tn[2] rsvd vss pe7rn[3] rsvd vccpe pevssa l k gpiosmbclk vss pe4tn[3] pe4rp[3] vss pe6rn[3] pe7tp[2] vss pe7tn[3] pe7rp[3] vss peclkn pevcca k j vss pe4tn[0] pe4tp[3] vccpe pe5tp[0] pe6rp[3] vss pe6tn[3] pe7tp[3] vss rsvd peclkp vss j h spd0smbclk pe4tp[0] vss pe5rp[0] pe5tn[0] vss pe5rn[3] pe6tp[3] vss pe7rn[2] pe7rp[2] vss rsvd h g spd0smbdata vccpe pe4rp[1] pe5rn[0] vss pe5rn[2] pe5rp[3] vss pe7tp[0] pe7tn[0] vss pe7tp[1] pe7tn[1] g f v3ref pe4rp[0] pe4rn[1] vss pe5tp[1] pe5rp[2] vss pe6rp[2] pe6rn[2] vss pe7rp[0] pe7rn[0] vss f e vss pe4rn[0] vss pe4rn[2] pe5tn[1] vss pe5tn[3] err[0]# vss pe6rp[1] pe6rn[1] vss pe7rn[1] e d xdpd[3]# vss pe4tn[2] pe4rp[2] vss pe5tp[2] pe5tp[3] vss pe6tp[1] pe6tn[1] vss err[2]# pe7rp[1] d c xdpdstbn# pe4tp[1] pe4tp[2] vss pe5rp[1] pe5tn[2] vss pe6rp[0] pe6rn[0] vss pe6tp[2] pe6tn[2] vss c b xdpd[6]# pe4tn[1] vss xdpd[1]# pe5rn[1] vss tdi tdo vss tdiocathode vss vss b a vs s xdpd[ 4]# xdp d[0]# xdp d[2]# v ss trst# tms tck err[1]# tdioanode vss a 13121110987654321
intel ? 5000x chipset memory controller hub (mch) datasheet 417 ballout and package information table 8-1. intel 5000x chipset mch signals (by ball number) (sheet 1 of 19) ball no. signal name buffer type direction b all no. signal name buffer type direction a3 vss power/other b6 tdo jtag ouput a4 tdioanode analog b7 tdi jtag i a5 err[1]# cmos o b8 vss power/other a6 tck jtag i b9 pe5rn[1] pex i a7 tms jtag i b10 xdpd[1]# xdp i/o a8 trst# jtag i b11 vss power/other a9 vss power/other b12 pe4tn[1] pex o a10 xdpd[2]# xdp i/o b13 xdpd[6]# xdp i/o a11 xdpd[0]# xdp i/o b14 xdpd[7]# xdp i/o a12 xdpd[4]# xdp i/o b15 xdpd[9]# xdp i/o a13 vss power/other b16 vss power/other a14 xdpd[10]# xdp i/o b17 vss power/other a15 xdpd[13]# xdp i/o b18 fbd3nbip[3] fbd i a16 xdpd[11]# xdp i/o b19 fbd3nbin[4] fbd i a17 xdprdy# xdp i/o b20 vss power/other a18 vss power/other b21 fbd3nbin[12] fbd i a19 fbd3nbip[4] fbd i b22 fbd3nbip[6] fbd i a20 vccfbd power/other b23 vss power/other a21 vss power/other b24 fbd3nbin[8] fbd i a22 fbd3nbin[6] fbd i b25 fbd2nbin[0] fbd i a23 vss power/other b26 fbd2nbip[1] fbd i a24 fbd3nbip[8] fbd i b27 fbd2nbip[2] fbd i a25 vss power/other b28 fbd2nbin[3] fbd i a26 fbd2nbin[1] fbd i b29 fbd2nbip[4] fbd i a27 fbd2nbin[2] fbd i b30 fbd2nbip[5] fbd i a28 vss power/other b31 fbd2nbin[13] fbd i a29 fbd2nbin[4] fbd i b32 fbd2nbip[12] fbd i a30 fbd2nbin[5] fbd i b33 fbd2nbip[6] fbd i a31 vss power/other b34 fbd2nbin[7] fbd i a32 fbd2nbin[12] fbd i b35 fbd2nbip[8] fbd i a33 fbd2nbin[6] fbd i b36 fbd2nbin[9] fbd i a34 vss power/other b37 vss power/other a35 fbd2nbin[8] fbd i c1 vss power/other a36 vss power/other c2 pe6tn[2] pex o b2 vss power/other c3 pe6tp[2] pex o b3 vss power/other c4 vss power/other b4 tdiocathode analog c5 pe6rn[0] pex i b5 vss power/other c6 pe6rp[0] pex i c7 vss power/other d7 pe5tp[3] pex o
ballout and package information 418 intel ? 5000x chipset memory controller hub (mch) datasheet c8 pe5tn[2] pex o d8 pe5tp[2] pex o c9 pe5rp[1] pex i d9 vss power/other c10 vss power/other d10 pe4rp[2] pex i c11 pe4tp[2] pex o d11 pe4tn[2] pex o c12 pe4tp[1] pex o d12 vss power/other c13 xdpdstbn# xdp i/o d13 xdpd[3]# xdp i/o c14 xdpdstbp# xdp i/o d14 vss power/other c15 vss power/other d15 xdpd[8]# xdp i/o c16 xdpd[12]# xdp i/o d16 xdpd[14]# xdp i/o c17 fbd3nbip[2] fbd i d17 fbd3nbin[2] fbd i c18 fbd3nbin[3] fbd i d18 vss power/other c19 vss power/other d19 fbd3nbip[5] fbd i c20 fbd3nbin[13] fbd i d20 fbd3nbip[13] fbd i c21 fbd3nbip[12] fbd i d21 vss power/other c22 vss power/other d22 fbd3sbop[0] fbd o c23 fbd3nbin[7] fbd i d23 fbd3nbip[7] fbd i c24 vss power/other d24 vss power/other c25 fbd2nbip[0] fbd i d25 fbd3nbip[11] fbd i c26 vss power/other d26 fbd3nbin[11] fbd i c27 vss power/other d27 vss power/other c28 fbd2nbip[3] fbd i d28 fbd23clkp analog c29 vss power/other d29 rsvd no connect c30 vss power/other d30 vss power/other c31 fbd2nbip[13] fbd i d31 fbd2sbop[3] fbd o c32 vss power/other d32 fbd2sbon[3] fbd o c33 vss power/other d33 vss power/other c34 fbd2nbip[7] fbd i d34 fbd2sbop[5] fbd o c35 vss power/other d35 fbd2sbon[5] fbd o c36 fbd2nbip[9] fbd i d36 vss power/other c37 fbd2nbip[10] fbd i d37 fbd2nbin[10] fbd i c38 vss power/other d38 fbd2nbip[11] fbd i d1 pe7rp[1] pex i e1 pe7rn[1] pex i d2 err[2]# cmos o e2 vss power/other d3 vss power/other e3 pe6rn[1] pex i d4 pe6tn[1] pex o e4 pe6rp[1] pex i d5 pe6tp[1] pex o e5 vss power/other d6 vss power/other e6 err[0]# cmos o e7 pe5tn[3] pex o f7 vss power/other e8 vss power/other f8 pe5rp[2] pex i table 8-1. intel 5000x chipset mch signals (by ball number) (sheet 2 of 19) ball no. signal name buffer type direction ball no. signal name buffer type direction
intel ? 5000x chipset memory controller hub (mch) datasheet 419 ballout and package information e9 pe5tn[1] pex o f9 pe5tp[1] pex o e10 pe4rn[2] pex i f10 vss power/other e11 vss power/other f11 pe4rn[1] pex i e12 pe4rn[0] pex i f12 pe4rp[0] pex i e13 vss power/other f13 v3ref analog e14 xdpd[5]# xdp i/o f14 xdpcomcres analog e15 spd2smbdata smb i/o f15 spd2smbclk smb i/o e16 xdpd[15]# xdp i/o f16 vss power/other e17 vss power/other f17 testhi_v3ref power/other e18 fbd3nbin[1] fbd i f18 fbd3nbip[1] fbd i e19 fbd3nbin[5] fbd i f19 vss power/other e20 vccfbd power/other f20 fbd3nbin[0] fbd i e21 vss power/other f21 vss power/other e22 fbd3sbon[0] fbd o f22 vss power/other e23 vccfbd power/other f23 fbd3nbip[9] fbd i e24 fbd3nbip[10] fbd i f24 fbd3nbin[9] fbd i e25 fbd3nbin[10] fbd i f25 vccfbd power/other e26 vss power/other f26 vss power/other e27 fbd23vcca power/other f27 fbd23vssa power/other e28 fbd23clkn analog i f28 vss power/other e29 vss power/other f29 fbd2sbop[1] fbd o e30 fbd2sbop[2] fbd o f30 fbd2sbon[1] fbd o e31 fbd2sbon[2] fbd o f31 vss power/other e32 vss power/other f32 fbd2sbop[4] fbd o e33 fbd2sbop[9] fbd o f33 fbd2sbon[4] fbd o e34 fbd2sbon[9] fbd o f34 vss power/other e35 vss power/other f35 fbdicompbias analog e36 fbdresin analog f36 fbd1nbip[9] fbd i e37 fbdbgbiasext analog f37 fbd1nbin[9] fbd i e38 fbd2nbin[11] fbd i f38 vss power/other f1 vss power/other g1 pe7tn[1] pex o f2 pe7rn[0] pex i g2 pe7tp[1] pex o f3 pe7rp[0] pex i g3 vss power/other f4 vss power/other g4 pe7tn[0] pex o f5 pe6rn[2] pex i g5 pe7tp[0] pex o f6 pe6rp[2] pex i g6 vss power/other g7 pe5rp[3] pex i h7 pe5rn[3] pex i g8 pe5rn[2] pex i h8 vss power/other g9 vss power/other h9 pe5tn[0] pex o table 8-1. intel 5000x chipset mch signals (by ball number) (sheet 3 of 19) ball no. signal name buffer type direction b all no. signal name buffer type direction
ballout and package information 420 intel ? 5000x chipset memory controller hub (mch) datasheet g10 pe5rn[0] pex i h10 pe5rp[0] pex i g11 pe4rp[1] pex i h11 vss power/other g12 vccpe power/other h12 pe4tp[0] pex o g13 spd0smbdata smb i/o h13 spd0smbclk smb i/o g14 xdpodtcres analog h14 vss power/other g15 vss power/other h15 spd3smbclk smb i/o g16 testhi_v3ref power/other h16 spd3smbdata smb i/o g17 reseti# cmos i h17 pwrgood cmos i g18 vss power/other h18 fbd3sbop[7] fbd o g19 fbd3sbop[6] fbd o h19 fbd3sbon[6] fbd o g20 fbd3nbip[0] fbd i h20 vccfbd power/other g21 vss power/other h21 fbd3sbon[9] fbd o g22 fbd3sbon[4] fbd o h22 fbd3sbop[9] fbd o g23 fbd3sbop[4] fbd o h23 vccfbd power/other g24 vss power/other h24 fbd3sbon[2] fbd o g25 fbd3sbon[1] fbd o h25 fbd3sbop[2] fbd o g26 fbd3sbop[1] fbd o h26 vss power/other g27 vss power/other h27 vss power/other g28 fbd2sbop[0] fbd o h28 vss power/other g29 fbd2sbon[0] fbd o h29 vss power/other g30 vss power/other h30 vss power/other g31 vss power/other h31 vss power/other g32 vss power/other h32 vss power/other g33 vss power/other h33 fbd2sbop[7] fbd o g34 fbd2sbop[6] fbd o h34 fbd2sbon[7] fbd o g35 fbd2sbon[6] fbd o h35 vss power/other g36 vss power/other h36 fbd1nbip[10] fbd i g37 vss power/other h37 fbd1nbin[10] fbd i g38 fbd1nbip[11] fbd i h38 fbd1nbin[11] fbd i h1 rsvd no connect j1 vss power/other h2 vss power/other j2 peclkp analog h3 pe7rp[2] pex i j3 rsvd no connect h4 pe7rn[2] pex i j4 vss power/other h5 vss power/other j5 pe7tp[3] pex o h6 pe6tp[3] pex o j6 pe6tn[3] pex o j7 vss power/other k7 pe7tp[2] pex o j8 pe6rp[3] pex i k8 pe6rn[3] pex i j9 pe5tp[0] pex o k9 vss power/other j10 vccpe power/other k10 pe4rp[3] pex i table 8-1. intel 5000x chipset mch signals (by ball number) (sheet 4 of 19) ball no. signal name buffer type direction ball no. signal name buffer type direction
intel ? 5000x chipset memory controller hub (mch) datasheet 421 ballout and package information j11 pe4tp[3] pex o k11 pe4tn[3] pex o j12 pe4tn[0] pex o k12 vss power/other j13 vss power/other k13 gpiosmbclk smb i/o j14 cfgsmbdata smb i/o k14 cfgsmbclk smb i/o j15 xdpslwcres analog k15 spd1smbdata smb i/o j16 spd1smbclk smb i/o k16 vss power/other j17 vss power/other k17 vss power/other j18 fbd3sbon[7] fbd o k18 fbd3sbon[8] fbd o j19 vss power/other k19 fbd3sbop[8] fbd o j20 fbd3sbon[5] fbd o k20 vss power/other j21 fbd3sbop[5] fbd o k21 vccfbd power/other j22 vss power/other k22 vccfbd power/other j23 fbd3sbon[3] fbd o k23 vccfbd power/other j24 fbd3sbop[3] fbd o k24 vss power/other j25 vss power/other k25 vss power/other j26 vss power/other k26 vss power/other j27 vss power/other k27 vss power/other j28 vss power/other k28 vss power/other j29 vss power/other k29 vss power/other j30 vss power/other k30 vss power/other j31 vss power/other k31 fbd1nbip[13] fbd i j32 fbd2sbop[8] fbd o k32 fbd1nbin[13] fbd i j33 fbd2sbon[8] fbd o k33 vss power/other j34 vss power/other k34 fbd1nbip[7] fbd i j35 fbd1nbip[8] fbd i k35 fbd1nbin[8] fbd i j36 fbd1sbop[0] fbd o k36 vss power/other j37 fbd1sbon[0] fbd o k37 vss power/other j38 vss power/other k38 fbd1sbop[2] fbd o k1 pevcca analog l1 pevssa analog k2 peclkn analog l2 vccpe power/other k3 vss power/other l3 rsvd no connect k4 pe7rp[3] pex i l4 pe7rn[3] pex i k5 pe7tn[3] pex o l5 vss power/other k6 vss power/other l6 rsvd no connect l7 pe7tn[2] pex o m7 vss power/other l8 vccpe power/other m8 pe6tn[0] pex o l9 vssquiet analog m9 pe6tp[0] pex o l10 pe4rn[3] pex i m10 vss power/other l11 vss power/other m11 rsv1 no connect table 8-1. intel 5000x chipset mch signals (by ball number) (sheet 5 of 19) ball no. signal name buffer type direction b all no. signal name buffer type direction
ballout and package information 422 intel ? 5000x chipset memory controller hub (mch) datasheet l12 gpiosmbdata smb i/o m12 rsvd no connect l13 vccpe power/other m13 vccpe power/other l14 vccpe power/other m14 vccpe power/other l15 vccpe power/other m15 vccpe power/other l16 vcc power/other m16 vcc power/other l17 vcc power/other m17 vcc power/other l18 vcc power/other m18 vcc power/other l19 vcc power/other m19 vss power/other l20 vccfbd power/other m20 vccfbd power/other l21 vccfbd power/other m21 vccfbd power/other l22 vccfbd power/other m22 vccfbd power/other l23 vccfbd power/other m23 vccfbd power/other l24 vccsen temp m24 vccfbd power/other l25 vsssen temp m25 vccfbd power/other l26 vss power/other m26 fbd1nbip[1] fbd i l27 fbd1nbip[2] fbd i m27 fbd1nbin[1] fbd i l28 fbd1nbin[2] fbd i m28 vss power/other l29 vss power/other m29 fbd1nbip[4] fbd i l30 fbd1nbip[5] fbd i m30 fbd1nbin[4] fbd i l31 fbd1nbin[5] fbd i m31 vss power/other l32 vss power/other m32 fbd1nbip[12] fbd i l33 fbd1nbip[6] fbd i m33 fbd1nbin[6] fbd i l34 fbd1nbin[7] fbd i m34 vss power/other l35 vss power/other m35 fbd1sbop[3] fbd o l36 fbd1sbop[1] fbd o m36 fbd1sbon[3] fbd o l37 fbd1sbon[1] fbd o m37 vss power/other l38 fbd1sbon[2] fbd o m38 vss power/other m1 vss power/other n1 pe2tp[2] pex o m2 rsvd no connect n2 rsvd no connect m3 rsvd no connect n3 vss power/other m4 vss power/other n4 pe2rp[1] pex i m5 rsvd no connect n5 rsvd no connect m6 rsvd no connect n6 vccpe power/other n7 rsvd no connect p7 rsvd no connect n8 rsvd no connect p8 vss power/other n9 vss power/other p9 rsvd no connect n10 rsvd no connect p10 rsvd no connect n11 pevssbg analog p11 vss power/other n12 vccpe power/other p12 percompo analog table 8-1. intel 5000x chipset mch signals (by ball number) (sheet 6 of 19) ball no. signal name buffer type direction ball no. signal name buffer type direction
intel ? 5000x chipset memory controller hub (mch) datasheet 423 ballout and package information n13 vccpe power/other p13 vccpe power/other n14 vccpe power/other p14 vccpe power/other n15 vccpe power/other p15 vss power/other n16 vss power/other p16 vcc power/other n17 vcc power/other p17 vss power/other n18 vss power/other p18 vcc power/other n19 vcc power/other p19 vss power/other n20 vccfbd power/other p20 vcc power/other n21 vccfbd power/other p21 vss power/other n22 vccfbd power/other p22 vcc power/other n23 vccfbd power/other p23 vss power/other n24 vccfbd power/other p24 vcc power/other n25 vccfbd power/other p25 vccfbd power/other n26 vccfbd power/other p26 vccfbd power/other n27 vss power/other p27 fbd1nbip[0] fbd i n28 fbd1nbip[3] fbd i p28 fbd1nbin[0] fbd i n29 fbd1nbin[3] fbd i p29 vss power/other n30 vss power/other p30 vss power/other n31 vss power/other p31 vss power/other n32 fbd1nbin[12] fbd i p32 vss power/other n33 vss power/other p33 fbd1sbon[7] fbd o n34 fbd1sbop[4] fbd o p34 fbd1sbop[7] fbd o n35 fbd1sbon[4] fbd o p35 vss power/other n36 vss power/other p36 fbd1sbon[5] fbd o n37 fbd1sbon[9] fbd o p37 fbd1sbop[5] fbd o n38 fbd1sbop[9] fbd o p38 vss power/other p1 pe2tn[2] pex o r1 vss power/other p2 vss power/other r2 pe2tp[3] pex o p3 pe2rp[2] pex i r3 pe2rn[2] pex i p4 pe2rn[1] pex i r4 vccpe power/other p5 vss power/other r5 pe2rn[0] pex i p6 rsvd no connect r6 rsvd no connect r7 vss power/other t7 pe2tn[0] pex o r8 rsvd no connect t8 pe2tp[0] pex o r9 rsvd no connect t9 vss power/other r10 vccpe power/other t10 vss power/other r11 pevccbg analog t11 vss power/other r12 peicompi analog t12 vss power/other r13 vccpe power/other t13 vccpe power/other table 8-1. intel 5000x chipset mch signals (by ball number) (sheet 7 of 19) ball no. signal name buffer type direction b all no. signal name buffer type direction
ballout and package information 424 intel ? 5000x chipset memory controller hub (mch) datasheet r14 vccpe power/other t14 vccpe power/other r15 vcc power/other t15 vss power/other r16 vss power/other t16 vcc power/other r17 vcc power/other t17 vss power/other r18 vss power/other t18 vcc power/other r19 vcc power/other t19 vss power/other r20 vss power/other t20 vcc power/other r21 vcc power/other t21 vss power/other r22 vss power/other t22 vcc power/other r23 vcc power/other t23 vss power/other r24 vss power/other t24 vcc power/other r25 vccfbd power/other t25 vccfbd power/other r26 vss power/other t26 vccfbd power/other r27 vss power/other t27 vccfbd fbd i r28 vss power/other t28 fbd0nbin[4] fbd i r29 vss power/other t29 vss power/other r30 vss power/other t30 vss power/other r31 vss power/other t31 fbd0nbip[6] fbd i r32 fbd1sbon[8] fbd o t32 fbd0nbin[6] fbd i r33 fbd1sbop[8] fbd o t33 vss power/other r34 vss power/other t34 fbd01vssa power/other r35 fbd1sbon[6] fbd o t35 fbd01vcca power/other r36 fbd1sbop[6] fbd o t36 vss power/other r37 vss power/other t37 rsvd no connect r38 fbd01clkp analog i t38 fbd01clkn analog i t1 pe2rp[3] pex i u1 pe2rn[3] pex i t2 pe2tn[3] pex o u2 vccpe power/other t3 vss power/other u3 pe3tp[0] pex o t4 pe2tn[1] pex o u4 pe2tp[1] pex o t5 pe2rp[0] pex i u5 vss power/other t6 vss power/other u6 pe3tp[2] pex o u7 pe3tn[2] pex o v7 vss power/other u8 vccpe power/other v8 pe3tp[3] pex o u9 pe3rp[3] pex i v9 pe3tn[3] pex o u10 pe3rn[3] pex i v10 vss power/other u11 vss power/other v11 vss power/other u12 vss power/other v12 vss power/other u13 vccpe power/other v13 vccpe power/other u14 vccpe power/other v14 vccpe power/other table 8-1. intel 5000x chipset mch signals (by ball number) (sheet 8 of 19) ball no. signal name buffer type direction ball no. signal name buffer type direction
intel ? 5000x chipset memory controller hub (mch) datasheet 425 ballout and package information u15 vcc power/other v15 vss power/other u16 vss power/other v16 vcc power/other u17 vcc power/other v17 vss power/other u18 vss power/other v18 vcc power/other u19 vcc power/other v19 vss power/other u20 vss power/other v20 vcc power/other u21 vcc power/other v21 vss power/other u22 vss power/other v22 vcc power/other u23 vcc power/other v23 vss power/other u24 vss power/other v24 vcc power/other u25 vccfbd power/other v25 vccfbd power/other u26 vccfbd power/other v26 vccfbd power/other u27 fbd0nbin[3] fbd i v27 fbd0nbip[3] fbd i u28 fbd0nbip[4] fbd i v28 vss power/other u29 vss power/other v29 fbd0nbip[13] fbd i u30 fbd0nbip[12] fbd i v30 fbd0nbin[13] fbd i u31 fbd0nbin[12] fbd i v31 vss power/other u32 vss power/other v32 fbd0nbip[7] fbd i u33 fbd0nbip[8] fbd i v33 fbd0nbin[7] fbd i u34 fbd0nbin[8] fbd i v34 vss power/other u35 vss power/other v35 fbd0nbip[10] fbd i u36 fbd0nbip[11] fbd i v36 fbd0nbin[10] fbd i u37 fbd0nbin[11] fbd i v37 vss power/other u38 vss power/other v38 fbd0sbop[1] fbd o v1 vss power/other w1 rsvd no connect v2 pe3rp[0] pex i w2 pe3rn[0] pex i v3 pe3tn[0] pex o w3 vss power/other v4 vss power/other w4 pe3tn[1] pex o v5 pe3rp[1] pex i w5 pe3tp[1] pex o v6 pe3rn[1] pex i w6 vccpe power/other w7 pe3rp[2] pex i y7 pe0tp[0] pex o w8 pe3rn[2] pex i y8 vss power/other w9 vss power/other y9 pe0rn[0] pex i w10 pewidth[3] power/other i y10 pe0rp[0] pex i w11 pewidth[2] power/other i y11 vss power/other w12 vccpe power/other y12 pewidth[1] power/other i w13 vccpe power/other y13 vccpe power/other w14 vccpe power/other y14 vccpe power/other w15 vcc power/other y15 vss power/other table 8-1. intel 5000x chipset mch signals (by ball number) (sheet 9 of 19) ball no. signal name buffer type direction b all no. signal name buffer type direction
ballout and package information 426 intel ? 5000x chipset memory controller hub (mch) datasheet w16 vss power/other y16 vcc power/other w17 vcc power/other y17 vss power/other w18 vss power/other y18 vcc power/other w19 vcc power/other y19 vss power/other w20 vss power/other y20 vcc power/other w21 vcc power/other y21 vss power/other w22 vss power/other y22 vcc power/other w23 vcc power/other y23 vss power/other w24 vss power/other y24 vcc power/other w25 vccfbd power/other y25 vccfbd power/other w26 vccfbd power/other y26 vccfbd power/other w27 vss power/other y27 fbd0nbip[0] fbd i w28 fbd0nbip[5] fbd i y28 fbd0nbin[0] fbd i w29 fbd0nbin[5] fbd i y29 vss power/other w30 vss power/other y30 fbd0nbip[1] fbd i w31 fbd0sbon[0] fbd o y31 fbd0nbin[1] fbd i w32 fbd0sbop[0] fbd o y32 vss power/other w33 vss power/other y33 fbd0sbon[3] fbd o w34 fbd0nbip[9] fbd i y34 fbd0sbop[3] fbd o w35 fbd0nbin[9] fbd i y35 vss power/other w36 vss power/other y36 fbd0sbop[4] fbd o w37 vss power/other y37 fbd0sbon[4] fbd o w38 fbd0sbon[1] fbd o y38 vss power/other y1 rsvd no connect aa1 vss power/other y2 vss power/other aa2 pe0tn[1] pex o y3 pe0rn[1] pex i aa3 pe0tp[1] pex o y4 pe0rp[1] pex i aa4 vss power/other y5 vss power/other aa5 pe0rp[3] pex i y6 pe0tn[0] pex o aa6 pe0rn[3] pex i aa7 vss power/other ab7 pe0rn[2] pex i aa8 pe0tp[3] pex o ab8 pe0rp[2] pex i aa9 pe0tn[3] pex o ab9 vss power/other aa10 vss power/other ab10 fsb1a[14]# source sync i/o aa11 pewidth[0] power/other i ab11 fsb1a[10]# source sync i/o aa12 fsb1a[16]# source sync i/o ab12 vss power/other aa13 vccsf power/other ab13 vccsf power/other aa14 vss power/other ab14 vccsf power/other aa15 vcc power/other ab15 vss power/other aa16 vss power/other ab16 vcc power/other table 8-1. intel 5000x chipset mch signals (by ball number) (sheet 10 of 19) ball no. signal name buffer type direction ball no. signal name buffer type direction
intel ? 5000x chipset memory controller hub (mch) datasheet 427 ballout and package information aa17 vcc power/other ab17 vss power/other aa18 vss power/other ab18 vcc power/other aa19 vcc power/other ab19 vss power/other aa20 vss power/other ab20 vcc power/other aa21 vcc power/other ab21 vss power/other aa22 vss power/other ab22 vcc power/other aa23 vcc power/other ab23 vss power/other aa24 vss power/other ab24 vcc power/other aa25 vccfbd power/other ab25 vccfbd power/other aa26 vccfbd power/other ab26 vccfbd power/other aa27 vccfbd power/other ab27 vss power/other aa28 vss power/other ab28 vss power/other aa29 vss power/other ab29 vss power/other aa30 vss power/other ab30 vss power/other aa31 vss power/other ab31 fbd0nbip[2] fbd i aa32 fbd0sbop[2] fbd o ab32 fbd0nbin[2] fbd i aa33 fbd0sbon[2] fbd o ab33 vss power/other aa34 vss power/other ab34 fbd0sbon[7] fbd o aa35 fbd0sbon[9] fbd o ab35 fbd0sbop[7] fbd o aa36 fbd0sbop[9] fbd o ab36 vss power/other aa37 vss power/other ab37 fbd0sbop[6] fbd o aa38 fbd0sbop[5] fbd o ab38 fbd0sbon[5] fbd o ab1 psel[2] cmos i ac1 psel[0] cmos i ab2 psel[1] cmos i ac2 vss power/other ab3 vss power/other ac3 fsb1a[35]# source sync i/o ab4 pe0tp[2] pex o ac4 fsb1a[34]# source sync i/o ab5 pe0tn[2] pex o ac5 vss power/other ab6 vss power/other ac6 fsb1a[22]# source sync i/o ac7 fsb1a[15]# source sync i/o ad7 vss power/other ac8 vss power/other ad8 fsb1a[12]# source sync i/o ac9 fsb1a[13]# source sync i/o ad9 fsb1a[4]# source sync i/o ac10 fsb1adstb[0]# source sync i/o ad10 vss power/other ac11 vss power/other ad11 fsb1req[1]# source sync i/o ac12 fsb1a[5]# source sync i/o ad12 fsb1a[3]# source sync i/o ac13 vtt power/other ad13 vtt power/other ac14 vtt power/other ad14 vtt power/other ac15 vcc power/other ad15 vtt power/other ac16 vss power/other ad16 vtt power/other ac17 vcc power/other ad17 vtt power/other table 8-1. intel 5000x chipset mch signals (by ball number) (sheet 11 of 19) ball no. signal name buffer type direction b all no. signal name buffer type direction
ballout and package information 428 intel ? 5000x chipset memory controller hub (mch) datasheet ac18 vss power/other ad18 vtt power/other ac19 vcc power/other ad19 vtt power/other ac20 vss power/other ad20 vtt power/other ac21 vcc power/other ad21 vtt power/other ac22 vss power/other ad22 vtt power/other ac23 vcc power/other ad23 vtt power/other ac24 vss power/other ad24 vtt power/other ac25 vccsf power/other ad25 vtt power/other ac26 vccsf power/other ad26 vccsf power/other ac27 vss power/other ad27 vss power/other ac28 vss power/other ad28 vss power/other ac29 vss power/other ad29 fsb0d[46]# source sync i/o ac30 fsb0d[42]# source sync i/o ad30 fsb0d[41]# source sync i/o ac31 fsb0d[44]# source sync i/o ad31 vss power/other ac32 vss power/other ad32 fsb0dstbn[2]# source sync i/o ac33 fbd0sbon[8] fbd o ad33 fsb0dstbp[2]# source sync i/o ac34 fbd0sbop[8] fbd o ad34 vss power/other ac35 vss power/other ad35 fsb0d[38]# source sync i/o ac36 testhi no connect ad36 vss power/other ac37 fbd0sbon[6] fbd o ad37 vss power/other ac38 vss power/other ad38 vss power/other ad1 vss power/other ae1 fsb1a[32]# source sync i/o ad2 fsb1a[33]# source sync i/o ae2 fsb1a[31]# source sync i/o ad3 fsb1a[29]# source sync i/o ae3 vss power/other ad4 vss power/other ae4 fsb1a[30]# source sync i/o ad5 fsb1a[23]# source sync i/o ae5 fsb1a[21]# source sync i/o ad6 fsb1a[20]# source sync i/o ae6 vss power/other ae7 fsb1a[9]# source sync i/o af7 fsb1a[8]# source sync i/o ae8 rsvd no connect af8 vss power/other ae9 vss power/other af9 fsb1req[3]# source sync i/o ae10 fsb1req[4]# source sync i/o af10 vss power/other ae11 fsb1reset# common clk i af11 vss power/other ae12 vss power/other af12 fsb1dp[2]# common clk i/o ae13 vtt power/other af13 fsb1dp[3]# common clk i/o ae14 vtt power/other af14 vss power/other ae15 vtt power/other af15 fsb1d[58]# source sync i/o ae16 vtt power/other af16 fsb1d[63]# source sync i/o ae17 vtt power/other af17 vss power/other ae18 vtt power/other af18 vtt power/other table 8-1. intel 5000x chipset mch signals (by ball number) (sheet 12 of 19) ball no. signal name buffer type direction ball no. signal name buffer type direction
intel ? 5000x chipset memory controller hub (mch) datasheet 429 ballout and package information ae19 vtt power/other af19 vtt power/other ae20 vtt power/other af20 vtt power/other ae21 vtt power/other af21 vtt power/other ae22 vtt power/other af22 fsb0a[16]# source sync i/o ae23 vtt power/other af23 vss power/other ae24 vtt power/other af24 vss power/other ae25 vtt power/other af25 fsb0a[14]# source sync i/o ae26 vtt power/other af26 vss power/other ae27 vss power/other af27 vss power/other ae28 fsb0d[47]# source sync i/o af28 fsb0d[45]# source sync i/o ae29 fsb0d[43]# source sync i/o af29 vss power/other ae30 vss power/other af30 fsb0dbi[2]# source sync i/o ae31 fsb0d[40]# source sync i/o af31 fsb0d[35]# source sync i/o ae32 fsb0d[39]# source sync i/o af32 vss power/other ae33 vss power/other af33 fsb0d[37]# source sync i/o ae34 fsb0d[34]# source sync i/o af34 fsb0vref power/other ae35 vccsf power/other af35 vss power/other ae36 fsb0d[62]# source sync i/o af36 vss power/other ae37 fsb0d[63]# source sync i/o af37 fsb0d[48]# source sync i/o ae38 fsb0d[58]# source sync i/o af38 fsb0d[59]# source sync i/o af1 fsb1a[27]# source sync i/o ag1 vss power/other af2 vss power/other ag2 rsvd no connect af3 fsb1a[28]# source sync i/o ag3 fsb1adstb[1]# source sync i/o af4 fsb1a[17]# source sync i/o ag4 vss power/other af5 vss power/other ag5 fsb1a[18]# source sync i/o af6 fsb1a[11]# source sync i/o ag6 rsvd no connect ag7 vss power/other ah7 rsvd no connect ag8 fsb1a[7]# source sync i/o ah8 fsb1a[6]# source sync i/o ag9 fsb1req[0]# source sync i/o ah9 vss power/other ag10 fsb1ap[1]# common clk i/o ah10 vccsf power/other ag11 fsb1dp[0]# common clk i/o ah11 fsb1mcerr# common clk i/o ag12 fsb1ap[0]# common clk i/o ah12 vss power/other ag13 vss power/other ah13 fsb1dbi[3]# source sync i/o ag14 fsb1d[62]# source sync i/o ah14 fsb1d[48]# source sync i/o ag15 fsb1d[59]# source sync i/o ah15 vss power/other ag16 vss power/other ah16 fsb1d[54]# source sync i/o ag17 vss power/other ah17 vss no connect ag18 vtt power/other ah18 vtt power/other ag19 vtt power/other ah19 vtt power/other table 8-1. intel 5000x chipset mch signals (by ball number) (sheet 13 of 19) ball no. signal name buffer type direction b all no. signal name buffer type direction
ballout and package information 430 intel ? 5000x chipset memory controller hub (mch) datasheet ag20 vtt power/other ah20 vtt power/other ag21 vtt power/other ah21 vtt power/other ag22 vss power/other ah22 fsb0a[13]# source sync i/o ag23 fsb0a[15]# source sync i/o ah23 fsb0a[8]# source sync i/o ag24 fsb0a[10]# source sync i/o ah24 vss power/other ag25 vss power/other ah25 fsb0req[1]# source sync i/o ag26 fsb0breq[1]# common clk i/o ah26 fsb0ap[0]# common clk i/o ag27 fsb0d[14]# source sync i/o ah27 vss power/other ag28 vss power/other ah28 fsb0d[2]# source sync i/o ag29 fsb0d[13]# source sync i/o ah29 fsb0d[4]# source sync i/o ag30 fsb0d[33]# source sync i/o ah30 vss power/other ag31 vss power/other ah31 fsb0d[11]# source sync i/o ag32 fsb0d[36]# source sync i/o ah32 fsb0d[9]# source sync i/o ag33 fsb0d[32]# source sync i/o ah33 vss power/other ag34 vss power/other ah34 fsb0dstbn[3]# source sync i/o ag35 fsb0d[54]# source sync i/o ah35 fsb0dstbp[3]# source sync i/o ag36 fsb0d[60]# source sync i/o ah36 fsb0d[61]# source sync i/o ag37 vss power/other ah37 fsb0dbi[3]# source sync i/o ag38 vss power/other ah38 fsb0d[57]# source sync i/o ah1 fsb1a[25]# source sync i/o aj1 rsvd no connect ah2 fsb1a[24]# source sync i/o aj2 vss power/other ah3 vss power/other aj3 fsb1a[26]# source sync i/o ah4 fsb1vref power/other aj4 fsb1binit# common clk i/o ah5 fsb1a[19]# source sync i/o aj5 vss power/other ah6 vss power/other aj6 fsb1req[2]# source sync i/o aj7 fsb1hitm# common clk i/o ak7 vss power/other aj8 vss power/other ak8 fsb1hit# common clk i/o aj9 fsb1defer# common clk o ak9 fsb1d[19]# source sync i/o aj10 fsb1bpri# common clk o ak10 vss power/other aj11 vss power/other ak11 fsb1dbi[1]# source sync i/o aj12 fsb1dp[1]# common clk i/o ak12 fsb1d[31]# source sync i/o aj13 fsb1d[57]# source sync i/o ak13 vss power/other aj14 vss power/other ak14 fsb1dstbn[3]# source sync i/o aj15 fsb1d[60]# source sync i/o ak15 fsb1dstbp[3]# source sync i/o aj16 fsb1d[61]# source sync i/o ak16 vss power/other aj17 vss power/other ak17 rsvd no connect aj18 vtt power/other ak18 vtt power/other aj19 vtt power/other ak19 vtt power/other aj20 vtt power/other ak20 vtt power/other table 8-1. intel 5000x chipset mch signals (by ball number) (sheet 14 of 19) ball no. signal name buffer type direction ball no. signal name buffer type direction
intel ? 5000x chipset memory controller hub (mch) datasheet 431 ballout and package information aj21 vtt power/other ak21 vtt power/other aj22 fsb0a[11]# source sync i/o ak22 vss power/other aj23 vss power/other ak23 rsvd no connect aj24 fsb0req[3]# source sync i/o ak24 fsb0req[2]# source sync i/o aj25 fsb0req[4]# source sync i/o ak25 vss power/other aj26 vss power/other ak26 fsb0ap[1]# source sync i/o aj27 fsb0mcerr# common clk i/o ak27 fsb0binit# common clk i/o aj28 fsb0d[0]# source sync i/o ak28 vss power/other aj29 vss power/other ak29 fsb0d[3]# source sync i/o aj30 fsb0d[10]# source sync i/o ak30 fsb0d[6]# source sync i/o aj31 fsb0d[8]# source sync i/o ak31 vss power/other aj32 vss power/other ak32 fsb0dstbn[0]# source sync i/o aj33 fsb0d[15]# source sync i/o ak33 fsb0dstbp[0]# source sync i/o aj34 fsb0d[49]# source sync i/o ak34 vss power/other aj35 vss power/other ak35 fsb0d[30]# source sync i/o aj36 vss power/other ak36 fsb0d[53]# source sync i/o aj37 fsb0d[55]# source sync i/o ak37 vss power/other aj38 fsb0d[56]# source sync i/o ak38 vss power/other ak1 vss power/other al1 fsb1rs[1]# common clk i ak2 fsb1rsp# common clk i al2 fsb1breq[0]# common clk i/o ak3 fsb1bnr# common clk i/o al3 vss power/other ak4 vss power/other al4 fsb1lock# common clk i/o ak5 fsb1rs[0]# common clk i al5 fsb1rs[2]# common clk i ak6 fsb1trdy# common clk o al6 vss power/other al7 fsb1d[16]# source sync i/o am7 rsvd no connect al8 fsb1d[17]# source sync i/o am8 vss power/other al9 vss power/other am9 fsb1d[21]# source sync i/o al10 fsb1dstbn[1]# source sync i/o am10 fsb1dstbp[1]# source sync i/o al11 fsb1d[29]# source sync i/o am11 vss power/other al12 vss power/other am12 fsb1d[26]# source sync i/o al13 fsb1d[30]# source sync i/o am13 fsb1d[28]# source sync i/o al14 fsb1d[52]# source sync i/o am14 vss power/other al15 vss power/other am15 fsb1d[51]# source sync i/o al16 fsb1d[56]# source sync i/o am16 fsb1d[49]# source sync i/o al17 vcc power/other am17 vss power/other al18 vtt power/other am18 vtt power/other al19 vtt power/other am19 vtt power/other al20 vtt power/other am20 vtt power/other al21 vtt power/other am21 vtt power/other table 8-1. intel 5000x chipset mch signals (by ball number) (sheet 15 of 19) ball no. signal name buffer type direction b all no. signal name buffer type direction
ballout and package information 432 intel ? 5000x chipset memory controller hub (mch) datasheet al22 fsb0a[12]# source sync i/o am22 fsb0a[9]# source sync i/o al23 fsb0adstb[0]# source sync i/o am23 vss power/other al24 vss power/other am24 rsvd no connect al25 fsb0a[3]# source sync i/o am25 fsb0a[5]# source sync i/o al26 fsb0req[0]# source sync i/o am26 vss power/other al27 vss power/other am27 fsb0vref power/other al28 fsb0rs[1]# common clk i am28 fsb0breq[0]# common clk i/o al29 fsb0d[1]# source sync i/o am29 vss power/other al30 vss power/other am30 fsb0vref power/other al31 fsb0d[7]# source sync i/o am31 rsvd no connect al32 fsb0dbi[0]# source sync i/o am32 vss power/other al33 vss power/other am33 fsb0d[12]# source sync i/o al34 fsb0d[17]# source sync i/o am34 fsb0d[29]# source sync i/o al35 fsb0d[25]# source sync i/o am35 vss power/other al36 fsb0d[51]# source sync i/o am36 vss power/other al37 fsb0d[52]# source sync i/o am37 fsb0d[31]# source sync i/o al38 fsb0d[50]# source sync i/o am38 fsb0d[28]# source sync i/o am1 fsb1breq[1]# common clk i/o an1 vss power/other am2 vss power/other an2 fsb1bpm[4]# common clk i/o am3 fsb1drdy# common clk i/o an3 fsb1bpm[5]# common clk i/o am4 fsb1dbsy# common clk i/o an4 vss power/other am5 vss power/other an5 fsb1vref power/other am6 fsb1d[20]# source sync i/o an6 fsb1d[18]# source sync i/o an7 vss power/other ap7 fsb1dbi[0]# source sync i/o an8 fsb1d[23]# source sync i/o ap8 fsb1d[22]# source sync i/o an9 fsb1d[24]# source sync i/o ap9 vss power/other an10 vss power/other ap10 fsb1dstbn[2]# source sync i/o an11 fsb1d[27]# source sync i/o ap11 fsb1d[44]# source sync i/o an12 fsb1d[25]# source sync i/o ap12 vss power/other an13 vss power/other ap13 fsb1d[43]# source sync i/o an14 fsb1d[50]# source sync i/o ap14 fsb1d[47]# source sync i/o an15 fsb1d[53]# source sync i/o ap15 vss power/other an16 vss power/other ap16 fsb1d[55]# source sync i/o an17 coreclkp analog i ap17 coreclkn analog i an18 vtt power/other ap18 vtt power/other an19 vtt power/other ap19 vtt power/other an20 vtt power/other ap20 vtt power/other an21 vtt power/other ap21 vtt power/other an22 vss power/other ap22 fsb0a[32]# source sync i/o table 8-1. intel 5000x chipset mch signals (by ball number) (sheet 16 of 19) ball no. signal name buffer type direction ball no. signal name buffer type direction
intel ? 5000x chipset memory controller hub (mch) datasheet 433 ballout and package information an23 rsvd no connect ap23 fsb0adstb[1]# source sync i/o an24 fsb0a[4]# source sync i/o ap24 vss power/other an25 vss power/other ap25 fsb0a[18]# source sync i/o an26 fsb0a[6]# source sync i/o ap26 fsb0a[7]# source sync i/o an27 fsb0rsp# common clk i ap27 vss power/other an28 vss power/other ap28 rsvd no connect an29 fsb0dp[3]# common clk i/o ap29 fsb0bpm[5]# common clk i/o an30 fsb0reset# common clk i ap30 vss power/other an31 vss power/other ap31 fsb0dp[2]# common clk i/o an32 fsb0d[5]# source sync i/o ap32 rsvd no connect an33 fsb0d[16]# source sync i/o ap33 vss power/other an34 vss power/other ap34 fsb0d[20]# source sync i/o an35 fsb0d[24]# source sync i/o ap35 fsb0d[18]# source sync i/o an36 fsb0d[26]# source sync i/o ap36 fsb0d[23]# source sync i/o an37 vss power/other ap37 fsb0dbi[1]# source sync i/o an38 vss power/other ap38 fsb0d[27]# source sync i/o ap1 fsb1d[0]# source sync i/o ar1 fsb1d[3]# source sync i/o ap2 fsb1ads# common clk i/o ar2 vss power/other ap3 vss power/other ar3 fsb1d[4]# source sync i/o ap4 fsb1d[2]# source sync i/o ar4 fsb1d[5]# source sync i/o ap5 fsb1d[1]# source sync i/o ar5 vss power/other ap6 vss power/other ar6 fsb1d[12]# source sync i/o ar7 fsb1d[14]# source sync i/o at7 vss power/other ar8 vss power/other at8 fsb1d[36]# source sync i/o ar9 fsb1d[35]# source sync i/o at9 fsb1d[34]# source sync i/o ar10 fsb1dstbp[2]# source sync i/o at10 vss power/other ar11 vss power/other at11 fsb1d[41]# source sync i/o ar12 fsb1d[46]# source sync i/o at12 fsb1d[42]# source sync i/o ar13 fsb1d[45]# source sync i/o at13 vss power/other ar14 vss power/other at14 fsb1vref power/other ar15 rsvd no connect at15 vss power/other ar16 rsvd no connect at16 vss power/other ar17 vss power/other at17 corevcca power/other ar18 vtt power/other at18 vtt power/other ar19 vtt power/other at19 vtt power/other ar20 vtt power/other at20 vtt power/other ar21 vtt power/other at21 vtt power/other ar22 fsb0a[33]# source sync i/o at22 vss power/other ar23 vss power/other at23 fsb0a[30]# source sync i/o table 8-1. intel 5000x chipset mch signals (by ball number) (sheet 17 of 19) ball no. signal name buffer type direction b all no. signal name buffer type direction
ballout and package information 434 intel ? 5000x chipset memory controller hub (mch) datasheet ar24 fsb0a[20]# source sync i/o at24 fsb0a[27]# source sync i/o ar25 fsb0a[26]# source sync i/o at25 vss power/other ar26 vss power/other at26 fsb0a[24]# source sync i/o ar27 fsb0a[19]# source sync i/o at27 fsb0a[23]# source sync i/o ar28 fsb0bpm[4]# common clk i/o at28 vss power/other ar29 vss power/other at29 fsb0drdy# common clk i/o ar30 fsb0dbsy# common clk i/o at30 fsb0lock# common clk i/o ar31 fsb0dp[0]# common clk i/o at31 vss power/other ar32 vss power/other at32 fsb0trdy# common clk o ar33 rsvd no connect at33 fsb0dp[1]# common clk i/o ar34 fsbodtcres analog at34 vss power/other ar35 vss power/other at35 fsbcres analog ar36 vss power/other at36 fsb0d[19]# source sync i/o ar37 fsb0dstbn[1]# source sync i/o at37 fsb0d[22]# source sync i/o ar38 fsb0dstbp[1]# source sync i/o at38 vss power/other at1 vss power/other au2 vss power/other at2 fsb1d[6]# source sync i/o au3 fsb1dstbn[0]# source sync i/o at3 fsb1d[7]# source sync i/o au4 fsb1dstbp[0]# source sync i/o at4 vss power/other au5 fsb1d[15]# source sync i/o at5 fsb1d[8]# source sync i/o au6 vss power/other at6 fsb1d[11]# source sync i/o au7 fsb1d[13]# source sync i/o au8 fsb1d[33]# source sync i/o av11 vss power/other au9 vss power/other av12 fsb1d[40]# source sync i/o au10 fsb1d[38]# source sync i/o av13 fsbslwctrl power/other au11 fsb1dbi[2]# source sync i/o av14 vss power/other au12 vss power/other av15 vss power/other au13 vss power/other av16 vss power/other au14 vss power/other av17 vss power/other au15 vss power/other av18 vtt power/other au16 corevssa power/other av19 vtt power/other au17 fsbvcca power/other av20 vtt power/other au18 vtt power/other av21 vtt power/other au19 vtt power/other av22 fsb0a[35]# source sync i/o au20 vtt power/other av23 vss power/other au21 vtt power/other av24 fsb0a[31]# source sync i/o au22 fsb0a[34]# source sync i/o av25 fsb0a[28]# source sync i/o au23 fsb0a[29]# source sync i/o av26 vss power/other au24 vss power/other av27 rsvd no connect au25 fsb0a[22]# source sync i/o av28 fsb0a[17]# source sync i/o table 8-1. intel 5000x chipset mch signals (by ball number) (sheet 18 of 19) ball no. signal name buffer type direction ball no. signal name buffer type direction
intel ? 5000x chipset memory controller hub (mch) datasheet 435 ballout and package information au26 fsb0a[25]# source sync i/o av29 vss power/other au27 vss power/other av30 fsb0bnr# common clk i/o au28 fsb0a[21]# source sync i/o av31 fsb0rs[0]# common clk i au29 fsb0ads# common clk i/o av32 vss power/other au30 vss power/other av33 fsb0hitm# common clk i/o au31 fsb0rs[2]# common clk i av34 fsb0defer# common clk o au32 fsb0hit# common clk i/m105o av35 vss power/other au33 vss power/other av36 vss power/other au34 fsb0bpri# common clk o au35 fsbslwcres analog au36 fsb0d[21]# source sync i/o au37 vss power/other av3 vss power/other av4 fsb1d[10]# source sync i/o av5 vss power/other av6 fsb1d[9]# source sync i/o av7 fsb1d[32]# source sync i/o av8 vss power/other av9 fsb1d[37]# source sync i/o av10 fsb1d[39]# source sync i/o table 8-1. intel 5000x chipset mch signals (by ball number) (sheet 19 of 19) ball no. signal name buffer type direction b all no. signal name buffer type direction
ballout and package information 436 intel ? 5000x chipset memory controller hub (mch) datasheet table 8-2. intel 5000x chipset mch signals (by signal name) (sheet 1 of 19) ball no. signal name buffer type direction ball no. signal name buffer type direction k14 cfgsmbclk smb i/o v32 fbd0nbip[7] fbd i j14 cfgsmbdata smb i/o u33 fbd0nbip[8] fbd i ap17 coreclkn analog i w34 fbd0nbip[9] fbd i an17 coreclkp analog i w31 fbd0sbon[0] fbd o at17 corevcca power/other w38 fbd0sbon[1] fbd o au16 corevssa power/other aa33 fbd0sbon[2] fbd o e6 err[0]# cmos o y33 fbd0sbon[3] fbd o a5 err[1]# cmos o y37 fbd0sbon[4] fbd o d2 err[2]# cmos o ab38 fbd0sbon[5] fbd o t38 fbd01clkn analog i ac37 fbd0sbon[6] fbd o r38 fbd01clkp analog i ab34 fbd0sbon[7] fbd o t35 fbd01vcca power/other ac33 fbd0sbon[8] fbd o t34 fbd01vssa power/other aa35 fbd0sbon[9] fbd o y28 fbd0nbin[0] fbd i w32 fbd0sbop[0] fbd o y31 fbd0nbin[1] fbd i v38 fbd0sbop[1] fbd o v36 fbd0nbin[10] fbd i aa32 fbd0sbop[2] fbd o u37 fbd0nbin[11] fbd i y34 fbd0sbop[3] fbd o u31 fbd0nbin[12] fbd i y36 fbd0sbop[4] fbd o v30 fbd0nbin[13] fbd i aa38 fbd0sbop[5] fbd o ab32 fbd0nbin[2] fbd i ab37 fbd0sbop[6] fbd o u27 fbd0nbin[3] fbd i ab35 fbd0sbop[7] fbd o t28 fbd0nbin[4] fbd i ac34 fbd0sbop[8] fbd o w29 fbd0nbin[5] fbd i aa36 fbd0sbop[9] fbd o t32 fbd0nbin[6] fbd i p28 fbd1nbin[0] fbd i v33 fbd0nbin[7] fbd i m27 fbd1nbin[1] fbd i u34 fbd0nbin[8] fbd i h37 fbd1nbin[10] fbd i w35 fbd0nbin[9] fbd i h38 fbd1nbin[11] fbd i y27 fbd0nbip[0] fbd i n32 fbd1nbin[12] fbd i y30 fbd0nbip[1] fbd i k32 fbd1nbin[13] fbd i v35 fbd0nbip[10] fbd i l28 fbd1nbin[2] fbd i u36 fbd0nbip[11] fbd i n29 fbd1nbin[3] fbd i u30 fbd0nbip[12] fbd i m30 fbd1nbin[4] fbd i v29 fbd0nbip[13] fbd i l31 fbd1nbin[5] fbd i ab31 fbd0nbip[2] fbd i m33 fbd1nbin[6] fbd i v27 fbd0nbip[3] fbd i l34 fbd1nbin[7] fbd i u28 fbd0nbip[4] fbd i k35 fbd1nbin[8] fbd i w28 fbd0nbip[5] fbd i f37 fbd1nbin[9] fbd i t31 fbd0nbip[6] fbd i p27 fbd1nbip[0] fbd i m26 fbd1nbip[1] fbd i a26 fbd2nbin[1] fbd i
intel ? 5000x chipset memory controller hub (mch) datasheet 437 ballout and package information h36 fbd1nbip[10] fbd i d37 fbd2nbin[10] fbd i g38 fbd1nbip[11] fbd i e38 fbd2nbin[11] fbd i m32 fbd1nbip[12] fbd i a32 fbd2nbin[12] fbd i k31 fbd1nbip[13] fbd i b31 fbd2nbin[13] fbd i l27 fbd1nbip[2] fbd i a27 fbd2nbin[2] fbd i n28 fbd1nbip[3] fbd i b28 fbd2nbin[3] fbd i m29 fbd1nbip[4] fbd i a29 fbd2nbin[4] fbd i l30 fbd1nbip[5] fbd i a30 fbd2nbin[5] fbd i l33 fbd1nbip[6] fbd i a33 fbd2nbin[6] fbd i k34 fbd1nbip[7] fbd i b34 fbd2nbin[7] fbd i j35 fbd1nbip[8] fbd i a35 fbd2nbin[8] fbd i f36 fbd1nbip[9] fbd i b36 fbd2nbin[9] fbd i j37 fbd1sbon[0] fbd o c25 fbd2nbip[0] fbd i l37 fbd1sbon[1] fbd o b26 fbd2nbip[1] fbd i l38 fbd1sbon[2] fbd o c37 fbd2nbip[10] fbd i m36 fbd1sbon[3] fbd o d38 fbd2nbip[11] fbd i n35 fbd1sbon[4] fbd o b32 fbd2nbip[12] fbd i p36 fbd1sbon[5] fbd o c31 fbd2nbip[13] fbd i r35 fbd1sbon[6] fbd o b27 fbd2nbip[2] fbd i p33 fbd1sbon[7] fbd o c28 fbd2nbip[3] fbd i r32 fbd1sbon[8] fbd o b29 fbd2nbip[4] fbd i n37 fbd1sbon[9] fbd o b30 fbd2nbip[5] fbd i j36 fbd1sbop[0] fbd o b33 fbd2nbip[6] fbd i l36 fbd1sbop[1] fbd o c34 fbd2nbip[7] fbd i k38 fbd1sbop[2] fbd o b35 fbd2nbip[8] fbd i m35 fbd1sbop[3] fbd o c36 fbd2nbip[9] fbd i n34 fbd1sbop[4] fbd o g29 fbd2sbon[0] fbd o p37 fbd1sbop[5] fbd o f30 fbd2sbon[1] fbd o r36 fbd1sbop[6] fbd o e31 fbd2sbon[2] fbd o p34 fbd1sbop[7] fbd o d32 fbd2sbon[3] fbd o r33 fbd1sbop[8] fbd o f33 fbd2sbon[4] fbd o n38 fbd1sbop[9] fbd o d35 fbd2sbon[5] fbd o e28 fbd23clkn analog i g35 fbd2sbon[6] fbd o d28 fbd23clkp analog h34 fbd2sbon[7] fbd o e27 fbd23vcca power/other j33 fbd2sbon[8] fbd o f27 fbd23vssa power/other e34 fbd2sbon[9] fbd o b25 fbd2nbin[0] fbd i g28 fbd2sbop[0] fbd o f29 fbd2sbop[1] fbd o g25 fbd3sbon[1] fbd o e30 fbd2sbop[2] fbd o h24 fbd3sbon[2] fbd o table 8-2. intel 5000x chipset mch signals (by signal name) (sheet 2 of 19) ball no. signal name buffer type direction b all no. signal name buffer type direction
ballout and package information 438 intel ? 5000x chipset memory controller hub (mch) datasheet d31 fbd2sbop[3] fbd o j23 fbd3sbon[3] fbd o f32 fbd2sbop[4] fbd o g22 fbd3sbon[4] fbd o d34 fbd2sbop[5] fbd o j20 fbd3sbon[5] fbd o g34 fbd2sbop[6] fbd o h19 fbd3sbon[6] fbd o h33 fbd2sbop[7] fbd o j18 fbd3sbon[7] fbd o j32 fbd2sbop[8] fbd o k18 fbd3sbon[8] fbd o e33 fbd2sbop[9] fbd o h21 fbd3sbon[9] fbd o f20 fbd3nbin[0] fbd i d22 fbd3sbop[0] fbd o e18 fbd3nbin[1] fbd i g26 fbd3sbop[1] fbd o e25 fbd3nbin[10] fbd i h25 fbd3sbop[2] fbd o d26 fbd3nbin[11] fbd i j24 fbd3sbop[3] fbd o b21 fbd3nbin[12] fbd i g23 fbd3sbop[4] fbd o c20 fbd3nbin[13] fbd i j21 fbd3sbop[5] fbd o d17 fbd3nbin[2] fbd i g19 fbd3sbop[6] fbd o c18 fbd3nbin[3] fbd i h18 fbd3sbop[7] fbd o b19 fbd3nbin[4] fbd i k19 fbd3sbop[8] fbd o e19 fbd3nbin[5] fbd i h22 fbd3sbop[9] fbd o a22 fbd3nbin[6] fbd i e37 fbdbgbiasext analog c23 fbd3nbin[7] fbd i f35 fbdicompbias analog b24 fbd3nbin[8] fbd i e36 fbdresin analog f24 fbd3nbin[9] fbd i ag24 fsb0a[10]# source sync i/o g20 fbd3nbip[0] fbd i aj22 fsb0a[11]# source sync i/o f18 fbd3nbip[1] fbd i al22 fsb0a[12]# source sync i/o e24 fbd3nbip[10] fbd i ah22 fsb0a[13]# source sync i/o d25 fbd3nbip[11] fbd i af25 fsb0a[14]# source sync i/o c21 fbd3nbip[12] fbd i ag23 fsb0a[15]# source sync i/o d20 fbd3nbip[13] fbd i af22 fsb0a[16]# source sync i/o c17 fbd3nbip[2] fbd i av28 fsb0a[17]# source sync i/o b18 fbd3nbip[3] fbd i ap25 fsb0a[18]# source sync i/o a19 fbd3nbip[4] fbd i ar27 fsb0a[19]# source sync i/o d19 fbd3nbip[5] fbd i ar24 fsb0a[20]# source sync i/o b22 fbd3nbip[6] fbd i au28 fsb0a[21]# source sync i/o d23 fbd3nbip[7] fbd i au25 fsb0a[22]# source sync i/o a24 fbd3nbip[8] fbd i at27 fsb0a[23]# source sync i/o f23 fbd3nbip[9] fbd i at26 fsb0a[24]# source sync i/o e22 fbd3sbon[0] fbd o au26 fsb0a[25]# source sync i/o ar25 fsb0a[26]# source sync i/o al34 fsb0d[17]# source sync i/o at24 fsb0a[27]# source sync i/o ap35 fsb0d[18]# source sync i/o av25 fsb0a[28]# source sync i/o at36 fsb0d[19]# source sync i/o table 8-2. intel 5000x chipset mch signals (by signal name) (sheet 3 of 19) ball no. signal name buffer type direction ball no. signal name buffer type direction
intel ? 5000x chipset memory controller hub (mch) datasheet 439 ballout and package information au23 fsb0a[29]# source sync i/o ah28 fsb0d[2]# source sync i/o al25 fsb0a[3]# source sync i/o ap34 fsb0d[20]# source sync i/o at23 fsb0a[30]# source sync i/o au36 fsb0d[21]# source sync i/o av24 fsb0a[31]# source sync i/o at37 fsb0d[22]# source sync i/o ap22 fsb0a[32]# source sync i/o ap36 fsb0d[23]# source sync i/o ar22 fsb0a[33]# source sync i/o an35 fsb0d[24]# source sync i/o au22 fsb0a[34]# source sync i/o al35 fsb0d[25]# source sync i/o av22 fsb0a[35]# source sync i/o an36 fsb0d[26]# source sync i/o an24 fsb0a[4]# source sync i/o ap38 fsb0d[27]# source sync i/o am25 fsb0a[5]# source sync i/o am38 fsb0d[28]# source sync i/o an26 fsb0a[6]# source sync i/o am34 fsb0d[29]# source sync i/o ap26 fsb0a[7]# source sync i/o ak29 fsb0d[3]# source sync i/o ah23 fsb0a[8]# source sync i/o ak35 fsb0d[30]# source sync i/o am22 fsb0a[9]# source sync i/o am37 fsb0d[31]# source sync i/o au29 fsb0ads# common clk i/o ag33 fsb0d[32]# source sync i/o al23 fsb0adstb[0]# source sync i/o ag30 fsb0d[33]# source sync i/o ap23 fsb0adstb[1]# source sync i/o ae34 fsb0d[34]# source sync i/o ah26 fsb0ap[0]# common clk i/o af31 fsb0d[35]# source sync i/o ak26 fsb0ap[1]# source sync i/o ag32 fsb0d[36]# source sync i/o ak27 fsb0binit# common clk i/o af33 fsb0d[37]# source sync i/o av30 fsb0bnr# common clk i/o ad35 fsb0d[38]# source sync i/o ar28 fsb0bpm[4]# common clk i/o ae32 fsb0d[39]# source sync i/o ap29 fsb0bpm[5]# common clk i/o ah29 fsb0d[4]# source sync i/o au34 fsb0bpri# common clk o ae31 fsb0d[40]# source sync i/o am28 fsb0breq[0]# common clk i/o ad30 fsb0d[41]# source sync i/o ag26 fsb0breq[1]# common clk i/o ac30 fsb0d[42]# source sync i/o aj28 fsb0d[0]# source sync i/o ae29 fsb0d[43]# source sync i/o al29 fsb0d[1]# source sync i/o ac31 fsb0d[44]# source sync i/o aj30 fsb0d[10]# source sync i/o af28 fsb0d[45]# source sync i/o ah31 fsb0d[11]# source sync i/o ad29 fsb0d[46]# source sync i/o am33 fsb0d[12]# source sync i/o ae28 fsb0d[47]# source sync i/o ag29 fsb0d[13]# source sync i/o af37 fsb0d[48]# source sync i/o ag27 fsb0d[14]# source sync i/o aj34 fsb0d[49]# source sync i/o aj33 fsb0d[15]# source sync i/o an32 fsb0d[5]# source sync i/o an33 fsb0d[16]# source sync i/o al38 fsb0d[50]# source sync i/o al36 fsb0d[51]# source sync i/o at30 fsb0lock# common clk i/o al37 fsb0d[52]# source sync i/o aj27 fsb0mcerr# common clk i/o ak36 fsb0d[53]# source sync i/o al26 fsb0req[0]# source sync i/o ag35 fsb0d[54]# source sync i/o ah25 fsb0req[1]# source sync i/o table 8-2. intel 5000x chipset mch signals (by signal name) (sheet 4 of 19) ball no. signal name buffer type direction b all no. signal name buffer type direction
ballout and package information 440 intel ? 5000x chipset memory controller hub (mch) datasheet aj37 fsb0d[55]# source sync i/o ak24 fsb0req[2]# source sync i/o aj38 fsb0d[56]# source sync i/o aj24 fsb0req[3]# source sync i/o ah38 fsb0d[57]# source sync i/o aj25 fsb0req[4]# source sync i/o ae38 fsb0d[58]# source sync i/o an30 fsb0reset# common clk i af38 fsb0d[59]# source sync i/o av31 fsb0rs[0]# common clk i ak30 fsb0d[6]# source sync i/o al28 fsb0rs[1]# common clk i ag36 fsb0d[60]# source sync i/o au31 fsb0rs[2]# common clk i ah36 fsb0d[61]# source sync i/o an27 fsb0rsp# common clk i ae36 fsb0d[62]# source sync i/o at32 fsb0trdy# common clk o ae37 fsb0d[63]# source sync i/o af34 fsb0vref power/other al31 fsb0d[7]# source sync i/o am27 fsb0vref power/other aj31 fsb0d[8]# source sync i/o am30 fsb0vref power/other ah32 fsb0d[9]# source sync i/o ab11 fsb1a[10]# source sync i/o al32 fsb0dbi[0]# source sync i/o af6 fsb1a[11]# source sync i/o ap37 fsb0dbi[1]# source sync i/o ad8 fsb1a[12]# source sync i/o af30 fsb0dbi[2]# source sync i/o ac9 fsb1a[13]# source sync i/o ah37 fsb0dbi[3]# source sync i/o ab10 fsb1a[14]# source sync i/o ar30 fsb0dbsy# common clk i/o ac7 fsb1a[15]# source sync i/o av34 fsb0defer# common clk o aa12 fsb1a[16]# source sync i/o ar31 fsb0dp[0]# common clk i/o af4 fsb1a[17]# source sync i/o at33 fsb0dp[1]# common clk i/o ag5 fsb1a[18]# source sync i/o ap31 fsb0dp[2]# common clk i/o ah5 fsb1a[19]# source sync i/o an29 fsb0dp[3]# common clk i/o ad6 fsb1a[20]# source sync i/o at29 fsb0drdy# common clk i/o ae5 fsb1a[21]# source sync i/o ak32 fsb0dstbn[0]# source sync i/o ac6 fsb1a[22]# source sync i/o ar37 fsb0dstbn[1]# source sync i/o ad5 fsb1a[23]# source sync i/o ad32 fsb0dstbn[2]# source sync i/o ah2 fsb1a[24]# source sync i/o ah34 fsb0dstbn[3]# source sync i/o ah1 fsb1a[25]# source sync i/o ak33 fsb0dstbp[0]# source sync i/o aj3 fsb1a[26]# source sync i/o ar38 fsb0dstbp[1]# source sync i/o af1 fsb1a[27]# source sync i/o ad33 fsb0dstbp[2]# source sync i/o af3 fsb1a[28]# source sync i/o ah35 fsb0dstbp[3]# source sync i/o ad3 fsb1a[29]# source sync i/o au32 fsb0hit# common clk i/m105o ad12 fsb1a[3]# source sync i/o av33 fsb0hitm# common clk i/o ae4 fsb1a[30]# source sync i/o ae2 fsb1a[31]# source sync i/o ap8 fsb1d[22]# source sync i/o ae1 fsb1a[32]# source sync i/o an8 fsb1d[23]# source sync i/o ad2 fsb1a[33]# source sync i/o an9 fsb1d[24]# source sync i/o ac4 fsb1a[34]# source sync i/o an12 fsb1d[25]# source sync i/o ac3 fsb1a[35]# source sync i/o am12 fsb1d[26]# source sync i/o table 8-2. intel 5000x chipset mch signals (by signal name) (sheet 5 of 19) ball no. signal name buffer type direction ball no. signal name buffer type direction
intel ? 5000x chipset memory controller hub (mch) datasheet 441 ballout and package information ad9 fsb1a[4]# source sync i/o an11 fsb1d[27]# source sync i/o ac12 fsb1a[5]# source sync i/o am13 fsb1d[28]# source sync i/o ah8 fsb1a[6]# source sync i/o al11 fsb1d[29]# source sync i/o ag8 fsb1a[7]# source sync i/o ar1 fsb1d[3]# source sync i/o af7 fsb1a[8]# source sync i/o al13 fsb1d[30]# source sync i/o ae7 fsb1a[9]# source sync i/o ak12 fsb1d[31]# source sync i/o ap2 fsb1ads# common clk i/o av7 fsb1d[32]# source sync i/o ac10 fsb1adstb[0]# source sync i/o au8 fsb1d[33]# source sync i/o ag3 fsb1adstb[1]# source sync i/o at9 fsb1d[34]# source sync i/o ag12 fsb1ap[0]# common clk i/o ar9 fsb1d[35]# source sync i/o ag10 fsb1ap[1]# common clk i/o at8 fsb1d[36]# source sync i/o aj4 fsb1binit# common clk i/o av9 fsb1d[37]# source sync i/o ak3 fsb1bnr# common clk i/o au10 fsb1d[38]# source sync i/o an2 fsb1bpm[4]# common clk i/o av10 fsb1d[39]# source sync i/o an3 fsb1bpm[5]# common clk i/o ar3 fsb1d[4]# source sync i/o aj10 fsb1bpri# common clk o av12 fsb1d[40]# source sync i/o al2 fsb1breq[0]# common clk i/o at11 fsb1d[41]# source sync i/o am1 fsb1breq[1]# common clk i/o at12 fsb1d[42]# source sync i/o ap1 fsb1d[0]# source sync i/o ap13 fsb1d[43]# source sync i/o ap5 fsb1d[1]# source sync i/o ap11 fsb1d[44]# source sync i/o av4 fsb1d[10]# source sync i/o ar13 fsb1d[45]# source sync i/o at6 fsb1d[11]# source sync i/o ar12 fsb1d[46]# source sync i/o ar6 fsb1d[12]# source sync i/o ap14 fsb1d[47]# source sync i/o au7 fsb1d[13]# source sync i/o ah14 fsb1d[48]# source sync i/o ar7 fsb1d[14]# source sync i/o am16 fsb1d[49]# source sync i/o au5 fsb1d[15]# source sync i/o ar4 fsb1d[5]# source sync i/o al7 fsb1d[16]# source sync i/o an14 fsb1d[50]# source sync i/o al8 fsb1d[17]# source sync i/o am15 fsb1d[51]# source sync i/o an6 fsb1d[18]# source sync i/o al14 fsb1d[52]# source sync i/o ak9 fsb1d[19]# source sync i/o an15 fsb1d[53]# source sync i/o ap4 fsb1d[2]# source sync i/o ah16 fsb1d[54]# source sync i/o am6 fsb1d[20]# source sync i/o ap16 fsb1d[55]# source sync i/o am9 fsb1d[21]# source sync i/o al16 fsb1d[56]# source sync i/o aj13 fsb1d[57]# source sync i/o ae10 fsb1req[4]# source sync i/o af15 fsb1d[58]# source sync i/o ae11 fsb1reset# common clk i ag15 fsb1d[59]# source sync i/o ak5 fsb1rs[0]# common clk i at2 fsb1d[6]# source sync i/o al1 fsb1rs[1]# common clk i aj15 fsb1d[60]# source sync i/o al5 fsb1rs[2]# common clk i aj16 fsb1d[61]# source sync i/o ak2 fsb1rsp# common clk i table 8-2. intel 5000x chipset mch signals (by signal name) (sheet 6 of 19) ball no. signal name buffer type direction b all no. signal name buffer type direction
ballout and package information 442 intel ? 5000x chipset memory controller hub (mch) datasheet ag14 fsb1d[62]# source sync i/o ak6 fsb1trdy# common clk o af16 fsb1d[63]# source sync i/o ah4 fsb1vref power/other at3 fsb1d[7]# source sync i/o an5 fsb1vref power/other at5 fsb1d[8]# source sync i/o at14 fsb1vref power/other av6 fsb1d[9]# source sync i/o at35 fsbcres analog ap7 fsb1dbi[0]# source sync i/o ar34 fsbodtcres analog ak11 fsb1dbi[1]# source sync i/o au35 fsbslwcres analog au11 fsb1dbi[2]# source sync i/o av13 fsbslwctrl power/other ah13 fsb1dbi[3]# source sync i/o au17 fsbvcca power/other am4 fsb1dbsy# common clk i/o k13 gpiosmbclk smb i/o aj9 fsb1defer# common clk o l12 gpiosmbdata smb i/o ag11 fsb1dp[0]# common clk i/o y9 pe0rn[0] pex i aj12 fsb1dp[1]# common clk i/o y3 pe0rn[1] pex i af12 fsb1dp[2]# common clk i/o ab7 pe0rn[2] pex i af13 fsb1dp[3]# common clk i/o aa6 pe0rn[3] pex i am3 fsb1drdy# common clk i/o y10 pe0rp[0] pex i au3 fsb1dstbn[0]# source sync i/o y4 pe0rp[1] pex i al10 fsb1dstbn[1]# source sync i/o ab8 pe0rp[2] pex i ap10 fsb1dstbn[2]# source sync i/o aa5 pe0rp[3] pex i ak14 fsb1dstbn[3]# source sync i/o y6 pe0tn[0] pex o au4 fsb1dstbp[0]# source sync i/o aa2 pe0tn[1] pex o am10 fsb1dstbp[1]# source sync i/o ab5 pe0tn[2] pex o ar10 fsb1dstbp[2]# source sync i/o aa9 pe0tn[3] pex o ak15 fsb1dstbp[3]# source sync i/o y7 pe0tp[0] pex o ak8 fsb1hit# common clk i/o aa3 pe0tp[1] pex o aj7 fsb1hitm# common clk i/o ab4 pe0tp[2] pex o al4 fsb1lock# common clk i/o aa8 pe0tp[3] pex o ah11 fsb1mcerr# common clk i/o r5 pe2rn[0] pex i ag9 fsb1req[0]# source sync i/o p4 pe2rn[1] pex i ad11 fsb1req[1]# source sync i/o r3 pe2rn[2] pex i aj6 fsb1req[2]# source sync i/o u1 pe2rn[3] pex i af9 fsb1req[3]# source sync i/o t5 pe2rp[0] pex i n4 pe2rp[1] pex i k11 pe4tn[3] pex o p3 pe2rp[2] pex i h12 pe4tp[0] pex o t1 pe2rp[3] pex i c12 pe4tp[1] pex o t7 pe2tn[0] pex o c11 pe4tp[2] pex o t4 pe2tn[1] pex o j11 pe4tp[3] pex o p1 pe2tn[2] pex o g10 pe5rn[0] pex i t2 pe2tn[3] pex o b9 pe5rn[1] pex i table 8-2. intel 5000x chipset mch signals (by signal name) (sheet 7 of 19) ball no. signal name buffer type direction ball no. signal name buffer type direction
intel ? 5000x chipset memory controller hub (mch) datasheet 443 ballout and package information t8 pe2tp[0] pex o g8 pe5rn[2] pex i u4 pe2tp[1] pex o h7 pe5rn[3] pex i n1 pe2tp[2] pex o h10 pe5rp[0] pex i r2 pe2tp[3] pex o c9 pe5rp[1] pex i w2 pe3rn[0] pex i f8 pe5rp[2] pex i v6 pe3rn[1] pex i g7 pe5rp[3] pex i w8 pe3rn[2] pex i h9 pe5tn[0] pex o u10 pe3rn[3] pex i e9 pe5tn[1] pex o v2 pe3rp[0] pex i c8 pe5tn[2] pex o v5 pe3rp[1] pex i e7 pe5tn[3] pex o w7 pe3rp[2] pex i j9 pe5tp[0] pex o u9 pe3rp[3] pex i f9 pe5tp[1] pex o v3 pe3tn[0] pex o d8 pe5tp[2] pex o w4 pe3tn[1] pex o d7 pe5tp[3] pex o u7 pe3tn[2] pex o c5 pe6rn[0] pex i v9 pe3tn[3] pex o e3 pe6rn[1] pex i u3 pe3tp[0] pex o f5 pe6rn[2] pex i w5 pe3tp[1] pex o k8 pe6rn[3] pex i u6 pe3tp[2] pex o c6 pe6rp[0] pex i v8 pe3tp[3] pex o e4 pe6rp[1] pex i e12 pe4rn[0] pex i f6 pe6rp[2] pex i f11 pe4rn[1] pex i j8 pe6rp[3] pex i e10 pe4rn[2] pex i m8 pe6tn[0] pex o l10 pe4rn[3] pex i d4 pe6tn[1] pex o f12 pe4rp[0] pex i c2 pe6tn[2] pex o g11 pe4rp[1] pex i j6 pe6tn[3] pex o d10 pe4rp[2] pex i m9 pe6tp[0] pex o k10 pe4rp[3] pex i d5 pe6tp[1] pex o j12 pe4tn[0] pex o c3 pe6tp[2] pex o b12 pe4tn[1] pex o h6 pe6tp[3] pex o d11 pe4tn[2] pex o f2 pe7rn[0] pex i e1 pe7rn[1] pex i m2 rsvd no connect h4 pe7rn[2] pex i m3 rsvd no connect l4 pe7rn[3] pex i m5 rsvd no connect f3 pe7rp[0] pex i m6 rsvd no connect d1 pe7rp[1] pex i m12 rsvd no connect h3 pe7rp[2] pex i n2 rsvd no connect k4 pe7rp[3] pex i n5 rsvd no connect g4 pe7tn[0] pex o n7 rsvd no connect table 8-2. intel 5000x chipset mch signals (by signal name) (sheet 8 of 19) ball no. signal name buffer type direction b all no. signal name buffer type direction
ballout and package information 444 intel ? 5000x chipset memory controller hub (mch) datasheet g1 pe7tn[1] pex o n8 rsvd no connect l7 pe7tn[2] pex o n10 rsvd no connect k5 pe7tn[3] pex o p6 rsvd no connect g5 pe7tp[0] pex o p7 rsvd no connect g2 pe7tp[1] pex o p9 rsvd no connect k7 pe7tp[2] pex o p10 rsvd no connect j5 pe7tp[3] pex o r6 rsvd no connect k2 peclkn analog r8 rsvd no connect j2 peclkp analog r9 rsvd no connect r12 peicompi analog t37 rsvd no connect p12 percompo analog w1 rsvd no connect k1 pevcca analog y1 rsvd no connect r11 pevccbg analog ae8 rsvd no connect l1 pevssa analog ag2 rsvd no connect n11 pevssbg analog ag6 rsvd no connect aa11 pewidth[0] power/other i ah7 rsvd no connect y12 pewidth[1] power/other i aj1 rsvd no connect w11 pewidth[2] power/other i ak17 rsvd no connect w10 pewidth[3] power/other i ak23 rsvd no connect ac1 psel[0] cmos i am7 rsvd no connect ab2 psel[1] cmos i am24 rsvd no connect ab1 psel[2] cmos i am31 rsvd no connect h17 pwrgood cmos i an23 rsvd no connect g17 reseti# cmos i ap28 rsvd no connect m11 rsv1 no connect ap32 rsvd no connect d29 rsvd no connect ar15 rsvd no connect h1 rsvd no connect ar16 rsvd no connect j3 rsvd no connect ar33 rsvd no connect l3 rsvd no connect av27 rsvd no connect l6 rsvd no connect h13 spd0smbclk smb i/o g13 spd0smbdata smb i/o t18 vcc power/other j16 spd1smbclk smb i/o t20 vcc power/other k15 spd1smbdata smb i/o t22 vcc power/other f15 spd2smbclk smb i/o t24 vcc power/other e15 spd2smbdata smb i/o u15 vcc power/other h15 spd3smbclk smb i/o u17 vcc power/other h16 spd3smbdata smb i/o u19 vcc power/other a6 tck jtag i u21 vcc power/other b7 tdi jtag i u23 vcc power/other table 8-2. intel 5000x chipset mch signals (by signal name) (sheet 9 of 19) ball no. signal name buffer type direction ball no. signal name buffer type direction
intel ? 5000x chipset memory controller hub (mch) datasheet 445 ballout and package information a4 tdioanode analog v16 vcc power/other b4 tdiocathode analog v18 vcc power/other b6 tdo jtag ouput v20 vcc power/other ac36 testhi no connect v22 vcc power/other f17 testhi_v3ref power/other v24 vcc power/other g16 testhi_v3ref power/other w15 vcc power/other a7 tms jtag i w17 vcc power/other a8 trst# jtag i w19 vcc power/other f13 v3ref analog w21 vcc power/other l16 vcc power/other w23 vcc power/other l17 vcc power/other y16 vcc power/other l18 vcc power/other y18 vcc power/other l19 vcc power/other y20 vcc power/other m16 vcc power/other y22 vcc power/other m17 vcc power/other y24 vcc power/other m18 vcc power/other aa13 vcc power/other n17 vcc power/other aa15 vcc power/other n19 vcc power/other aa17 vcc power/other p16 vcc power/other aa19 vcc power/other p18 vcc power/other aa21 vcc power/other p20 vcc power/other aa23 vcc power/other p22 vcc power/other ab13 vcc power/other p24 vcc power/other ab14 vcc power/other r15 vcc power/other ab16 vcc power/other r17 vcc power/other ab18 vcc power/other r19 vcc power/other ab20 vcc power/other r21 vcc power/other ab22 vcc power/other r23 vcc power/other ab24 vcc power/other t16 vcc power/other ac15 vcc power/other ac17 vcc power/other r25 vccfbd power/other ac19 vcc power/other t25 vccfbd power/other ac21 vcc power/other t26 vccfbd power/other ac23 vcc power/other t27 vccfbd fbd i ac25 vcc power/other u25 vccfbd power/other ac26 vcc power/other u26 vccfbd power/other ad26 vcc power/other v25 vccfbd power/other ae35 vcc power/other v26 vccfbd power/other ah10 vcc power/other w25 vccfbd power/other al17 vcc power/other w26 vccfbd power/other table 8-2. intel 5000x chipset mch signals (by signal name) (sheet 10 of 19) ball no. signal name buffer type direction b all no. signal name buffer type direction
ballout and package information 446 intel ? 5000x chipset memory controller hub (mch) datasheet a20 vccfbd power/other y25 vccfbd power/other e20 vccfbd power/other y26 vccfbd power/other e23 vccfbd power/other aa25 vccfbd power/other f25 vccfbd power/other aa26 vccfbd power/other h20 vccfbd power/other aa27 vccfbd power/other h23 vccfbd power/other ab25 vccfbd power/other k21 vccfbd power/other ab26 vccfbd power/other k22 vccfbd power/other g12 vccpe power/other k23 vccfbd power/other j10 vccpe power/other l20 vccfbd power/other l2 vccpe power/other l21 vccfbd power/other l8 vccpe power/other l22 vccfbd power/other l13 vccpe power/other l23 vccfbd power/other l14 vccpe power/other m20 vccfbd power/other l15 vccpe power/other m21 vccfbd power/other m13 vccpe power/other m22 vccfbd power/other m14 vccpe power/other m23 vccfbd power/other m15 vccpe power/other m24 vccfbd power/other n6 vccpe power/other m25 vccfbd power/other n12 vccpe power/other n20 vccfbd power/other n13 vccpe power/other n21 vccfbd power/other n14 vccpe power/other n22 vccfbd power/other n15 vccpe power/other n23 vccfbd power/other p13 vccpe power/other n24 vccfbd power/other p14 vccpe power/other n25 vccfbd power/other r4 vccpe power/other n26 vccfbd power/other r10 vccpe power/other p25 vccfbd power/other r13 vccpe power/other p26 vccfbd power/other r14 vccpe power/other t13 vccpe power/other c7 vss power/other t14 vccpe power/other c10 vss power/other u2 vccpe power/other c15 vss power/other u8 vccpe power/other c19 vss power/other u13 vccpe power/other c22 vss power/other u14 vccpe power/other c24 vss power/other v13 vccpe power/other c26 vss power/other v14 vccpe power/other c27 vss power/other w6 vccpe power/other c29 vss power/other w12 vccpe power/other c30 vss power/other w13 vccpe power/other c32 vss power/other table 8-2. intel 5000x chipset mch signals (by signal name) (sheet 11 of 19) ball no. signal name buffer type direction ball no. signal name buffer type direction
intel ? 5000x chipset memory controller hub (mch) datasheet 447 ballout and package information w14 vccpe power/other c33 vss power/other y13 vccpe power/other c35 vss power/other y14 vccpe power/other c38 vss power/other l24 vccsen temp d3 vss power/other a3 vss power/other d6 vss power/other a9 vss power/other d9 vss power/other a13 vss power/other d12 vss power/other a18 vss power/other d14 vss power/other a21 vss power/other d18 vss power/other a23 vss power/other d21 vss power/other a25 vss power/other d24 vss power/other a28 vss power/other d27 vss power/other a31 vss power/other d30 vss power/other a34 vss power/other d33 vss power/other a36 vss power/other d36 vss power/other b2 vss power/other e2 vss power/other b3 vss power/other e5 vss power/other b5 vss power/other e8 vss power/other b8 vss power/other e11 vss power/other b11 vss power/other e13 vss power/other b16 vss power/other e17 vss power/other b17 vss power/other e21 vss power/other b20 vss power/other e26 vss power/other b23 vss power/other e29 vss power/other b37 vss power/other e32 vss power/other c1 vss power/other e35 vss power/other c4 vss power/other f1 vss power/other f4 vss power/other h35 vss power/other f7 vss power/other j1 vss power/other f10 vss power/other j4 vss power/other f16 vss power/other j7 vss power/other f19 vss power/other j13 vss power/other f21 vss power/other j17 vss power/other f22 vss power/other j19 vss power/other f26 vss power/other j22 vss power/other f28 vss power/other j25 vss power/other f31 vss power/other j26 vss power/other f34 vss power/other j27 vss power/other f38 vss power/other j28 vss power/other table 8-2. intel 5000x chipset mch signals (by signal name) (sheet 12 of 19) ball no. signal name buffer type direction b all no. signal name buffer type direction
ballout and package information 448 intel ? 5000x chipset memory controller hub (mch) datasheet g3 vss power/other j29 vss power/other g6 vss power/other j30 vss power/other g9 vss power/other j31 vss power/other g15 vss power/other j34 vss power/other g18 vss power/other j38 vss power/other g21 vss power/other k3 vss power/other g24 vss power/other k6 vss power/other g27 vss power/other k9 vss power/other g30 vss power/other k12 vss power/other g31 vss power/other k16 vss power/other g32 vss power/other k17 vss power/other g33 vss power/other k20 vss power/other g36 vss power/other k24 vss power/other g37 vss power/other k25 vss power/other h2 vss power/other k26 vss power/other h5 vss power/other k27 vss power/other h8 vss power/other k28 vss power/other h11 vss power/other k29 vss power/other h14 vss power/other k30 vss power/other h26 vss power/other k33 vss power/other h27 vss power/other k36 vss power/other h28 vss power/other k37 vss power/other h29 vss power/other l5 vss power/other h30 vss power/other l11 vss power/other h31 vss power/other l26 vss power/other h32 vss power/other l29 vss power/other l32 vss power/other r16 vss power/other l35 vss power/other r18 vss power/other m1 vss power/other r20 vss power/other m4 vss power/other r22 vss power/other m7 vss power/other r24 vss power/other m10 vss power/other r26 vss power/other m19 vss power/other r27 vss power/other m28 vss power/other r28 vss power/other m31 vss power/other r29 vss power/other m34 vss power/other r30 vss power/other m37 vss power/other r31 vss power/other m38 vss power/other r34 vss power/other n3 vss power/other r37 vss power/other table 8-2. intel 5000x chipset mch signals (by signal name) (sheet 13 of 19) ball no. signal name buffer type direction ball no. signal name buffer type direction
intel ? 5000x chipset memory controller hub (mch) datasheet 449 ballout and package information n9 vss power/other t3 vss power/other n16 vss power/other t6 vss power/other n18 vss power/other t9 vss power/other n27 vss power/other t10 vss power/other n30 vss power/other t11 vss power/other n31 vss power/other t12 vss power/other n33 vss power/other t15 vss power/other n36 vss power/other t17 vss power/other p2 vss power/other t19 vss power/other p5 vss power/other t21 vss power/other p8 vss power/other t23 vss power/other p11 vss power/other t29 vss power/other p15 vss power/other t30 vss power/other p17 vss power/other t33 vss power/other p19 vss power/other t36 vss power/other p21 vss power/other u5 vss power/other p23 vss power/other u11 vss power/other p29 vss power/other u12 vss power/other p30 vss power/other u16 vss power/other p31 vss power/other u18 vss power/other p32 vss power/other u20 vss power/other p35 vss power/other u22 vss power/other p38 vss power/other u24 vss power/other r1 vss power/other u29 vss power/other r7 vss power/other u32 vss power/other u35 vss power/other y29 vss power/other u38 vss power/other y32 vss power/other v1 vss power/other y35 vss power/other v4 vss power/other y38 vss power/other v7 vss power/other aa1 vss power/other v10 vss power/other aa4 vss power/other v11 vss power/other aa7 vss power/other v12 vss power/other aa10 vss power/other v15 vss power/other aa14 vss power/other v17 vss power/other aa16 vss power/other v19 vss power/other aa18 vss power/other v21 vss power/other aa20 vss power/other v23 vss power/other aa22 vss power/other v28 vss power/other aa24 vss power/other table 8-2. intel 5000x chipset mch signals (by signal name) (sheet 14 of 19) ball no. signal name buffer type direction b all no. signal name buffer type direction
ballout and package information 450 intel ? 5000x chipset memory controller hub (mch) datasheet v31 vss power/other aa28 vss power/other v34 vss power/other aa29 vss power/other v37 vss power/other aa30 vss power/other w3 vss power/other aa31 vss power/other w9 vss power/other aa34 vss power/other w16 vss power/other aa37 vss power/other w18 vss power/other ab3 vss power/other w20 vss power/other ab6 vss power/other w22 vss power/other ab9 vss power/other w24 vss power/other ab12 vss power/other w27 vss power/other ab15 vss power/other w30 vss power/other ab17 vss power/other w33 vss power/other ab19 vss power/other w36 vss power/other ab21 vss power/other w37 vss power/other ab23 vss power/other y2 vss power/other ab27 vss power/other y5 vss power/other ab28 vss power/other y8 vss power/other ab29 vss power/other y11 vss power/other ab30 vss power/other y15 vss power/other ab33 vss power/other y17 vss power/other ab36 vss power/other y19 vss power/other ac2 vss power/other y21 vss power/other ac5 vss power/other y23 vss power/other ac8 vss power/other ac11 vss power/other af24 vss power/other ac16 vss power/other af26 vss power/other ac18 vss power/other af27 vss power/other ac20 vss power/other af29 vss power/other ac22 vss power/other af32 vss power/other ac24 vss power/other af35 vss power/other ac27 vss power/other af36 vss power/other ac28 vss power/other ag1 vss power/other ac29 vss power/other ag4 vss power/other ac32 vss power/other ag7 vss power/other ac35 vss power/other ag13 vss power/other ac38 vss power/other ag16 vss power/other ad1 vss power/other ag17 vss power/other ad4 vss power/other ag22 vss power/other ad7 vss power/other ag25 vss power/other table 8-2. intel 5000x chipset mch signals (by signal name) (sheet 15 of 19) ball no. signal name buffer type direction ball no. signal name buffer type direction
intel ? 5000x chipset memory controller hub (mch) datasheet 451 ballout and package information ad10 vss power/other ag28 vss power/other ad27 vss power/other ag31 vss power/other ad28 vss power/other ag34 vss power/other ad31 vss power/other ag37 vss power/other ad34 vss power/other ag38 vss power/other ad36 vss power/other ah3 vss power/other ad37 vss power/other ah6 vss power/other ad38 vss power/other ah9 vss power/other ae3 vss power/other ah12 vss power/other ae6 vss power/other ah15 vss power/other ae9 vss power/other ah17 vss no connect ae12 vss power/other ah24 vss power/other ae27 vss power/other ah27 vss power/other ae30 vss power/other ah30 vss power/other ae33 vss power/other ah33 vss power/other af2 vss power/other aj2 vss power/other af5 vss power/other aj5 vss power/other af8 vss power/other aj8 vss power/other af10 vss power/other aj11 vss power/other af11 vss power/other aj14 vss power/other af14 vss power/other aj17 vss power/other af17 vss power/other aj23 vss power/other af23 vss power/other aj26 vss power/other aj29 vss power/other an1 vss power/other aj32 vss power/other an4 vss power/other aj35 vss power/other an7 vss power/other aj36 vss power/other an10 vss power/other ak1 vss power/other an13 vss power/other ak4 vss power/other an16 vss power/other ak7 vss power/other an22 vss power/other ak10 vss power/other an25 vss power/other ak13 vss power/other an28 vss power/other ak16 vss power/other an31 vss power/other ak22 vss power/other an34 vss power/other ak25 vss power/other an37 vss power/other ak28 vss power/other an38 vss power/other ak31 vss power/other ap3 vss power/other ak34 vss power/other ap6 vss power/other ak37 vss power/other ap9 vss power/other table 8-2. intel 5000x chipset mch signals (by signal name) (sheet 16 of 19) ball no. signal name buffer type direction b all no. signal name buffer type direction
ballout and package information 452 intel ? 5000x chipset memory controller hub (mch) datasheet ak38 vss power/other ap12 vss power/other al3 vss power/other ap15 vss power/other al6 vss power/other ap24 vss power/other al9 vss power/other ap27 vss power/other al12 vss power/other ap30 vss power/other al15 vss power/other ap33 vss power/other al24 vss power/other ar2 vss power/other al27 vss power/other ar5 vss power/other al30 vss power/other ar8 vss power/other al33 vss power/other ar11 vss power/other am2 vss power/other ar14 vss power/other am5 vss power/other ar17 vss power/other am8 vss power/other ar23 vss power/other am11 vss power/other ar26 vss power/other am14 vss power/other ar29 vss power/other am17 vss power/other ar32 vss power/other am23 vss power/other ar35 vss power/other am26 vss power/other ar36 vss power/other am29 vss power/other at1 vss power/other am32 vss power/other at4 vss power/other am35 vss power/other at7 vss power/other am36 vss power/other at10 vss power/other at13 vss power/other ac14 vtt power/other at15 vss power/other ad13 vtt power/other at16 vss power/other ad14 vtt power/other at22 vss power/other ad15 vtt power/other at25 vss power/other ad16 vtt power/other at28 vss power/other ad17 vtt power/other at31 vss power/other ad18 vtt power/other at34 vss power/other ad19 vtt power/other at38 vss power/other ad20 vtt power/other au2 vss power/other ad21 vtt power/other au6 vss power/other ad22 vtt power/other au9 vss power/other ad23 vtt power/other au12 vss power/other ad24 vtt power/other au13 vss power/other ad25 vtt power/other au14 vss power/other ae13 vtt power/other au15 vss power/other ae14 vtt power/other au24 vss power/other ae15 vtt power/other table 8-2. intel 5000x chipset mch signals (by signal name) (sheet 17 of 19) ball no. signal name buffer type direction ball no. signal name buffer type direction
intel ? 5000x chipset memory controller hub (mch) datasheet 453 ballout and package information au27 vss power/other ae16 vtt power/other au30 vss power/other ae17 vtt power/other au33 vss power/other ae18 vtt power/other au37 vss power/other ae19 vtt power/other av3 vss power/other ae20 vtt power/other av5 vss power/other ae21 vtt power/other av8 vss power/other ae22 vtt power/other av11 vss power/other ae23 vtt power/other av14 vss power/other ae24 vtt power/other av15 vss power/other ae25 vtt power/other av16 vss power/other ae26 vtt power/other av17 vss power/other af18 vtt power/other av23 vss power/other af19 vtt power/other av26 vss power/other af20 vtt power/other av29 vss power/other af21 vtt power/other av32 vss power/other ag18 vtt power/other av35 vss power/other ag19 vtt power/other av36 vss power/other ag20 vtt power/other l9 vssquiet analog ag21 vtt power/other l25 vsssen temp ah18 vtt power/other ac13 vtt power/other ah19 vtt power/other ah20 vtt power/other av18 vtt power/other ah21 vtt power/other av19 vtt power/other aj18 vtt power/other av20 vtt power/other aj19 vtt power/other av21 vtt power/other aj20 vtt power/other f14 xdpcomcres analog aj21 vtt power/other a11 xdpd[0]# xdp i/o ak18 vtt power/other b10 xdpd[1]# xdp i/o ak19 vtt power/other a14 xdpd[10]# xdp i/o ak20 vtt power/other a16 xdpd[11]# xdp i/o ak21 vtt power/other c16 xdpd[12]# xdp i/o al18 vtt power/other a15 xdpd[13]# xdp i/o al19 vtt power/other d16 xdpd[14]# xdp i/o al20 vtt power/other e16 xdpd[15]# xdp i/o al21 vtt power/other a10 xdpd[2]# xdp i/o am18 vtt power/other d13 xdpd[3]# xdp i/o am19 vtt power/other a12 xdpd[4]# xdp i/o am20 vtt power/other e14 xdpd[5]# xdp i/o am21 vtt power/other b13 xdpd[6]# xdp i/o table 8-2. intel 5000x chipset mch signals (by signal name) (sheet 18 of 19) ball no. signal name buffer type direction b all no. signal name buffer type direction
ballout and package information 454 intel ? 5000x chipset memory controller hub (mch) datasheet an18 vtt power/other b14 xdpd[7]# xdp i/o an19 vtt power/other d15 xdpd[8]# xdp i/o an20 vtt power/other b15 xdpd[9]# xdp i/o an21 vtt power/other c13 xdpdstbn# xdp i/o ap18 vtt power/other c14 xdpdstbp# xdp i/o ap19 vtt power/other g14 xdpodtcres analog ap20 vtt power/other a17 xdprdy# xdp i/o ap21 vtt power/other j15 xdpslwcres analog ar18 vtt power/other ar19 vtt power/other ar20 vtt power/other ar21 vtt power/other at18 vtt power/other at19 vtt power/other at20 vtt power/other at21 vtt power/other au18 vtt power/other au19 vtt power/other au20 vtt power/other au21 vtt power/other table 8-2. intel 5000x chipset mch signals (by signal name) (sheet 19 of 19) ball no. signal name buffer type direction ball no. signal name buffer type direction
intel ? 5000x chipset memory controller hub (mch) datasheet 455 ballout and package information 8.2 package information figure 8-5. bottom view
ballout and package information 456 intel ? 5000x chipset memory controller hub (mch) datasheet figure 8-6. top view
intel ? 5000x chipset memory controller hub (mch) datasheet 457 ballout and package information figure 8-7. package stackup
ballout and package information 458 intel ? 5000x chipset memory controller hub (mch) datasheet figure 8-8. notes

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